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target/arm: Use isar_feature function for testing AA32HPD feature

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Now we have moved ID_MMFR4 into the ARMISARegisters struct, we
can define and use an isar_feature for the presence of the
ARMv8.2-AA32HPD feature, rather than open-coding the test.

While we're here, correct a comment typo which missed an 'A'
from the feature name.

Backports commit 4036b7d1cd9fb1097a5f4bc24d7d31744256260f from qemu
This commit is contained in:
Peter Maydell 2020-03-21 18:48:43 -04:00 committed by Lioncash
parent 4693b2c011
commit 2ce106df33
2 changed files with 7 additions and 2 deletions
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5
qemu/target/arm/cpu.h
View file

@ -3399,6 +3399,11 @@ static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id)
FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf;
} }
static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id)
{
return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0;
}
/* /*
* 64-bit feature tests via id registers. * 64-bit feature tests via id registers.
*/ */

4
qemu/target/arm/helper.c
View file

@ -7208,8 +7208,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
} else { } else {
define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
define_arm_cp_regs(cpu, vmsa_cp_reginfo); define_arm_cp_regs(cpu, vmsa_cp_reginfo);
/* TTCBR2 is introduced with ARMv8.2-A32HPD. */ /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */
if (FIELD_EX32(cpu->isar.id_mmfr4, ID_MMFR4, HPDS) != 0) { if (cpu_isar_feature(aa32_hpd, cpu)) {
define_one_arm_cp_reg(cpu, &ttbcr2_reginfo); define_one_arm_cp_reg(cpu, &ttbcr2_reginfo);
} }
} }