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https://github.com/yuzu-emu/unicorn.git
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target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks
The isar_feature_aa32_pan and isar_feature_aa32_ats1e1 functions are supposed to be testing fields in ID_MMFR3; but a cut-and-paste error meant we were looking at MVFR0 instead. Fix the functions to look at the right register; this requires us to move at least id_mmfr3 to the ARMISARegisters struct; we choose to move all the ID_MMFRn registers for consistency. Backports commit 10054016eda1b13bdd8340d100fd029cc8b58f36 from qemu
This commit is contained in:
Peter Maydell
Lioncash
parent
e72fa1cb33
commit
4693b2c011
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@ -1183,9 +1183,9 @@ static void arm1136_r2_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_pfr1 = 0x1;
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cpu->isar.id_dfr0 = 0x2;
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cpu->id_afr0 = 0x3;
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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cpu->id_mmfr2 = 0x01222110;
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cpu->isar.id_mmfr0 = 0x01130003;
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cpu->isar.id_mmfr1 = 0x10030302;
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cpu->isar.id_mmfr2 = 0x01222110;
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cpu->isar.id_isar0 = 0x00140011;
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cpu->isar.id_isar1 = 0x12002111;
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cpu->isar.id_isar2 = 0x11231111;
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@ -1215,9 +1215,9 @@ static void arm1136_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_pfr1 = 0x1;
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cpu->isar.id_dfr0 = 0x2;
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cpu->id_afr0 = 0x3;
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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cpu->id_mmfr2 = 0x01222110;
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cpu->isar.id_mmfr0 = 0x01130003;
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cpu->isar.id_mmfr1 = 0x10030302;
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cpu->isar.id_mmfr2 = 0x01222110;
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cpu->isar.id_isar0 = 0x00140011;
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cpu->isar.id_isar1 = 0x12002111;
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cpu->isar.id_isar2 = 0x11231111;
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@ -1248,9 +1248,9 @@ static void arm1176_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_pfr1 = 0x11;
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cpu->isar.id_dfr0 = 0x33;
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cpu->id_afr0 = 0;
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cpu->id_mmfr0 = 0x01130003;
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cpu->id_mmfr1 = 0x10030302;
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cpu->id_mmfr2 = 0x01222100;
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cpu->isar.id_mmfr0 = 0x01130003;
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cpu->isar.id_mmfr1 = 0x10030302;
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cpu->isar.id_mmfr2 = 0x01222100;
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cpu->isar.id_isar0 = 0x0140011;
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cpu->isar.id_isar1 = 0x12002111;
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cpu->isar.id_isar2 = 0x11231121;
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@ -1278,9 +1278,9 @@ static void arm11mpcore_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_pfr1 = 0x1;
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cpu->isar.id_dfr0 = 0;
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cpu->id_afr0 = 0x2;
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cpu->id_mmfr0 = 0x01100103;
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cpu->id_mmfr1 = 0x10020302;
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cpu->id_mmfr2 = 0x01222000;
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cpu->isar.id_mmfr0 = 0x01100103;
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cpu->isar.id_mmfr1 = 0x10020302;
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cpu->isar.id_mmfr2 = 0x01222000;
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cpu->isar.id_isar0 = 0x00100011;
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cpu->isar.id_isar1 = 0x12002111;
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cpu->isar.id_isar2 = 0x11221011;
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@ -1310,10 +1310,10 @@ static void cortex_m3_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_pfr1 = 0x00000200;
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cpu->isar.id_dfr0 = 0x00100000;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x00000030;
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cpu->id_mmfr1 = 0x00000000;
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cpu->id_mmfr2 = 0x00000000;
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cpu->id_mmfr3 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x00000030;
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cpu->isar.id_mmfr1 = 0x00000000;
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cpu->isar.id_mmfr2 = 0x00000000;
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cpu->isar.id_mmfr3 = 0x00000000;
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cpu->isar.id_isar0 = 0x01141110;
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cpu->isar.id_isar1 = 0x02111000;
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cpu->isar.id_isar2 = 0x21112231;
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@ -1341,10 +1341,10 @@ static void cortex_m4_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_pfr1 = 0x00000200;
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cpu->isar.id_dfr0 = 0x00100000;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x00000030;
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cpu->id_mmfr1 = 0x00000000;
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cpu->id_mmfr2 = 0x00000000;
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cpu->id_mmfr3 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x00000030;
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cpu->isar.id_mmfr1 = 0x00000000;
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cpu->isar.id_mmfr2 = 0x00000000;
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cpu->isar.id_mmfr3 = 0x00000000;
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cpu->isar.id_isar0 = 0x01141110;
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cpu->isar.id_isar1 = 0x02111000;
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cpu->isar.id_isar2 = 0x21112231;
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@ -1372,10 +1372,10 @@ static void cortex_m7_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_pfr1 = 0x00000200;
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cpu->isar.id_dfr0 = 0x00100000;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x00100030;
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cpu->id_mmfr1 = 0x00000000;
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cpu->id_mmfr2 = 0x01000000;
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cpu->id_mmfr3 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x00100030;
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cpu->isar.id_mmfr1 = 0x00000000;
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cpu->isar.id_mmfr2 = 0x01000000;
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cpu->isar.id_mmfr3 = 0x00000000;
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cpu->isar.id_isar0 = 0x01101110;
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cpu->isar.id_isar1 = 0x02112000;
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cpu->isar.id_isar2 = 0x20232231;
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@ -1406,10 +1406,10 @@ static void cortex_m33_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_pfr1 = 0x00000210;
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cpu->isar.id_dfr0 = 0x00200000;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x00101F40;
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cpu->id_mmfr1 = 0x00000000;
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cpu->id_mmfr2 = 0x01000000;
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cpu->id_mmfr3 = 0x00000000;
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cpu->isar.id_mmfr0 = 0x00101F40;
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cpu->isar.id_mmfr1 = 0x00000000;
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cpu->isar.id_mmfr2 = 0x01000000;
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cpu->isar.id_mmfr3 = 0x00000000;
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cpu->isar.id_isar0 = 0x01101110;
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cpu->isar.id_isar1 = 0x02212000;
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cpu->isar.id_isar2 = 0x20232232;
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@ -1456,10 +1456,10 @@ static void cortex_r5_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_pfr1 = 0x001;
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cpu->isar.id_dfr0 = 0x010400;
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cpu->id_afr0 = 0x0;
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cpu->id_mmfr0 = 0x0210030;
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cpu->id_mmfr1 = 0x00000000;
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cpu->id_mmfr2 = 0x01200000;
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cpu->id_mmfr3 = 0x0211;
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cpu->isar.id_mmfr0 = 0x0210030;
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cpu->isar.id_mmfr1 = 0x00000000;
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cpu->isar.id_mmfr2 = 0x01200000;
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cpu->isar.id_mmfr3 = 0x0211;
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cpu->isar.id_isar0 = 0x02101111;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232141;
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@ -1511,10 +1511,10 @@ static void cortex_a8_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_pfr1 = 0x11;
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cpu->isar.id_dfr0 = 0x400;
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cpu->id_afr0 = 0;
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cpu->id_mmfr0 = 0x31100003;
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cpu->id_mmfr1 = 0x20000000;
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cpu->id_mmfr2 = 0x01202000;
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cpu->id_mmfr3 = 0x11;
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cpu->isar.id_mmfr0 = 0x31100003;
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cpu->isar.id_mmfr1 = 0x20000000;
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cpu->isar.id_mmfr2 = 0x01202000;
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cpu->isar.id_mmfr3 = 0x11;
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cpu->isar.id_isar0 = 0x00101111;
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cpu->isar.id_isar1 = 0x12112111;
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cpu->isar.id_isar2 = 0x21232031;
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@ -1584,10 +1584,10 @@ static void cortex_a9_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_pfr1 = 0x11;
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cpu->isar.id_dfr0 = 0x000;
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cpu->id_afr0 = 0;
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cpu->id_mmfr0 = 0x00100103;
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cpu->id_mmfr1 = 0x20000000;
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cpu->id_mmfr2 = 0x01230000;
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cpu->id_mmfr3 = 0x00002111;
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cpu->isar.id_mmfr0 = 0x00100103;
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cpu->isar.id_mmfr1 = 0x20000000;
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cpu->isar.id_mmfr2 = 0x01230000;
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cpu->isar.id_mmfr3 = 0x00002111;
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cpu->isar.id_isar0 = 0x00101111;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232041;
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@ -1647,10 +1647,10 @@ static void cortex_a7_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_pfr1 = 0x00011011;
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cpu->isar.id_dfr0 = 0x02010555;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10101105;
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cpu->id_mmfr1 = 0x40000000;
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cpu->id_mmfr2 = 0x01240000;
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cpu->id_mmfr3 = 0x02102211;
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cpu->isar.id_mmfr0 = 0x10101105;
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cpu->isar.id_mmfr1 = 0x40000000;
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cpu->isar.id_mmfr2 = 0x01240000;
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cpu->isar.id_mmfr3 = 0x02102211;
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/* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but
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* table 4-41 gives 0x02101110, which includes the arm div insns.
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*/
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@ -1693,10 +1693,10 @@ static void cortex_a15_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_pfr1 = 0x00011011;
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cpu->isar.id_dfr0 = 0x02010555;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10201105;
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cpu->id_mmfr1 = 0x20000000;
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cpu->id_mmfr2 = 0x01240000;
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cpu->id_mmfr3 = 0x02102211;
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cpu->isar.id_mmfr0 = 0x10201105;
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cpu->isar.id_mmfr1 = 0x20000000;
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cpu->isar.id_mmfr2 = 0x01240000;
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cpu->isar.id_mmfr3 = 0x02102211;
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cpu->isar.id_isar0 = 0x02101110;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232041;
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@ -1928,13 +1928,13 @@ static void arm_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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t = FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */
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cpu->isar.mvfr2 = t;
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t = cpu->id_mmfr3;
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t = cpu->isar.id_mmfr3;
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t = FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */
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cpu->id_mmfr3 = t;
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cpu->isar.id_mmfr3 = t;
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t = cpu->id_mmfr4;
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t = cpu->isar.id_mmfr4;
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t = FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */
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cpu->id_mmfr4 = t;
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cpu->isar.id_mmfr4 = t;
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}
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}
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#endif
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@ -834,6 +834,11 @@ struct ARMCPU {
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uint32_t id_isar4;
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uint32_t id_isar5;
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uint32_t id_isar6;
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uint32_t id_mmfr0;
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uint32_t id_mmfr1;
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uint32_t id_mmfr2;
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uint32_t id_mmfr3;
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uint32_t id_mmfr4;
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uint32_t mvfr0;
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uint32_t mvfr1;
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uint32_t mvfr2;
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@ -859,11 +864,6 @@ struct ARMCPU {
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uint64_t pmceid0;
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uint64_t pmceid1;
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uint32_t id_afr0;
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uint32_t id_mmfr0;
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uint32_t id_mmfr1;
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uint32_t id_mmfr2;
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uint32_t id_mmfr3;
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uint32_t id_mmfr4;
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uint64_t id_aa64afr0;
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uint64_t id_aa64afr1;
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uint32_t clidr;
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@ -3377,12 +3377,12 @@ static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id)
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static inline bool isar_feature_aa32_pan(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) != 0;
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return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) != 0;
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}
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static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id)
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{
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return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >= 2;
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return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2;
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}
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static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id)
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@ -118,10 +118,10 @@ static void aarch64_a57_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_pfr1 = 0x00011011;
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cpu->isar.id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10101105;
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cpu->id_mmfr1 = 0x40000000;
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cpu->id_mmfr2 = 0x01260000;
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cpu->id_mmfr3 = 0x02102211;
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cpu->isar.id_mmfr0 = 0x10101105;
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cpu->isar.id_mmfr1 = 0x40000000;
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cpu->isar.id_mmfr2 = 0x01260000;
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cpu->isar.id_mmfr3 = 0x02102211;
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cpu->isar.id_isar0 = 0x02101110;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232042;
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@ -169,10 +169,10 @@ static void aarch64_a53_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_pfr1 = 0x00011011;
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cpu->isar.id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10101105;
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cpu->id_mmfr1 = 0x40000000;
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cpu->id_mmfr2 = 0x01260000;
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cpu->id_mmfr3 = 0x02102211;
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cpu->isar.id_mmfr0 = 0x10101105;
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cpu->isar.id_mmfr1 = 0x40000000;
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cpu->isar.id_mmfr2 = 0x01260000;
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cpu->isar.id_mmfr3 = 0x02102211;
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cpu->isar.id_isar0 = 0x02101110;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232042;
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@ -219,10 +219,10 @@ static void aarch64_a72_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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cpu->id_pfr1 = 0x00011011;
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cpu->isar.id_dfr0 = 0x03010066;
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cpu->id_afr0 = 0x00000000;
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cpu->id_mmfr0 = 0x10201105;
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cpu->id_mmfr1 = 0x40000000;
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cpu->id_mmfr2 = 0x01260000;
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cpu->id_mmfr3 = 0x02102211;
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cpu->isar.id_mmfr0 = 0x10201105;
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cpu->isar.id_mmfr1 = 0x40000000;
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cpu->isar.id_mmfr2 = 0x01260000;
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cpu->isar.id_mmfr3 = 0x02102211;
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cpu->isar.id_isar0 = 0x02101110;
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cpu->isar.id_isar1 = 0x13112111;
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cpu->isar.id_isar2 = 0x21232042;
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@ -343,9 +343,9 @@ static void aarch64_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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u = FIELD_DP32(u, ID_ISAR6, SPECRES, 1);
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cpu->isar.id_isar6 = u;
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u = cpu->id_mmfr3;
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u = cpu->isar.id_mmfr3;
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u = FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */
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cpu->id_mmfr3 = u;
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cpu->isar.id_mmfr3 = u;
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u = cpu->isar.id_aa64dfr0;
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u = FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
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@ -6711,22 +6711,22 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
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.access = PL1_R, .type = ARM_CP_CONST,
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.accessfn = access_aa32_tid3,
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.resetvalue = cpu->id_mmfr0 },
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.resetvalue = cpu->isar.id_mmfr0 },
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{ .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
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.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
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.access = PL1_R, .type = ARM_CP_CONST,
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.accessfn = access_aa32_tid3,
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.resetvalue = cpu->id_mmfr1 },
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.resetvalue = cpu->isar.id_mmfr1 },
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{ .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
.accessfn = access_aa32_tid3,
|
||||
.resetvalue = cpu->id_mmfr2 },
|
||||
.resetvalue = cpu->isar.id_mmfr2 },
|
||||
{ .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
.accessfn = access_aa32_tid3,
|
||||
.resetvalue = cpu->id_mmfr3 },
|
||||
.resetvalue = cpu->isar.id_mmfr3 },
|
||||
{ .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
|
|
@ -6761,7 +6761,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
|
|||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
.accessfn = access_aa32_tid3,
|
||||
.resetvalue = cpu->id_mmfr4 },
|
||||
.resetvalue = cpu->isar.id_mmfr4 },
|
||||
{ .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,
|
||||
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
|
||||
.access = PL1_R, .type = ARM_CP_CONST,
|
||||
|
|
@ -7209,7 +7209,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
|
|||
define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
|
||||
define_arm_cp_regs(cpu, vmsa_cp_reginfo);
|
||||
/* TTCBR2 is introduced with ARMv8.2-A32HPD. */
|
||||
if (FIELD_EX32(cpu->id_mmfr4, ID_MMFR4, HPDS) != 0) {
|
||||
if (FIELD_EX32(cpu->isar.id_mmfr4, ID_MMFR4, HPDS) != 0) {
|
||||
define_one_arm_cp_reg(cpu, &ttbcr2_reginfo);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue