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target/arm: Use aarch32_cpsr_valid_mask in helper_exception_return
Using ~0 as the mask on the aarch64->aarch32 exception return was not even as correct as the CPSR_ERET_MASK that we had used on the aarch32->aarch32 exception return. Backports commit d203cabd1bd12f31c9df0b5737421ba67b96857b from qemu
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@ -957,7 +957,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
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{
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int cur_el = arm_current_el(env);
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unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el);
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uint32_t spsr = env->banked_spsr[spsr_idx];
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uint32_t mask, spsr = env->banked_spsr[spsr_idx];
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int new_el;
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bool return_to_aa64 = (spsr & PSTATE_nRW) == 0;
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@ -1013,7 +1013,8 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc)
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* will sort the register banks out for us, and we've already
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* caught all the bad-mode cases in el_from_spsr().
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*/
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cpsr_write(env, spsr, ~0, CPSRWriteRaw);
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mask = aarch32_cpsr_valid_mask(env->features, &env_archcpu(env)->isar);
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cpsr_write(env, spsr, mask, CPSRWriteRaw);
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if (!arm_singlestep_active(env)) {
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env->uncached_cpsr &= ~PSTATE_SS;
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}
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