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tcg: Add support for vector compare select

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Perform a per-element conditional move. This combination operation is
easier to implement on some host vector units than plain cmp+bitsel.
Omit the usual gvec interface, as this is intended to be used by
target-specific gvec expansion call-backs.

Backports commit f75da2988eb2457fa23d006d573220c5c680ec4e from qemu
This commit is contained in:
Richard Henderson 2019-05-24 18:21:10 -04:00 committed by Lioncash
parent ca58be9cb4
commit 2ea6dfbd63
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
24 changed files with 92 additions and 1 deletions
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1
qemu/aarch64.h
View file

@ -2805,6 +2805,7 @@
#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_aarch64
#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_aarch64
#define tcg_gen_cmp_vec tcg_gen_cmp_vec_aarch64
#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_aarch64
#define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_aarch64
#define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_aarch64
#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_aarch64

1
qemu/aarch64eb.h
View file

@ -2805,6 +2805,7 @@
#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_aarch64eb
#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_aarch64eb
#define tcg_gen_cmp_vec tcg_gen_cmp_vec_aarch64eb
#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_aarch64eb
#define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_aarch64eb
#define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_aarch64eb
#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_aarch64eb

1
qemu/arm.h
View file

@ -2805,6 +2805,7 @@
#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_arm
#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_arm
#define tcg_gen_cmp_vec tcg_gen_cmp_vec_arm
#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_arm
#define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_arm
#define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_arm
#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_arm

1
qemu/armeb.h
View file

@ -2805,6 +2805,7 @@
#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_armeb
#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_armeb
#define tcg_gen_cmp_vec tcg_gen_cmp_vec_armeb
#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_armeb
#define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_armeb
#define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_armeb
#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_armeb

1
qemu/header_gen.py
View file

@ -2811,6 +2811,7 @@ symbols = (
'tcg_gen_clzi_i32',
'tcg_gen_clzi_i64',
'tcg_gen_cmp_vec',
'tcg_gen_cmpsel_vec',
'tcg_gen_ctpop_i32',
'tcg_gen_ctpop_i64',
'tcg_gen_ctz_i32',

1
qemu/m68k.h
View file

@ -2805,6 +2805,7 @@
#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_m68k
#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_m68k
#define tcg_gen_cmp_vec tcg_gen_cmp_vec_m68k
#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_m68k
#define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_m68k
#define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_m68k
#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_m68k

1
qemu/mips.h
View file

@ -2805,6 +2805,7 @@
#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_mips
#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_mips
#define tcg_gen_cmp_vec tcg_gen_cmp_vec_mips
#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_mips
#define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_mips
#define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_mips
#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_mips

1
qemu/mips64.h
View file

@ -2805,6 +2805,7 @@
#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_mips64
#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_mips64
#define tcg_gen_cmp_vec tcg_gen_cmp_vec_mips64
#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_mips64
#define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_mips64
#define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_mips64
#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_mips64

1
qemu/mips64el.h
View file

@ -2805,6 +2805,7 @@
#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_mips64el
#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_mips64el
#define tcg_gen_cmp_vec tcg_gen_cmp_vec_mips64el
#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_mips64el
#define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_mips64el
#define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_mips64el
#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_mips64el

1
qemu/mipsel.h
View file

@ -2805,6 +2805,7 @@
#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_mipsel
#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_mipsel
#define tcg_gen_cmp_vec tcg_gen_cmp_vec_mipsel
#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_mipsel
#define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_mipsel
#define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_mipsel
#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_mipsel

1
qemu/powerpc.h
View file

@ -2805,6 +2805,7 @@
#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_powerpc
#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_powerpc
#define tcg_gen_cmp_vec tcg_gen_cmp_vec_powerpc
#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_powerpc
#define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_powerpc
#define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_powerpc
#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_powerpc

1
qemu/riscv32.h
View file

@ -2805,6 +2805,7 @@
#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_riscv32
#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_riscv32
#define tcg_gen_cmp_vec tcg_gen_cmp_vec_riscv32
#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_riscv32
#define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_riscv32
#define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_riscv32
#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_riscv32

1
qemu/riscv64.h
View file

@ -2805,6 +2805,7 @@
#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_riscv64
#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_riscv64
#define tcg_gen_cmp_vec tcg_gen_cmp_vec_riscv64
#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_riscv64
#define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_riscv64
#define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_riscv64
#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_riscv64

1
qemu/sparc.h
View file

@ -2805,6 +2805,7 @@
#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_sparc
#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_sparc
#define tcg_gen_cmp_vec tcg_gen_cmp_vec_sparc
#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_sparc
#define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_sparc
#define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_sparc
#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_sparc

1
qemu/sparc64.h
View file

@ -2805,6 +2805,7 @@
#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_sparc64
#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_sparc64
#define tcg_gen_cmp_vec tcg_gen_cmp_vec_sparc64
#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_sparc64
#define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_sparc64
#define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_sparc64
#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_sparc64

7
qemu/tcg/README
View file

@ -626,6 +626,13 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
Bitwise select, v0 = (v2 & v1) | (v3 & ~v1), across the entire vector.
* cmpsel_vec v0, c1, c2, v3, v4, cond
Select elements based on comparison results:
for (i = 0; i < n; ++i) {
v0[i] = (c1[i] cond c2[i]) ? v3[i] : v4[i].
}
*********
Note 1: Some shortcuts are defined when the last operand is known to be

1
qemu/tcg/aarch64/tcg-target.h
View file

@ -141,6 +141,7 @@ typedef enum {
#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 0
#define TCG_TARGET_HAS_cmpsel_vec 0
#define TCG_TARGET_DEFAULT_MO (0)
#define TCG_TARGET_HAS_MEMORY_BSWAP 1

1
qemu/tcg/i386/tcg-target.h
View file

@ -224,6 +224,7 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_sat_vec 1
#define TCG_TARGET_HAS_minmax_vec 1
#define TCG_TARGET_HAS_bitsel_vec 0
#define TCG_TARGET_HAS_cmpsel_vec 0
#define TCG_TARGET_deposit_i32_valid(ofs, len) \
(((ofs) == 0 && (len) == 8) || ((ofs) == 8 && (len) == 8) || \

59
qemu/tcg/tcg-op-vec.c
View file

@ -120,6 +120,11 @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list,
continue;
}
break;
case INDEX_op_cmpsel_vec:
if (tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece)) {
continue;
}
break;
default:
break;
}
@ -160,6 +165,20 @@ void vec_gen_4(TCGContext *s, TCGOpcode opc, TCGType type, unsigned vece,
op->args[3] = c;
}
static void vec_gen_6(TCGContext *s, TCGOpcode opc, TCGType type, unsigned vece, TCGArg r,
TCGArg a, TCGArg b, TCGArg c, TCGArg d, TCGArg e)
{
TCGOp *op = tcg_emit_op(s, opc);
TCGOP_VECL(op) = type - TCG_TYPE_V64;
TCGOP_VECE(op) = vece;
op->args[0] = r;
op->args[1] = a;
op->args[2] = b;
op->args[3] = c;
op->args[4] = d;
op->args[5] = e;
}
static void vec_gen_op2(TCGContext *s, TCGOpcode opc, unsigned vece, TCGv_vec r, TCGv_vec a)
{
TCGTemp *rt = tcgv_vec_temp(s, r);
@ -718,3 +737,43 @@ void tcg_gen_bitsel_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a,
tcg_temp_free_vec(s, t);
}
}
void tcg_gen_cmpsel_vec(TCGContext *s, TCGCond cond, unsigned vece, TCGv_vec r,
TCGv_vec a, TCGv_vec b, TCGv_vec c, TCGv_vec d)
{
TCGTemp *rt = tcgv_vec_temp(s, r);
TCGTemp *at = tcgv_vec_temp(s, a);
TCGTemp *bt = tcgv_vec_temp(s, b);
TCGTemp *ct = tcgv_vec_temp(s, c);
TCGTemp *dt = tcgv_vec_temp(s, d);
TCGArg ri = temp_arg(rt);
TCGArg ai = temp_arg(at);
TCGArg bi = temp_arg(bt);
TCGArg ci = temp_arg(ct);
TCGArg di = temp_arg(dt);
TCGType type = rt->base_type;
const TCGOpcode *hold_list;
int can;
tcg_debug_assert(at->base_type >= type);
tcg_debug_assert(bt->base_type >= type);
tcg_debug_assert(ct->base_type >= type);
tcg_debug_assert(dt->base_type >= type);
tcg_assert_listed_vecop(s, INDEX_op_cmpsel_vec);
hold_list = tcg_swap_vecop_list(s, NULL);
can = tcg_can_emit_vec_op(INDEX_op_cmpsel_vec, type, vece);
if (can > 0) {
vec_gen_6(s, INDEX_op_cmpsel_vec, type, vece, ri, ai, bi, ci, di, cond);
} else if (can < 0) {
tcg_expand_vec_op(s, INDEX_op_cmpsel_vec, type, vece,
ri, ai, bi, ci, di, cond);
} else {
TCGv_vec t = tcg_temp_new_vec(s, type);
tcg_gen_cmp_vec(s, cond, vece, t, a, b);
tcg_gen_bitsel_vec(s, vece, r, t, c, d);
tcg_temp_free_vec(s, t);
}
tcg_swap_vecop_list(s, hold_list);
}

2
qemu/tcg/tcg-op.h
View file

@ -1015,6 +1015,8 @@ void tcg_gen_cmp_vec(TCGContext *, TCGCond cond, unsigned vece, TCGv_vec r,
void tcg_gen_bitsel_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a,
TCGv_vec b, TCGv_vec c);
void tcg_gen_cmpsel_vec(TCGContext *, TCGCond cond, unsigned vece, TCGv_vec r,
TCGv_vec a, TCGv_vec b, TCGv_vec c, TCGv_vec d);
void tcg_gen_ld_vec(TCGContext *, TCGv_vec r, TCGv_ptr base, TCGArg offset);
void tcg_gen_st_vec(TCGContext *, TCGv_vec r, TCGv_ptr base, TCGArg offset);

1
qemu/tcg/tcg-opc.h
View file

@ -262,6 +262,7 @@ DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
DEF(cmp_vec, 1, 2, 1, IMPLVEC)
DEF(bitsel_vec, 1, 3, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_bitsel_vec))
DEF(cmpsel_vec, 1, 4, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_cmpsel_vec))
DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)

3
qemu/tcg/tcg.c
View file

@ -1090,6 +1090,8 @@ bool tcg_op_supported(TCGOpcode op)
return have_vec && TCG_TARGET_HAS_minmax_vec;
case INDEX_op_bitsel_vec:
return have_vec && TCG_TARGET_HAS_bitsel_vec;
case INDEX_op_cmpsel_vec:
return have_vec && TCG_TARGET_HAS_cmpsel_vec;
default:
tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS);
@ -1470,6 +1472,7 @@ static void tcg_dump_ops(TCGContext *s, bool have_prefs)
case INDEX_op_setcond_i64:
case INDEX_op_movcond_i64:
case INDEX_op_cmp_vec:
case INDEX_op_cmpsel_vec:
if (op->args[k] < ARRAY_SIZE(cond_name)
&& cond_name[op->args[k]]) {
col += qemu_log(",%s", cond_name[op->args[k++]]);

3
qemu/tcg/tcg.h
View file

@ -191,6 +191,7 @@ typedef uint64_t TCGRegSet;
#define TCG_TARGET_HAS_sat_vec 0
#define TCG_TARGET_HAS_minmax_vec 0
#define TCG_TARGET_HAS_bitsel_vec 0
#define TCG_TARGET_HAS_cmpsel_vec 0
#else
#define TCG_TARGET_MAYBE_vec 1
#endif
@ -1177,7 +1178,7 @@ static inline TCGv_ptr tcg_temp_local_new_ptr(TCGContext *s)
}
// UNICORN: Added
#define TCG_OP_DEFS_TABLE_SIZE 184
#define TCG_OP_DEFS_TABLE_SIZE 185
extern const TCGOpDef tcg_op_defs_org[TCG_OP_DEFS_TABLE_SIZE];
typedef struct TCGTargetOpDef {

1
qemu/x86_64.h
View file

@ -2805,6 +2805,7 @@
#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_x86_64
#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_x86_64
#define tcg_gen_cmp_vec tcg_gen_cmp_vec_x86_64
#define tcg_gen_cmpsel_vec tcg_gen_cmpsel_vec_x86_64
#define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_x86_64
#define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_x86_64
#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_x86_64