yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2024-12-22 20:25:38 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/riscv: vector iota instruction

Browse source 
Backports 78d90cfe859c8f5bd7baa0d41a4b5126e08eac24
This commit is contained in:
LIU Zhiwei 2021-03-07 12:27:07 -05:00 committed by Lioncash
parent ec24e09ce7
commit 2f7cdaee7b
7 changed files with 76 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
qemu/header_gen.py
View file

@ -7263,6 +7263,10 @@ riscv_symbols = (
'helper_vmsbf_m',
'helper_vmsif_m',
'helper_vmsof_m',
'helper_viota_m_b',
'helper_viota_m_h',
'helper_viota_m_w',
'helper_viota_m_d',
'pmp_hart_has_privs',
'pmpaddr_csr_read',
'pmpaddr_csr_write',

4
qemu/riscv32.h
View file

@ -4699,6 +4699,10 @@
#define helper_vmsbf_m helper_vmsbf_m_riscv32
#define helper_vmsif_m helper_vmsif_m_riscv32
#define helper_vmsof_m helper_vmsof_m_riscv32
#define helper_viota_m_b helper_viota_m_b_riscv32
#define helper_viota_m_h helper_viota_m_h_riscv32
#define helper_viota_m_w helper_viota_m_w_riscv32
#define helper_viota_m_d helper_viota_m_d_riscv32
#define pmp_hart_has_privs pmp_hart_has_privs_riscv32
#define pmpaddr_csr_read pmpaddr_csr_read_riscv32
#define pmpaddr_csr_write pmpaddr_csr_write_riscv32

4
qemu/riscv64.h
View file

@ -4699,6 +4699,10 @@
#define helper_vmsbf_m helper_vmsbf_m_riscv64
#define helper_vmsif_m helper_vmsif_m_riscv64
#define helper_vmsof_m helper_vmsof_m_riscv64
#define helper_viota_m_b helper_viota_m_b_riscv64
#define helper_viota_m_h helper_viota_m_h_riscv64
#define helper_viota_m_w helper_viota_m_w_riscv64
#define helper_viota_m_d helper_viota_m_d_riscv64
#define pmp_hart_has_privs pmp_hart_has_privs_riscv64
#define pmpaddr_csr_read pmpaddr_csr_read_riscv64
#define pmpaddr_csr_write pmpaddr_csr_write_riscv64

5
qemu/target/riscv/helper.h
View file

@ -1112,3 +1112,8 @@ DEF_HELPER_4(vmfirst_m, tl, ptr, ptr, env, i32)
DEF_HELPER_5(vmsbf_m, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vmsif_m, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(vmsof_m, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(viota_m_b, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(viota_m_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(viota_m_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(viota_m_d, void, ptr, ptr, ptr, env, i32)

1
qemu/target/riscv/insn32.decode
View file

@ -560,6 +560,7 @@ vmfirst_m 010101 . ..... ----- 010 ..... 1010111 @r2_vm
vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm
vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm
vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm
viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r

29
qemu/target/riscv/insn_trans/trans_rvv.inc.c
View file

@ -2524,3 +2524,32 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \
GEN_M_TRANS(vmsbf_m)
GEN_M_TRANS(vmsif_m)
GEN_M_TRANS(vmsof_m)
/* Vector Iota Instruction */
static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
if (vext_check_isa_ill(s) &&
vext_check_reg(s, a->rd, false) &&
vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2, 1) &&
(a->vm != 0 || a->rd != 0)) {
uint32_t data = 0;
TCGLabel *over = gen_new_label(tcg_ctx);
tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_vl_risc, 0, over);
data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
static gen_helper_gvec_3_ptr * const fns[4] = {
gen_helper_viota_m_b, gen_helper_viota_m_h,
gen_helper_viota_m_w, gen_helper_viota_m_d,
};
tcg_gen_gvec_3_ptr(tcg_ctx, vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs2), tcg_ctx->cpu_env, 0,
s->vlen / 8, data, fns[s->sew]);
gen_set_label(tcg_ctx, over);
return true;
}
return false;
}

29
qemu/target/riscv/vector_helper.c
View file

@ -4620,3 +4620,32 @@ void HELPER(vmsof_m)(void *vd, void *v0, void *vs2, CPURISCVState *env,
{
vmsetm(vd, v0, vs2, env, desc, ONLY_FIRST);
}
/* Vector Iota Instruction */
#define GEN_VEXT_VIOTA_M(NAME, ETYPE, H, CLEAR_FN) \
void HELPER(NAME)(void *vd, void *v0, void *vs2, CPURISCVState *env, \
uint32_t desc) \
{ \
uint32_t mlen = vext_mlen(desc); \
uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
uint32_t sum = 0; \
int i; \
\
for (i = 0; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, mlen, i)) { \
continue; \
} \
*((ETYPE *)vd + H(i)) = sum; \
if (vext_elem_mask(vs2, mlen, i)) { \
sum++; \
} \
} \
CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1, clearb)
GEN_VEXT_VIOTA_M(viota_m_h, uint16_t, H2, clearh)
GEN_VEXT_VIOTA_M(viota_m_w, uint32_t, H4, clearl)
GEN_VEXT_VIOTA_M(viota_m_d, uint64_t, H8, clearq)