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tcg/arm: Fully convert tcg_target_op_def
Backports commit 7536b82d28876d1ffe0359667b28c93d49386fa0 from qemu
This commit is contained in:
Richard Henderson
Lioncash
parent
47ed20fdd4
commit
3094e7927e
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@ -2060,91 +2060,102 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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}
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}
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static const TCGTargetOpDef arm_op_defs[] = {
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{ INDEX_op_exit_tb, { } },
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{ INDEX_op_goto_tb, { } },
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{ INDEX_op_br, { } },
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{ INDEX_op_goto_ptr, { "r" } },
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{ INDEX_op_ld8u_i32, { "r", "r" } },
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{ INDEX_op_ld8s_i32, { "r", "r" } },
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{ INDEX_op_ld16u_i32, { "r", "r" } },
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{ INDEX_op_ld16s_i32, { "r", "r" } },
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{ INDEX_op_ld_i32, { "r", "r" } },
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{ INDEX_op_st8_i32, { "r", "r" } },
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{ INDEX_op_st16_i32, { "r", "r" } },
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{ INDEX_op_st_i32, { "r", "r" } },
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/* TODO: "r", "r", "ri" */
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{ INDEX_op_add_i32, { "r", "r", "rIN" } },
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{ INDEX_op_sub_i32, { "r", "rI", "rIN" } },
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{ INDEX_op_mul_i32, { "r", "r", "r" } },
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{ INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
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{ INDEX_op_muls2_i32, { "r", "r", "r", "r" } },
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{ INDEX_op_and_i32, { "r", "r", "rIK" } },
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{ INDEX_op_andc_i32, { "r", "r", "rIK" } },
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{ INDEX_op_or_i32, { "r", "r", "rI" } },
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{ INDEX_op_xor_i32, { "r", "r", "rI" } },
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{ INDEX_op_neg_i32, { "r", "r" } },
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{ INDEX_op_not_i32, { "r", "r" } },
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{ INDEX_op_shl_i32, { "r", "r", "ri" } },
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{ INDEX_op_shr_i32, { "r", "r", "ri" } },
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{ INDEX_op_sar_i32, { "r", "r", "ri" } },
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{ INDEX_op_rotl_i32, { "r", "r", "ri" } },
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{ INDEX_op_rotr_i32, { "r", "r", "ri" } },
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{ INDEX_op_clz_i32, { "r", "r", "rIK" } },
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{ INDEX_op_ctz_i32, { "r", "r", "rIK" } },
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{ INDEX_op_brcond_i32, { "r", "rIN" } },
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{ INDEX_op_setcond_i32, { "r", "r", "rIN" } },
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{ INDEX_op_movcond_i32, { "r", "r", "rIN", "rIK", "0" } },
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{ INDEX_op_add2_i32, { "r", "r", "r", "r", "rIN", "rIK" } },
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{ INDEX_op_sub2_i32, { "r", "r", "rI", "rI", "rIN", "rIK" } },
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{ INDEX_op_brcond2_i32, { "r", "r", "rIN", "rIN" } },
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{ INDEX_op_setcond2_i32, { "r", "r", "r", "rIN", "rIN" } },
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#if TARGET_LONG_BITS == 32
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{ INDEX_op_qemu_ld_i32, { "r", "l" } },
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{ INDEX_op_qemu_ld_i64, { "r", "r", "l" } },
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{ INDEX_op_qemu_st_i32, { "s", "s" } },
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{ INDEX_op_qemu_st_i64, { "s", "s", "s" } },
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#else
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{ INDEX_op_qemu_ld_i32, { "r", "l", "l" } },
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{ INDEX_op_qemu_ld_i64, { "r", "r", "l", "l" } },
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{ INDEX_op_qemu_st_i32, { "s", "s", "s" } },
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{ INDEX_op_qemu_st_i64, { "s", "s", "s", "s" } },
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#endif
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{ INDEX_op_bswap16_i32, { "r", "r" } },
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{ INDEX_op_bswap32_i32, { "r", "r" } },
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{ INDEX_op_ext8s_i32, { "r", "r" } },
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{ INDEX_op_ext16s_i32, { "r", "r" } },
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{ INDEX_op_ext16u_i32, { "r", "r" } },
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{ INDEX_op_deposit_i32, { "r", "0", "rZ" } },
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{ INDEX_op_extract_i32, { "r", "r" } },
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{ INDEX_op_sextract_i32, { "r", "r" } },
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{ INDEX_op_div_i32, { "r", "r", "r" } },
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{ INDEX_op_divu_i32, { "r", "r", "r" } },
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{ INDEX_op_mb, { } },
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{ -1 },
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};
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static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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{
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int i, n = ARRAY_SIZE(arm_op_defs);
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static const TCGTargetOpDef r = { 0, { "r" } };
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static const TCGTargetOpDef r_r = { 0, { "r", "r" } };
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static const TCGTargetOpDef s_s = { 0, { "s", "s" } };
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static const TCGTargetOpDef r_l = { 0, { "r", "l" } };
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static const TCGTargetOpDef r_r_r = { 0, { "r", "r", "r" } };
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static const TCGTargetOpDef r_r_l = { 0, { "r", "r", "l" } };
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static const TCGTargetOpDef r_l_l = { 0, { "r", "l", "l" } };
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static const TCGTargetOpDef s_s_s = { 0, { "s", "s", "s" } };
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static const TCGTargetOpDef r_r_ri = { 0, { "r", "r", "ri" } };
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static const TCGTargetOpDef r_r_rI = { 0, { "r", "r", "rI" } };
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static const TCGTargetOpDef r_r_rIN = { 0, { "r", "r", "rIN" } };
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static const TCGTargetOpDef r_r_rIK = { 0, { "r", "r", "rIK" } };
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static const TCGTargetOpDef r_r_r_r = { 0, { "r", "r", "r", "r" } };
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static const TCGTargetOpDef r_r_l_l = { 0, { "r", "r", "l", "l" } };
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static const TCGTargetOpDef s_s_s_s = { 0, { "s", "s", "s", "s" } };
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static const TCGTargetOpDef br = { 0, { "r", "rIN" } };
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static const TCGTargetOpDef dep = { 0, { "r", "0", "rZ" } };
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static const TCGTargetOpDef movc = { 0, { "r", "r", "rIN", "rIK", "0" } };
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static const TCGTargetOpDef add2 = { 0, { "r", "r", "r", "r", "rIN", "rIK" } };
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static const TCGTargetOpDef sub2 = { 0, { "r", "r", "rI", "rI", "rIN", "rIK" } };
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static const TCGTargetOpDef br2 = { 0, { "r", "r", "rIN", "rIN" } };
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static const TCGTargetOpDef setc2 = { 0, { "r", "r", "r", "rIN", "rIN" } };
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for (i = 0; i < n; ++i) {
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if (arm_op_defs[i].op == op) {
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return &arm_op_defs[i];
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}
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switch (op) {
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case INDEX_op_goto_ptr:
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return &r;
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case INDEX_op_ld8u_i32:
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case INDEX_op_ld8s_i32:
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case INDEX_op_ld16u_i32:
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case INDEX_op_ld16s_i32:
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case INDEX_op_ld_i32:
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case INDEX_op_st8_i32:
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case INDEX_op_st16_i32:
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case INDEX_op_st_i32:
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case INDEX_op_neg_i32:
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case INDEX_op_not_i32:
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case INDEX_op_bswap16_i32:
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case INDEX_op_bswap32_i32:
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case INDEX_op_ext8s_i32:
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case INDEX_op_ext16s_i32:
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case INDEX_op_ext16u_i32:
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case INDEX_op_extract_i32:
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case INDEX_op_sextract_i32:
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return &r_r;
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case INDEX_op_add_i32:
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case INDEX_op_sub_i32:
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case INDEX_op_setcond_i32:
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return &r_r_rIN;
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case INDEX_op_and_i32:
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case INDEX_op_andc_i32:
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case INDEX_op_clz_i32:
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case INDEX_op_ctz_i32:
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return &r_r_rIK;
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case INDEX_op_mul_i32:
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case INDEX_op_div_i32:
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case INDEX_op_divu_i32:
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return &r_r_r;
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case INDEX_op_mulu2_i32:
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case INDEX_op_muls2_i32:
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return &r_r_r_r;
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case INDEX_op_or_i32:
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case INDEX_op_xor_i32:
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return &r_r_rI;
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case INDEX_op_shl_i32:
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case INDEX_op_shr_i32:
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case INDEX_op_sar_i32:
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case INDEX_op_rotl_i32:
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case INDEX_op_rotr_i32:
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return &r_r_ri;
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case INDEX_op_brcond_i32:
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return &br;
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case INDEX_op_deposit_i32:
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return &dep;
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case INDEX_op_movcond_i32:
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return &movc;
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case INDEX_op_add2_i32:
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return &add2;
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case INDEX_op_sub2_i32:
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return &sub2;
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case INDEX_op_brcond2_i32:
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return &br2;
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case INDEX_op_setcond2_i32:
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return &setc2;
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case INDEX_op_qemu_ld_i32:
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return TARGET_LONG_BITS == 32 ? &r_l : &r_l_l;
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case INDEX_op_qemu_ld_i64:
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return TARGET_LONG_BITS == 32 ? &r_r_l : &r_r_l_l;
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case INDEX_op_qemu_st_i32:
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return TARGET_LONG_BITS == 32 ? &s_s : &s_s_s;
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case INDEX_op_qemu_st_i64:
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return TARGET_LONG_BITS == 32 ? &s_s_s : &s_s_s_s;
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default:
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return NULL;
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}
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return NULL;
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}
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static void tcg_target_init(TCGContext *s)
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