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target/arm: Implement HACR_EL2

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HACR_EL2 is a register with IMPDEF behaviour, which allows
implementation specific trapping to EL2. Implement it as RAZ/WI,
since QEMU's implementation has no extra traps. This also
matches what h/w implementations like Cortex-A53 and A57 do.

Backports commit 831a2fca343ebcd6651eab9102bd7a36b77da65d from qemu
This commit is contained in:
Peter Maydell 2019-02-15 17:15:33 -05:00 committed by Lioncash
parent af17f7fa59
commit 31813bafe2
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 6 additions and 0 deletions
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6
qemu/target/arm/helper.c
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@ -3935,6 +3935,9 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
{ "HCR_EL2", 0,1,1, 3,4,0, ARM_CP_STATE_BOTH,
ARM_CP_CONST, PL2_RW, 0, NULL, 0, 0, {0, 0},
NULL, NULL, NULL },
{ "HACR_EL2", 0,1,1, 3,4,7, ARM_CP_STATE_BOTH,
ARM_CP_CONST, PL2_RW, 0, NULL, 0, 0, {0, 0},
NULL, NULL, NULL },
{ "ESR_EL2", 0,5,2, 3,1,0, ARM_CP_STATE_BOTH, ARM_CP_CONST,
PL2_RW, 0, NULL, 0 },
{ "CPTR_EL2", 0,1,1, 3,4,2, ARM_CP_STATE_BOTH, ARM_CP_CONST,
@ -4130,6 +4133,9 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
{0, 0}, NULL, NULL, hcr_writelow },
{ "ELR_EL2", 0,4,0, 3,4,1, ARM_CP_STATE_AA64,
ARM_CP_ALIAS, PL2_RW, 0, NULL, 0, offsetof(CPUARMState, elr_el[2]) },
{ "HACR_EL2", 0,1,1, 3,4,7, ARM_CP_STATE_BOTH,
ARM_CP_CONST, PL2_RW, 0, NULL, 0, 0, {0, 0},
NULL, NULL, NULL },
{ "ESR_EL2", 0,5,2, 3,4,0, ARM_CP_STATE_BOTH, 0,
PL2_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.esr_el[2]) },
{ "FAR_EL2", 0,6,0, 3,4,0, ARM_CP_STATE_BOTH,