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target/mips: Add preprocessor constants for nanoMIPS

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Add ISA_NANOMIPS32 and CPU_NANOMIPS32 preprocessor constants.

Backports commit fa7c0c9f5bc12970858a89f46dd5012c01545b80 from qemu
This commit is contained in:
Aleksandar Markovic 2018-08-27 04:11:09 -04:00 committed by Lioncash
parent 39045d67df
commit 31f42b9f2c
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 4 additions and 0 deletions
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4
qemu/target/mips/mips-defs.h
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@ -35,6 +35,7 @@
#define ISA_MIPS64R5 0x00001000
#define ISA_MIPS32R6 0x00002000
#define ISA_MIPS64R6 0x00004000
#define ISA_NANOMIPS32 0x00008000
/* MIPS ASEs. */
#define ASE_MIPS16 0x00010000
@ -83,6 +84,9 @@
#define CPU_MIPS32R6 (CPU_MIPS32R5 | ISA_MIPS32R6)
#define CPU_MIPS64R6 (CPU_MIPS64R5 | CPU_MIPS32R6 | ISA_MIPS64R6)
/* Wave Computing: "nanoMIPS" */
#define CPU_NANOMIPS32 (CPU_MIPS32R6 | ISA_NANOMIPS32)
/* Strictly follow the architecture standard:
- Disallow "special" instruction handling for PMON/SPIM.
Note that we still maintain Count/Compare to match the host clock. */