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target-mips: Add M14K and M14Kc MIPS32r2 microMIPS processors

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Add the M14K and M14Kc processors from MIPS Technologies that are the
original implementation of the microMIPS ISA. They are dual instruction
set processors, implementing both the microMIPS and the standard MIPSr32
ISA.

These processors correspond to the M4K and 4KEc CPUs respectively,
except with support for the microMIPS instruction set added, support for
the MCU ASE added and two extra interrupt lines, making a total of 8
hardware interrupts plus 2 software interrupts. The remaining parts of
the microarchitecture, in particular the pipeline, stayed unchanged.

The presence of the microMIPS ASE is is reflected in the configuration
added. We currently have no support for the MCU ASE, including in
particular the ACLR, ASET and IRET instructions in either encoding, and
we have no support for the extra interrupt lines, including bits in
CP0.Status and CP0.Cause registers, so these features are not marked,
making our support diverge from real hardware.

Backports commit 11f5ea105c06bec72e9bc9a700fa65d60afb5ec3 from qemu
This commit is contained in:
Maciej W. Rozycki 2018-02-11 15:55:54 -05:00 committed by Lioncash
parent 833b0ff964
commit 338e34290d
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 59 additions and 0 deletions
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59
qemu/target-mips/translate_init.c
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@ -429,6 +429,65 @@ static const mips_def_t mips_defs[] =
CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2, CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
MMU_TYPE_R4000, MMU_TYPE_R4000,
}, },
{
"M14K",
0x00019b00,
/* Config1 implemented, fixed mapping MMU,
no virtual icache, uncached coherency. */
MIPS_CONFIG0 | (0x2 << CP0C0_KU) | (0x2 << CP0C0_K23) |
(0x1 << CP0C0_AR) | (MMU_TYPE_FMT << CP0C0_MT),
MIPS_CONFIG1,
MIPS_CONFIG2,
MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (1 << CP0C3_VInt),
0, 0,
0, 0,
0,
0,
0,
4,
32,
2,
0x1258FF17,
0,
0,
0,
0,
32,
32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS32R2 | ASE_MICROMIPS,
MMU_TYPE_FMT,
},
{
"M14Kc",
/* This is the TLB-based MMU core. */
0x00019c00,
MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
(MMU_TYPE_R4000 << CP0C0_MT),
MIPS_CONFIG1 | (15 << CP0C1_MMU) |
(0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
(0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA),
MIPS_CONFIG2,
MIPS_CONFIG3 | (0x2 << CP0C3_ISA) | (0 << CP0C3_VInt),
0, 0,
0, 0,
0,
0,
0,
4,
32,
2,
0x1278FF17,
0,
0,
0,
0,
32,
32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
CPU_MIPS32R2 | ASE_MICROMIPS,
MMU_TYPE_R4000,
},
{ {
/* A generic CPU providing MIPS32 Release 5 features. /* A generic CPU providing MIPS32 Release 5 features.
FIXME: Eventually this should be replaced by a real CPU model. */ FIXME: Eventually this should be replaced by a real CPU model. */