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target-arm: emulate SWP with atomic_xchg helper

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Backports commit cf12bce088f22b92bf62ffa0d7f6a3e951e355a9 from qemu
This commit is contained in:
Emilio G. Cota 2018-02-28 00:11:20 -05:00 committed by Lioncash
parent ec14a00925
commit 3546558f66
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 14 additions and 12 deletions
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26
qemu/target-arm/translate.c
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@ -8946,25 +8946,27 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) // qq
}
tcg_temp_free_i32(tcg_ctx, addr);
} else {
TCGv taddr;
TCGMemOp opc = s->be_data;
/* SWP instruction */
rm = (insn) & 0xf;
/* ??? This is not really atomic. However we know
we never have multiple CPUs running in parallel,
so it is good enough. */
addr = load_reg(s, rn);
tmp = load_reg(s, rm);
tmp2 = tcg_temp_new_i32(tcg_ctx);
if (insn & (1 << 22)) {
gen_aa32_ld8u(s, tmp2, addr, get_mem_index(s));
gen_aa32_st8(s, tmp, addr, get_mem_index(s));
opc |= MO_UB;
} else {
gen_aa32_ld32u(s, tmp2, addr, get_mem_index(s));
gen_aa32_st32(s, tmp, addr, get_mem_index(s));
opc |= MO_UL | MO_ALIGN;
}
tcg_temp_free_i32(tcg_ctx, tmp);
addr = load_reg(s, rn);
taddr = gen_aa32_addr(s, addr, opc);
tcg_temp_free_i32(tcg_ctx, addr);
store_reg(s, rd, tmp2);
tmp = load_reg(s, rm);
tcg_gen_atomic_xchg_i32(tcg_ctx, tmp, taddr, tmp,
get_mem_index(s), opc);
tcg_temp_free(tcg_ctx, taddr);
store_reg(s, rd, tmp);
}
}
} else {