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target/arm: Update arm_cpu_do_interrupt_aarch64 for VHE

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When VHE is enabled, the exception level below EL2 is not EL1,
but EL0, and so to identify the entry vector offset for exceptions
targeting EL2 we need to look at the width of EL0, not of EL1.

Backports commit cb092fbbaeb7b4e91b3f9c53150c8160f91577c7 from qemu
This commit is contained in:
Richard Henderson 2020-03-21 16:35:04 -04:00 committed by Lioncash
parent 8f1201e392
commit 36407da586
1 changed files with 7 additions and 2 deletions
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9
qemu/target/arm/helper.c
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@ -8793,14 +8793,19 @@ static void arm_cpu_do_interrupt_aarch64_(CPUState *cs)
* immediately lower than the target level is using AArch32 or AArch64
*/
bool is_aa64 = false;
uint64_t hcr;
switch (new_el) {
case 3:
is_aa64 = (env->cp15.scr_el3 & SCR_RW) != 0;
break;
case 2:
is_aa64 = (env->cp15.hcr_el2 & HCR_RW) != 0;
break;
hcr = arm_hcr_el2_eff(env);
if ((hcr & (HCR_E2H | HCR_TGE)) != (HCR_E2H | HCR_TGE)) {
is_aa64 = (hcr & HCR_RW) != 0;
break;
}
/* fall through */
case 1:
is_aa64 = is_a64(env);
break;