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target/mips: Implement emulation of nanoMIPS LLWP/SCWP pair
Implement support for nanoMIPS LLWP/SCWP instructions. Beside adding core functionality of these instructions, this patch adds support for availability control via configuration bit XNP. Backports commit 0b16dcd180bdbe3add9edea42c2374d427882661 from qemu
This commit is contained in:
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128bfa00d2
commit
371bb5a134
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@ -507,6 +507,8 @@ struct CPUMIPSState {
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uint64_t lladdr;
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target_ulong llval;
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target_ulong llnewval;
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uint64_t llval_wp;
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uint32_t llnewval_wp;
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target_ulong llreg;
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uint64_t CP0_LLAddr_rw_bitmask;
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int CP0_LLAddr_shift;
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@ -1922,6 +1922,18 @@ static inline void check_mvh(DisasContext *ctx)
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}
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#endif
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/*
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* This code generates a "reserved instruction" exception if the
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* Config5 XNP bit is set.
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*/
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static inline void check_xnp(DisasContext *ctx)
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{
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if (unlikely(ctx->CP0_Config5 & (1 << CP0C5_XNP))) {
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generate_exception_end(ctx, EXCP_RI);
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}
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}
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/* Define small wrappers for gen_load_fpr* so that we have a uniform
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calling interface for 32 and 64-bit FPRs. No sense in changing
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all callers for gen_load_fpr32 when we need the CTX parameter for
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@ -2377,6 +2389,32 @@ static void gen_ld(DisasContext *ctx, uint32_t opc,
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tcg_temp_free(tcg_ctx, t0);
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}
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static void gen_llwp(DisasContext *ctx, uint32_t base, int16_t offset,
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uint32_t reg1, uint32_t reg2)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv taddr = tcg_temp_new(tcg_ctx);
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TCGv_i64 tval = tcg_temp_new_i64(tcg_ctx);
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TCGv tmp1 = tcg_temp_new(tcg_ctx);
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TCGv tmp2 = tcg_temp_new(tcg_ctx);
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gen_base_offset_addr(ctx, taddr, base, offset);
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tcg_gen_qemu_ld64(ctx->uc, tval, taddr, ctx->mem_idx);
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#ifdef TARGET_WORDS_BIGENDIAN
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tcg_gen_extr_i64_tl(tcg_ctx, tmp2, tmp1, tval);
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#else
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tcg_gen_extr_i64_tl(tcg_ctx, tmp1, tmp2, tval);
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#endif
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gen_store_gpr(tcg_ctx, tmp1, reg1);
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tcg_temp_free(tcg_ctx, tmp1);
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gen_store_gpr(tcg_ctx, tmp2, reg2);
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tcg_temp_free(tcg_ctx, tmp2);
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tcg_gen_st_i64(tcg_ctx, tval, tcg_ctx->cpu_env, offsetof(CPUMIPSState, llval_wp));
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tcg_temp_free_i64(tcg_ctx, tval);
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tcg_gen_st_tl(tcg_ctx, taddr, tcg_ctx->cpu_env, offsetof(CPUMIPSState, lladdr));
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tcg_temp_free(tcg_ctx, taddr);
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}
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/* Store */
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static void gen_st (DisasContext *ctx, uint32_t opc, int rt,
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int base, int offset)
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@ -2475,6 +2513,52 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
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tcg_temp_free(tcg_ctx, t0);
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}
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static void gen_scwp(DisasContext *ctx, uint32_t base, int16_t offset,
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uint32_t reg1, uint32_t reg2)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv taddr = tcg_temp_local_new(tcg_ctx);
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TCGv lladdr = tcg_temp_local_new(tcg_ctx);
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TCGv_i64 tval = tcg_temp_new_i64(tcg_ctx);
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TCGv_i64 llval = tcg_temp_new_i64(tcg_ctx);
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TCGv_i64 val = tcg_temp_new_i64(tcg_ctx);
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TCGv tmp1 = tcg_temp_new(tcg_ctx);
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TCGv tmp2 = tcg_temp_new(tcg_ctx);
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TCGLabel *lab_fail = gen_new_label(tcg_ctx);
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TCGLabel *lab_done = gen_new_label(tcg_ctx);
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gen_base_offset_addr(ctx, taddr, base, offset);
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tcg_gen_ld_tl(tcg_ctx, lladdr, tcg_ctx->cpu_env, offsetof(CPUMIPSState, lladdr));
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tcg_gen_brcond_tl(tcg_ctx, TCG_COND_NE, taddr, lladdr, lab_fail);
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gen_load_gpr(ctx, tmp1, reg1);
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gen_load_gpr(ctx, tmp2, reg2);
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#ifdef TARGET_WORDS_BIGENDIAN
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tcg_gen_concat_tl_i64(tcg_ctx, tval, tmp2, tmp1);
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#else
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tcg_gen_concat_tl_i64(tcg_ctx, tval, tmp1, tmp2);
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#endif
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tcg_gen_ld_i64(tcg_ctx, llval, tcg_ctx->cpu_env, offsetof(CPUMIPSState, llval_wp));
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tcg_gen_atomic_cmpxchg_i64(tcg_ctx, val, taddr, llval, tval,
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ctx->mem_idx, MO_64);
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if (reg1 != 0) {
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tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr[reg1], 1);
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}
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tcg_gen_brcond_i64(tcg_ctx, TCG_COND_EQ, val, llval, lab_done);
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gen_set_label(tcg_ctx, lab_fail);
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if (reg1 != 0) {
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tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr[reg1], 0);
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}
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gen_set_label(tcg_ctx, lab_done);
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tcg_gen_movi_tl(tcg_ctx, lladdr, -1);
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tcg_gen_st_tl(tcg_ctx, lladdr, tcg_ctx->cpu_env, offsetof(CPUMIPSState, lladdr));
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}
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/* Load and store */
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static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
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TCGv t0)
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@ -18240,6 +18324,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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gen_ld(ctx, OPC_LL, rt, rs, s);
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break;
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case NM_LLWP:
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check_xnp(ctx);
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gen_llwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
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break;
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}
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break;
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@ -18249,6 +18335,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
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gen_st_cond(ctx, OPC_SC, rt, rs, s);
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break;
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case NM_SCWP:
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check_xnp(ctx);
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gen_scwp(ctx, rs, 0, rt, extract32(ctx->opcode, 3, 5));
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break;
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}
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break;
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