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target/arm: Introduce arm_stage1_mmu_idx

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While we could expose stage_1_mmu_idx, the combination is
probably going to be more useful.

Backports commit 64be86ab1b5ef10b660a4230ee7f27c0da499043 from qemu
This commit is contained in:
Richard Henderson 2019-01-22 16:08:35 -05:00 committed by Lioncash
parent 9743787d0f
commit 377bd123bd
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GPG key ID: 4E3C3CC1031BA9C7
7 changed files with 28 additions and 0 deletions
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1
qemu/aarch64.h
View file

@ -3291,6 +3291,7 @@
#define arm_reset_cpu arm_reset_cpu_aarch64
#define arm_set_cpu_off arm_set_cpu_off_aarch64
#define arm_set_cpu_on arm_set_cpu_on_aarch64
#define arm_stage1_mmu_idx arm_stage1_mmu_idx_aarch64
#define bif_op bif_op_aarch64
#define bit_op bit_op_aarch64
#define bsl_op bsl_op_aarch64

1
qemu/aarch64eb.h
View file

@ -3291,6 +3291,7 @@
#define arm_reset_cpu arm_reset_cpu_aarch64eb
#define arm_set_cpu_off arm_set_cpu_off_aarch64eb
#define arm_set_cpu_on arm_set_cpu_on_aarch64eb
#define arm_stage1_mmu_idx arm_stage1_mmu_idx_aarch64eb
#define bif_op bif_op_aarch64eb
#define bit_op bit_op_aarch64eb
#define bsl_op bsl_op_aarch64eb

1
qemu/arm.h
View file

@ -3283,6 +3283,7 @@
#define arm_reset_cpu arm_reset_cpu_arm
#define arm_set_cpu_off arm_set_cpu_off_arm
#define arm_set_cpu_on arm_set_cpu_on_arm
#define arm_stage1_mmu_idx arm_stage1_mmu_idx_arm
#define cmtst_op cmtst_op_arm
#define fp_exception_el fp_exception_el_arm
#define gen_cmtst_i64 gen_cmtst_i64_arm

1
qemu/armeb.h
View file

@ -3283,6 +3283,7 @@
#define arm_reset_cpu arm_reset_cpu_armeb
#define arm_set_cpu_off arm_set_cpu_off_armeb
#define arm_set_cpu_on arm_set_cpu_on_armeb
#define arm_stage1_mmu_idx arm_stage1_mmu_idx_armeb
#define cmtst_op cmtst_op_armeb
#define fp_exception_el fp_exception_el_armeb
#define gen_cmtst_i64 gen_cmtst_i64_armeb

2
qemu/header_gen.py
View file

@ -3292,6 +3292,7 @@ arm_symbols = (
'arm_reset_cpu',
'arm_set_cpu_off',
'arm_set_cpu_on',
'arm_stage1_mmu_idx',
'cmtst_op',
'fp_exception_el',
'gen_cmtst_i64',
@ -3329,6 +3330,7 @@ aarch64_symbols = (
'arm_reset_cpu',
'arm_set_cpu_off',
'arm_set_cpu_on',
'arm_stage1_mmu_idx',
'bif_op',
'bit_op',
'bsl_op',

7
qemu/target/arm/helper.c
View file

@ -12205,6 +12205,13 @@ int cpu_mmu_index(CPUARMState *env, bool ifetch)
return arm_to_core_mmu_idx(arm_mmu_idx(env));
}
#ifndef CONFIG_USER_ONLY
ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
{
return stage_1_mmu_idx(arm_mmu_idx(env));
}
#endif
void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *pflags)
{

15
qemu/target/arm/internals.h
View file

@ -929,4 +929,19 @@ void arm_cpu_update_vfiq(ARMCPU *cpu);
*/
ARMMMUIdx arm_mmu_idx(CPUARMState *env);
/**
* arm_stage1_mmu_idx:
* @env: The cpu environment
*
* Return the ARMMMUIdx for the stage1 traversal for the current regime.
*/
#ifdef CONFIG_USER_ONLY
static inline ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env)
{
return ARMMMUIdx_S1NSE0;
}
#else
ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env);
#endif
#endif