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target-arm: Add support for AArch64 PMU register PMXEVTYPER_EL0
In order to support Linux perf, which uses PMXEVTYPER register, this patch adds read/write access support for PMXEVTYPER. The access is CONSTRAINED UNPREDICTABLE when PMSELR is not 0x1f. Additionally this patch adds support for PMXEVTYPER_EL0. Backports commit fdb8665672ded05f650d18f8b62d5c8524b4385b from qemu
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@ -311,7 +311,6 @@ typedef struct CPUARMState {
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uint64_t c9_pmcr; /* performance monitor control register */
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uint64_t c9_pmcnten; /* perf monitor counter enables */
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uint32_t c9_pmovsr; /* perf monitor overflow status */
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uint32_t c9_pmxevtyper; /* perf monitor event type */
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uint32_t c9_pmuserenr; /* perf monitor user enable */
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uint64_t c9_pmselr; /* perf monitor counter selection register */
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uint32_t c9_pminten; /* perf monitor interrupt enables */
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@ -942,7 +942,25 @@ static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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env->cp15.c9_pmxevtyper = value & 0xff;
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/* Attempts to access PMXEVTYPER are CONSTRAINED UNPREDICTABLE when
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* PMSELR value is equal to or greater than the number of implemented
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* counters, but not equal to 0x1f. We opt to behave as a RAZ/WI.
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*/
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if (env->cp15.c9_pmselr == 0x1f) {
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pmccfiltr_write(env, ri, value);
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}
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}
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static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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/* We opt to behave as a RAZ/WI when attempts to access PMXEVTYPER
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* are CONSTRAINED UNPREDICTABLE. See comments in pmxevtyper_write().
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*/
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if (env->cp15.c9_pmselr == 0x1f) {
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return env->cp15.pmccfiltr_el0;
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} else {
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return 0;
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}
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}
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static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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@ -1094,9 +1112,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
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{ "PMCCFILTR_EL0", 0,14,15, 3,3,7, ARM_CP_STATE_AA64,
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ARM_CP_IO, PL0_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.pmccfiltr_el0), {0, 0},
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pmreg_access, NULL, pmccfiltr_write, },
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{ "PMXEVTYPER", 15,9,13, 0,0,1, 0,
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0, PL0_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c9_pmxevtyper), {0, 0},
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pmreg_access, NULL, pmxevtyper_write, NULL, raw_write },
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{ "PMXEVTYPER", 15,9,13, 0,0,1, 0, ARM_CP_NO_RAW,
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PL0_RW, 0, NULL, 0, 0, {0, 0},
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pmreg_access, pmxevtyper_read, pmxevtyper_write },
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{ "PMXEVTYPER_EL0", 0,9,13, 3,3,1, ARM_CP_STATE_AA64, ARM_CP_NO_RAW,
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PL0_RW, 0, NULL, 0, 0, {0, 0},
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pmreg_access, pmxevtyper_read, pmxevtyper_write },
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/* Unimplemented, RAZ/WI. */
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{ "PMXEVCNTR", 15,9,13, 0,0,2, 0,
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ARM_CP_CONST, PL0_RW, 0, NULL, 0, 0, {0, 0},
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