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target/riscv: Remove gen_jalr()

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trans_jalr() is the only caller, so move the code into trans_jalr().

Backports commit 9e92c57d834cd50ab088d75510c3c720878eef13 from qemu
This commit is contained in:
Bastian Koppelmann 2019-03-19 04:55:50 -04:00 committed by Lioncash
parent 580457a1d2
commit 3fe4cf353c
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 29 additions and 41 deletions
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30
qemu/target/riscv/insn_trans/trans_rvi.inc.c
View file

@ -44,7 +44,35 @@ static bool trans_jal(DisasContext *ctx, arg_jal *a)
static bool trans_jalr(DisasContext *ctx, arg_jalr *a) static bool trans_jalr(DisasContext *ctx, arg_jalr *a)
{ {
gen_jalr(ctx, OPC_RISC_JALR, a->rd, a->rs1, a->imm); TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
/* no chaining with JALR */
TCGLabel *misaligned = NULL;
TCGv t0 = tcg_temp_new(tcg_ctx);
gen_get_gpr(ctx, tcg_ctx->cpu_pc_risc, a->rs1);
tcg_gen_addi_tl(tcg_ctx, tcg_ctx->cpu_pc_risc, tcg_ctx->cpu_pc_risc, a->imm);
tcg_gen_andi_tl(tcg_ctx, tcg_ctx->cpu_pc_risc, tcg_ctx->cpu_pc_risc, (target_ulong)-2);
if (!has_ext(ctx, RVC)) {
misaligned = gen_new_label(tcg_ctx);
tcg_gen_andi_tl(tcg_ctx, t0, tcg_ctx->cpu_pc_risc, 0x2);
tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_NE, t0, 0x0, misaligned);
}
if (a->rd != 0) {
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr_risc[a->rd], ctx->pc_succ_insn);
}
tcg_gen_lookup_and_goto_ptr(tcg_ctx);
if (misaligned) {
gen_set_label(tcg_ctx, misaligned);
gen_exception_inst_addr_mis(ctx);
}
ctx->base.is_jmp = DISAS_NORETURN;
tcg_temp_free(tcg_ctx, t0);
return true; return true;
} }

40
qemu/target/riscv/translate.c
View file

@ -547,46 +547,6 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;
} }
static void gen_jalr(DisasContext *ctx, uint32_t opc, int rd, int rs1,
target_long imm)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
/* no chaining with JALR */
TCGLabel *misaligned = NULL;
TCGv t0 = tcg_temp_new(tcg_ctx);
switch (opc) {
case OPC_RISC_JALR:
gen_get_gpr(ctx, tcg_ctx->cpu_pc_risc, rs1);
tcg_gen_addi_tl(tcg_ctx, tcg_ctx->cpu_pc_risc, tcg_ctx->cpu_pc_risc, imm);
tcg_gen_andi_tl(tcg_ctx, tcg_ctx->cpu_pc_risc, tcg_ctx->cpu_pc_risc, (target_ulong)-2);
if (!has_ext(ctx, RVC)) {
misaligned = gen_new_label(tcg_ctx);
tcg_gen_andi_tl(tcg_ctx, t0, tcg_ctx->cpu_pc_risc, 0x2);
tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_NE, t0, 0x0, misaligned);
}
if (rd != 0) {
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr_risc[rd], ctx->pc_succ_insn);
}
tcg_gen_lookup_and_goto_ptr(tcg_ctx);
if (misaligned) {
gen_set_label(tcg_ctx, misaligned);
gen_exception_inst_addr_mis(ctx);
}
ctx->base.is_jmp = DISAS_NORETURN;
break;
default:
gen_exception_illegal(ctx);
break;
}
tcg_temp_free(tcg_ctx, t0);
}
static void gen_branch(DisasContext *ctx, uint32_t opc, int rs1, int rs2, static void gen_branch(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
target_long bimm) target_long bimm)
{ {