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target/arm: New helper function arm_v7m_mmu_idx_all()

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Add a new helper function which returns the MMU index to use
for v7M, where the caller specifies all of the security
state, privilege level and whether the execution priority
is negative, and reimplement the existing
arm_v7m_mmu_idx_for_secstate_and_priv() in terms of it.

We are going to need this for the lazy-FP-stacking code.

Backports commit fa6252a988dbe440cd6087bf93cbe0887f0c401b from qemu
This commit is contained in:
Peter Maydell 2019-04-30 10:54:24 -04:00 committed by Lioncash
parent 719231b4c0
commit 3fff653e20
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
7 changed files with 24 additions and 6 deletions
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1
qemu/aarch64.h
View file

@ -3340,6 +3340,7 @@
#define arm64_reg_reset arm64_reg_reset_aarch64
#define arm64_reg_write arm64_reg_write_aarch64
#define arm64_release arm64_release_aarch64
#define arm_v7m_mmu_idx_all arm_v7m_mmu_idx_all_aarch64
#define arm_v7m_mmu_idx_for_secstate arm_v7m_mmu_idx_for_secstate_aarch64
#define arm_v7m_mmu_idx_for_secstate_and_priv arm_v7m_mmu_idx_for_secstate_and_priv_aarch64
#define arm_hcr_el2_eff arm_hcr_el2_eff_aarch64

1
qemu/aarch64eb.h
View file

@ -3340,6 +3340,7 @@
#define arm64_reg_reset arm64_reg_reset_aarch64eb
#define arm64_reg_write arm64_reg_write_aarch64eb
#define arm64_release arm64_release_aarch64eb
#define arm_v7m_mmu_idx_all arm_v7m_mmu_idx_all_aarch64eb
#define arm_v7m_mmu_idx_for_secstate arm_v7m_mmu_idx_for_secstate_aarch64eb
#define arm_v7m_mmu_idx_for_secstate_and_priv arm_v7m_mmu_idx_for_secstate_and_priv_aarch64eb
#define arm_hcr_el2_eff arm_hcr_el2_eff_aarch64eb

1
qemu/arm.h
View file

@ -3331,6 +3331,7 @@
#define aa64_va_parameters aa64_va_parameters_arm
#define aa64_va_parameters_both aa64_va_parameters_both_arm
#define aarch64_translator_ops aarch64_translator_ops_arm
#define arm_v7m_mmu_idx_all arm_v7m_mmu_idx_all_arm
#define arm_v7m_mmu_idx_for_secstate arm_v7m_mmu_idx_for_secstate_arm
#define arm_v7m_mmu_idx_for_secstate_and_priv arm_v7m_mmu_idx_for_secstate_and_priv_arm
#define ARM_REGS_STORAGE_SIZE ARM_REGS_STORAGE_SIZE_arm

1
qemu/armeb.h
View file

@ -3331,6 +3331,7 @@
#define aa64_va_parameters aa64_va_parameters_armeb
#define aa64_va_parameters_both aa64_va_parameters_both_armeb
#define aarch64_translator_ops aarch64_translator_ops_armeb
#define arm_v7m_mmu_idx_all arm_v7m_mmu_idx_all_armeb
#define arm_v7m_mmu_idx_for_secstate arm_v7m_mmu_idx_for_secstate_armeb
#define arm_v7m_mmu_idx_for_secstate_and_priv arm_v7m_mmu_idx_for_secstate_and_priv_armeb
#define ARM_REGS_STORAGE_SIZE ARM_REGS_STORAGE_SIZE_armeb

2
qemu/header_gen.py
View file

@ -3340,6 +3340,7 @@ arm_symbols = (
'aa64_va_parameters',
'aa64_va_parameters_both',
'aarch64_translator_ops',
'arm_v7m_mmu_idx_all',
'arm_v7m_mmu_idx_for_secstate',
'arm_v7m_mmu_idx_for_secstate_and_priv',
'ARM_REGS_STORAGE_SIZE',
@ -3394,6 +3395,7 @@ aarch64_symbols = (
'arm64_reg_reset',
'arm64_reg_write',
'arm64_release',
'arm_v7m_mmu_idx_all',
'arm_v7m_mmu_idx_for_secstate',
'arm_v7m_mmu_idx_for_secstate_and_priv',
'arm_hcr_el2_eff',

7
qemu/target/arm/cpu.h
View file

@ -2868,6 +2868,13 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx)
}
}
/*
* Return the MMU index for a v7M CPU with all relevant information
* manually specified.
*/
ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
bool secstate, bool priv, bool negpri);
/* Return the MMU index for a v7M CPU in the specified security and
* privilege state.
*/

17
qemu/target/arm/helper.c
View file

@ -13023,8 +13023,8 @@ int fp_exception_el(CPUARMState *env, int cur_el)
return 0;
}
ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
bool secstate, bool priv)
ARMMMUIdx arm_v7m_mmu_idx_all(CPUARMState *env,
bool secstate, bool priv, bool negpri)
{
ARMMMUIdx mmu_idx = ARM_MMU_IDX_M;
@ -13032,12 +13032,9 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
mmu_idx |= ARM_MMU_IDX_M_PRIV;
}
// Unicorn: disabled
#if 0
if (armv7m_nvic_neg_prio_requested(env->nvic, secstate)) {
if (negpri) {
mmu_idx |= ARM_MMU_IDX_M_NEGPRI;
}
#endif
if (secstate) {
mmu_idx |= ARM_MMU_IDX_M_S;
@ -13046,6 +13043,14 @@ ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
return mmu_idx;
}
ARMMMUIdx arm_v7m_mmu_idx_for_secstate_and_priv(CPUARMState *env,
bool secstate, bool priv)
{
bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate);
return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);
}
/* Return the MMU index for a v7M CPU in the specified security state */
ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)
{