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aarch64: Add FPCR and FPSR registers
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@ -293,6 +293,10 @@ typedef enum uc_arm64_reg {
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UC_ARM64_REG_PSTATE, // PSTATE pseudoregister
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//> floating point control and status registers
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UC_ARM64_REG_FPCR,
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UC_ARM64_REG_FPSR,
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UC_ARM64_REG_ENDING, // <-- mark the end of the list of registers
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//> alias registers
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@ -109,6 +109,12 @@ int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int co
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case UC_ARM64_REG_PSTATE:
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*(uint32_t *)value = pstate_read(&ARM_CPU(uc, mycpu)->env);
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break;
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case UC_ARM64_REG_FPCR:
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*(uint32_t *)value = vfp_get_fpcr(&ARM_CPU(uc, mycpu)->env);
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break;
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case UC_ARM64_REG_FPSR:
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*(uint32_t *)value = vfp_get_fpsr(&ARM_CPU(uc, mycpu)->env);
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break;
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}
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}
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}
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@ -180,6 +186,12 @@ int arm64_reg_write(struct uc_struct *uc, unsigned int *regs, void* const* vals,
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case UC_ARM64_REG_PSTATE:
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pstate_write(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value);
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break;
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case UC_ARM64_REG_FPCR:
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vfp_set_fpcr(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value);
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break;
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case UC_ARM64_REG_FPSR:
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vfp_set_fpsr(&ARM_CPU(uc, mycpu)->env, *(uint32_t *)value);
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break;
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}
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}
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}
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