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target-mips: Set Config5.XNP for R6 cores

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Set Config5.XNP for R6 cores to indicate the extended LL/SC family
of instructions NOT present.

Backports commit 35ac9e342e008e3d47ef18d33a6977fdb99de9cd from qemu
This commit is contained in:
Yongbok Kim 2018-02-17 14:41:27 -05:00 committed by Lioncash
parent 4a9cd8ec0b
commit 4544aa4134
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 2 additions and 2 deletions
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4
qemu/target-mips/translate_init.c
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@ -553,7 +553,7 @@ static const mips_def_t mips_defs[] =
MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
(3 << CP0C4_IE) | (1U << CP0C4_M),
0,
MIPS_CONFIG5 | (1 << CP0C5_LLB),
MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB),
(1 << CP0C5_SBRI) | (1 << CP0C5_FRE) | (1 << CP0C5_UFE),
0,
0,
@ -788,7 +788,7 @@ static const mips_def_t mips_defs[] =
(1 << CP0C3_RXI) | (1 << CP0C3_LPA),
MIPS_CONFIG4 | (1U << CP0C4_M) | (3 << CP0C4_IE) |
(0xfc << CP0C4_KScrExist),
MIPS_CONFIG5 | (1 << CP0C5_LLB),
MIPS_CONFIG5 | (1 << CP0C5_XNP) | (1 << CP0C5_LLB),
(1 << CP0C5_MSAEn) | (1 << CP0C5_SBRI) |
(1 << CP0C5_FRE) | (1 << CP0C5_UFE),
0,