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cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmap

Browse source 
While the vargs approach was flexible the original MTTCG ended up
having munge the bits to a bitmap so the data could be used in
deferred work helpers. Instead of hiding that in cputlb we push the
change to the API to make it take a bitmap of MMU indexes instead.

For ARM some the resulting flushes end up being quite long so to aid
readability I've tended to move the index shifting to a new line so
all the bits being or-ed together line up nicely, for example:

tlb_flush_page_by_mmuidx(other_cs, pageaddr,
(1 << ARMMMUIdx_S1SE1) |
(1 << ARMMMUIdx_S1SE0));

Backports commit 0336cbf8532935d8e23c2aabf3e2ce2c0697b6ac from qemu
This commit is contained in:
Alex Bennée 2018-03-02 10:10:49 -05:00 committed by Lioncash
parent d56a4b0be4
commit 454932263c
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
4 changed files with 130 additions and 112 deletions
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65
qemu/cputlb.c
View file

@ -66,9 +66,6 @@ static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,
target_ulong size); target_ulong size);
static void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr); static void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr);
/* statistics */
//int tlb_flush_count;
/* This is OK because CPU architectures generally permit an /* This is OK because CPU architectures generally permit an
* implementation to drop entries from the TLB at any time, so * implementation to drop entries from the TLB at any time, so
* flushing more entries than required is only an efficiency issue, * flushing more entries than required is only an efficiency issue,
@ -85,7 +82,6 @@ void tlb_flush(CPUState *cpu)
env->vtlb_index = 0; env->vtlb_index = 0;
env->tlb_flush_addr = -1; env->tlb_flush_addr = -1;
env->tlb_flush_mask = 0; env->tlb_flush_mask = 0;
//tlb_flush_count++;
} }
void tlb_flush_page(CPUState *cpu, target_ulong addr) void tlb_flush_page(CPUState *cpu, target_ulong addr)
@ -375,34 +371,29 @@ static bool tlb_is_dirty_ram(CPUTLBEntry *tlbe)
return (tlbe->addr_write & (TLB_INVALID_MASK|TLB_MMIO|TLB_NOTDIRTY)) == 0; return (tlbe->addr_write & (TLB_INVALID_MASK|TLB_MMIO|TLB_NOTDIRTY)) == 0;
} }
static inline void v_tlb_flush_by_mmuidx(CPUState *cpu, va_list argp) static inline void v_tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
{ {
CPUArchState *env = cpu->env_ptr; CPUArchState *env = cpu->env_ptr;
unsigned long mmu_idx_bitmask = idxmap;
int mmu_idx;
tlb_debug("start\n"); tlb_debug("start\n");
for (;;) { for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
int mmu_idx = va_arg(argp, int); if (test_bit(mmu_idx, &mmu_idx_bitmask)) {
tlb_debug("%d\n", mmu_idx);
if (mmu_idx < 0) { memset(env->tlb_table[mmu_idx], -1, sizeof(env->tlb_table[0]));
break; memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[0]));
} }
tlb_debug("%d\n", mmu_idx);
memset(env->tlb_table[mmu_idx], -1, sizeof(env->tlb_table[0]));
memset(env->tlb_v_table[mmu_idx], -1, sizeof(env->tlb_v_table[0]));
} }
memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache)); memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache));
} }
void tlb_flush_by_mmuidx(CPUState *cpu, ...) void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
{ {
va_list argp; v_tlb_flush_by_mmuidx(cpu, idxmap);
va_start(argp, cpu);
v_tlb_flush_by_mmuidx(cpu, argp);
va_end(argp);
} }
static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr) static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
@ -417,13 +408,11 @@ static inline void tlb_flush_entry(CPUTLBEntry *tlb_entry, target_ulong addr)
} }
} }
void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...) void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, uint16_t idxmap)
{ {
CPUArchState *env = cpu->env_ptr; CPUArchState *env = cpu->env_ptr;
int i, k; unsigned long mmu_idx_bitmap = idxmap;
va_list argp; int i, page, mmu_idx;
va_start(argp, addr);
tlb_debug("addr "TARGET_FMT_lx"\n", addr); tlb_debug("addr "TARGET_FMT_lx"\n", addr);
@ -433,31 +422,21 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...)
TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
env->tlb_flush_addr, env->tlb_flush_mask); env->tlb_flush_addr, env->tlb_flush_mask);
v_tlb_flush_by_mmuidx(cpu, argp); v_tlb_flush_by_mmuidx(cpu, idxmap);
va_end(argp);
return; return;
} }
addr &= TARGET_PAGE_MASK; addr &= TARGET_PAGE_MASK;
i = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); page = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
for (;;) { if (test_bit(mmu_idx, &mmu_idx_bitmap)) {
int mmu_idx = va_arg(argp, int); tlb_flush_entry(&env->tlb_table[mmu_idx][page], addr);
/* check whether there are vltb entries that need to be flushed */
if (mmu_idx < 0) { for (i = 0; i < CPU_VTLB_SIZE; i++) {
break; tlb_flush_entry(&env->tlb_v_table[mmu_idx][i], addr);
} }
tlb_debug("idx %d\n", mmu_idx);
tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
/* check whether there are vltb entries that need to be flushed */
for (k = 0; k < CPU_VTLB_SIZE; k++) {
tlb_flush_entry(&env->tlb_v_table[mmu_idx][k], addr);
} }
} }
va_end(argp);
tb_flush_jmp_cache(cpu, addr); tb_flush_jmp_cache(cpu, addr);
} }

13
qemu/include/exec/exec-all.h
View file

@ -118,21 +118,22 @@ void tlb_flush(CPUState *cpu);
* tlb_flush_page_by_mmuidx: * tlb_flush_page_by_mmuidx:
* @cpu: CPU whose TLB should be flushed * @cpu: CPU whose TLB should be flushed
* @addr: virtual address of page to be flushed * @addr: virtual address of page to be flushed
* @...: list of MMU indexes to flush, terminated by a negative value * @idxmap: bitmap of MMU indexes to flush
* *
* Flush one page from the TLB of the specified CPU, for the specified * Flush one page from the TLB of the specified CPU, for the specified
* MMU indexes. * MMU indexes.
*/ */
void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...); void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr,
uint16_t idxmap);
/** /**
* tlb_flush_by_mmuidx: * tlb_flush_by_mmuidx:
* @cpu: CPU whose TLB should be flushed * @cpu: CPU whose TLB should be flushed
* @...: list of MMU indexes to flush, terminated by a negative value * @idxmap: bitmap of MMU indexes to flush
* *
* Flush all entries from the TLB of the specified CPU, for the specified * Flush all entries from the TLB of the specified CPU, for the specified
* MMU indexes. * MMU indexes.
*/ */
void tlb_flush_by_mmuidx(CPUState *cpu, ...); void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap);
/** /**
* tlb_set_page_with_attrs: * tlb_set_page_with_attrs:
* @cpu: CPU to add this TLB entry for * @cpu: CPU to add this TLB entry for
@ -182,11 +183,11 @@ static inline void tlb_flush(CPUState *cpu)
} }
static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, static inline void tlb_flush_page_by_mmuidx(CPUState *cpu,
target_ulong addr, ...) target_ulong addr, uint16_t idxmap)
{ {
} }
static inline void tlb_flush_by_mmuidx(CPUState *cpu, ...) static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap)
{ {
} }
#endif #endif

156
qemu/target/arm/helper.c
View file

@ -476,8 +476,10 @@ static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
{ {
CPUState *cs = ENV_GET_CPU(env); CPUState *cs = ENV_GET_CPU(env);
tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, tlb_flush_by_mmuidx(cs,
ARMMMUIdx_S2NS, -1); (1 << ARMMMUIdx_S12NSE1) |
(1 << ARMMMUIdx_S12NSE0) |
(1 << ARMMMUIdx_S2NS));
} }
static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -487,8 +489,10 @@ static void tlbiall_nsnh_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
CPUState *other_cs; CPUState *other_cs;
CPU_FOREACH(other_cs) { CPU_FOREACH(other_cs) {
tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1, tlb_flush_by_mmuidx(other_cs,
ARMMMUIdx_S12NSE0, ARMMMUIdx_S2NS, -1); (1 << ARMMMUIdx_S12NSE1) |
(1 << ARMMMUIdx_S12NSE0) |
(1 << ARMMMUIdx_S2NS));
}*/ }*/
} }
@ -510,7 +514,7 @@ static void tlbiipas2_write(CPUARMState *env, const ARMCPRegInfo *ri,
pageaddr = sextract64(value << 12, 0, 40); pageaddr = sextract64(value << 12, 0, 40);
tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S2NS, -1); tlb_flush_page_by_mmuidx(cs, pageaddr, (1 << ARMMMUIdx_S2NS));
} }
static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -527,7 +531,7 @@ static void tlbiipas2_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
pageaddr = sextract64(value << 12, 0, 40); pageaddr = sextract64(value << 12, 0, 40);
CPU_FOREACH(other_cs) { CPU_FOREACH(other_cs) {
tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S2NS, -1); tlb_flush_page_by_mmuidx(other_cs, pageaddr, (1 << ARMMMUIdx_S2NS));
}*/ }*/
} }
@ -536,7 +540,7 @@ static void tlbiall_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
{ {
CPUState *cs = ENV_GET_CPU(env); CPUState *cs = ENV_GET_CPU(env);
tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E2, -1); tlb_flush_by_mmuidx(cs, (1 << ARMMMUIdx_S1E2));
} }
static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -546,7 +550,7 @@ static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
CPUState *other_cs; CPUState *other_cs;
CPU_FOREACH(other_cs) { CPU_FOREACH(other_cs) {
tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E2, -1); tlb_flush_by_mmuidx(other_cs, (1 << ARMMMUIdx_S1E2));
}*/ }*/
} }
@ -556,7 +560,7 @@ static void tlbimva_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri,
CPUState *cs = ENV_GET_CPU(env); CPUState *cs = ENV_GET_CPU(env);
uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E2, -1); tlb_flush_page_by_mmuidx(cs, pageaddr, (1 << ARMMMUIdx_S1E2));
} }
static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -567,7 +571,7 @@ static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12); uint64_t pageaddr = value & ~MAKE_64BIT_MASK(0, 12);
CPU_FOREACH(other_cs) { CPU_FOREACH(other_cs) {
tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1); tlb_flush_page_by_mmuidx(other_cs, pageaddr, (1 << ARMMMUIdx_S1E2));
}*/ }*/
} }
@ -2268,8 +2272,10 @@ static void vttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
/* Accesses to VTTBR may change the VMID so we must flush the TLB. */ /* Accesses to VTTBR may change the VMID so we must flush the TLB. */
if (raw_read(env, ri) != value) { if (raw_read(env, ri) != value) {
tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, tlb_flush_by_mmuidx(cs,
ARMMMUIdx_S2NS, -1); (1 << ARMMMUIdx_S12NSE1) |
(1 << ARMMMUIdx_S12NSE0) |
(1 << ARMMMUIdx_S2NS));
raw_write(env, ri, value); raw_write(env, ri, value);
} }
} }
@ -2587,28 +2593,36 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
CPUState *cs = CPU(cpu); CPUState *cs = CPU(cpu);
if (arm_is_secure_below_el3(env)) { if (arm_is_secure_below_el3(env)) {
tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1); tlb_flush_by_mmuidx(cs,
(1 << ARMMMUIdx_S1SE1) |
(1 << ARMMMUIdx_S1SE0));
} else { } else {
tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1); tlb_flush_by_mmuidx(cs,
(1 << ARMMMUIdx_S12NSE1) |
(1 << ARMMMUIdx_S12NSE0));
} }
} }
static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_vmalle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value) uint64_t value)
{ {
/* UNICORN: TODO: issue #642 // UNICORN: TODO: issue #642
#if 0
bool sec = arm_is_secure_below_el3(env); bool sec = arm_is_secure_below_el3(env);
CPUState *other_cs; CPUState *other_cs;
CPU_FOREACH(other_cs) { CPU_FOREACH(other_cs) {
if (sec) { if (sec) {
tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1); tlb_flush_by_mmuidx(other_cs,
(1 << ARMMMUIdx_S1SE1) |
(1 << ARMMMUIdx_S1SE0));
} else { } else {
tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1, tlb_flush_by_mmuidx(other_cs,
ARMMMUIdx_S12NSE0, -1); (1 << ARMMMUIdx_S12NSE1) |
(1 << ARMMMUIdx_S12NSE0));
} }
} }
*/ #endif
} }
static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -2623,13 +2637,19 @@ static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri,
CPUState *cs = CPU(cpu); CPUState *cs = CPU(cpu);
if (arm_is_secure_below_el3(env)) { if (arm_is_secure_below_el3(env)) {
tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1); tlb_flush_by_mmuidx(cs,
(1 << ARMMMUIdx_S1SE1) |
(1 << ARMMMUIdx_S1SE0));
} else { } else {
if (arm_feature(env, ARM_FEATURE_EL2)) { if (arm_feature(env, ARM_FEATURE_EL2)) {
tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, tlb_flush_by_mmuidx(cs,
ARMMMUIdx_S2NS, -1); (1 << ARMMMUIdx_S12NSE1) |
(1 << ARMMMUIdx_S12NSE0) |
(1 << ARMMMUIdx_S2NS));
} else { } else {
tlb_flush_by_mmuidx(cs, ARMMMUIdx_S12NSE1, ARMMMUIdx_S12NSE0, -1); tlb_flush_by_mmuidx(cs,
(1 << ARMMMUIdx_S12NSE1) |
(1 << ARMMMUIdx_S12NSE0));
} }
} }
} }
@ -2640,7 +2660,7 @@ static void tlbi_aa64_alle2_write(CPUARMState *env, const ARMCPRegInfo *ri,
ARMCPU *cpu = arm_env_get_cpu(env); ARMCPU *cpu = arm_env_get_cpu(env);
CPUState *cs = CPU(cpu); CPUState *cs = CPU(cpu);
tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E2, -1); tlb_flush_by_mmuidx(cs, (1 << ARMMMUIdx_S1E2));
} }
static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -2649,7 +2669,7 @@ static void tlbi_aa64_alle3_write(CPUARMState *env, const ARMCPRegInfo *ri,
ARMCPU *cpu = arm_env_get_cpu(env); ARMCPU *cpu = arm_env_get_cpu(env);
CPUState *cs = CPU(cpu); CPUState *cs = CPU(cpu);
tlb_flush_by_mmuidx(cs, ARMMMUIdx_S1E3, -1); tlb_flush_by_mmuidx(cs, (1 << ARMMMUIdx_S1E3));
} }
static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -2659,47 +2679,55 @@ static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
* stage 2 translations, whereas most other scopes only invalidate * stage 2 translations, whereas most other scopes only invalidate
* stage 1 translations. * stage 1 translations.
*/ */
/* UNICORN: TODO: issue #642 // UNICORN: TODO: issue #642
#if 0
bool sec = arm_is_secure_below_el3(env); bool sec = arm_is_secure_below_el3(env);
bool has_el2 = arm_feature(env, ARM_FEATURE_EL2); bool has_el2 = arm_feature(env, ARM_FEATURE_EL2);
CPUState *other_cs; CPUState *other_cs;
CPU_FOREACH(other_cs) { CPU_FOREACH(other_cs) {
if (sec) { if (sec) {
tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1SE1, ARMMMUIdx_S1SE0, -1); tlb_flush_by_mmuidx(other_cs,
(1 << ARMMMUIdx_S1SE1) |
(1 << ARMMMUIdx_S1SE0));
} else if (has_el2) { } else if (has_el2) {
tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1, tlb_flush_by_mmuidx(other_cs,
ARMMMUIdx_S12NSE0, ARMMMUIdx_S2NS, -1); (1 << ARMMMUIdx_S12NSE1) |
(1 << ARMMMUIdx_S12NSE0) |
(1 << ARMMMUIdx_S2NS));
} else { } else {
tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S12NSE1, tlb_flush_by_mmuidx(other_cs,
ARMMMUIdx_S12NSE0, -1); (1 << ARMMMUIdx_S12NSE1) |
(1 << ARMMMUIdx_S12NSE0));
} }
} }
*/ #endif
} }
static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_alle2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value) uint64_t value)
{ {
/* UNICORN: TODO: issue #642 // UNICORN: TODO: issue #642
#if 0
CPUState *other_cs; CPUState *other_cs;
CPU_FOREACH(other_cs) { CPU_FOREACH(other_cs) {
tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E2, -1); tlb_flush_by_mmuidx(other_cs, (1 << ARMMMUIdx_S1E2));
} }
*/ #endif
} }
static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_alle3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value) uint64_t value)
{ {
/* UNICORN: TODO: issue #642 // UNICORN: TODO: issue #642
#if 0
CPUState *other_cs; CPUState *other_cs;
CPU_FOREACH(other_cs) { CPU_FOREACH(other_cs) {
tlb_flush_by_mmuidx(other_cs, ARMMMUIdx_S1E3, -1); tlb_flush_by_mmuidx(other_cs, (1 << ARMMMUIdx_S1E3));
} }
*/ #endif
} }
static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -2715,11 +2743,13 @@ static void tlbi_aa64_vae1_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t pageaddr = sextract64(value << 12, 0, 56); uint64_t pageaddr = sextract64(value << 12, 0, 56);
if (arm_is_secure_below_el3(env)) { if (arm_is_secure_below_el3(env)) {
tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1SE1, tlb_flush_page_by_mmuidx(cs, pageaddr,
ARMMMUIdx_S1SE0, -1); (1 << ARMMMUIdx_S1SE1) |
(1 << ARMMMUIdx_S1SE0));
} else { } else {
tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S12NSE1, tlb_flush_page_by_mmuidx(cs, pageaddr,
ARMMMUIdx_S12NSE0, -1); (1 << ARMMMUIdx_S12NSE1) |
(1 << ARMMMUIdx_S12NSE0));
} }
} }
@ -2734,7 +2764,7 @@ static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri,
CPUState *cs = CPU(cpu); CPUState *cs = CPU(cpu);
uint64_t pageaddr = sextract64(value << 12, 0, 56); uint64_t pageaddr = sextract64(value << 12, 0, 56);
tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E2, -1); tlb_flush_page_by_mmuidx(cs, pageaddr, (1 << ARMMMUIdx_S1E2));
} }
static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -2748,53 +2778,58 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, const ARMCPRegInfo *ri,
CPUState *cs = CPU(cpu); CPUState *cs = CPU(cpu);
uint64_t pageaddr = sextract64(value << 12, 0, 56); uint64_t pageaddr = sextract64(value << 12, 0, 56);
tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S1E3, -1); tlb_flush_page_by_mmuidx(cs, pageaddr, (1 << ARMMMUIdx_S1E3));
} }
static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value) uint64_t value)
{ {
/* UNICORN: TODO: issue #642 // UNICORN: TODO: issue #642
#if 0
bool sec = arm_is_secure_below_el3(env); bool sec = arm_is_secure_below_el3(env);
CPUState *other_cs; CPUState *other_cs;
uint64_t pageaddr = sextract64(value << 12, 0, 56); uint64_t pageaddr = sextract64(value << 12, 0, 56);
CPU_FOREACH(other_cs) { CPU_FOREACH(other_cs) {
if (sec) { if (sec) {
tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1SE1, tlb_flush_page_by_mmuidx(other_cs, pageaddr,
ARMMMUIdx_S1SE0, -1); (1 << ARMMMUIdx_S1SE1) |
(1 << ARMMMUIdx_S1SE0));
} else { } else {
tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S12NSE1, tlb_flush_page_by_mmuidx(other_cs, pageaddr,
ARMMMUIdx_S12NSE0, -1); (1 << ARMMMUIdx_S12NSE1) |
(1 << ARMMMUIdx_S12NSE0));
} }
} }
*/ #endif
} }
static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value) uint64_t value)
{ {
/* UNICORN: TODO: issue #642 // UNICORN: TODO: issue #642
#if 0
CPUState *other_cs; CPUState *other_cs;
uint64_t pageaddr = sextract64(value << 12, 0, 56); uint64_t pageaddr = sextract64(value << 12, 0, 56);
CPU_FOREACH(other_cs) { CPU_FOREACH(other_cs) {
tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E2, -1); tlb_flush_page_by_mmuidx(other_cs, pageaddr, (1 << ARMMMUIdx_S1E2));
} }
*/ #endif
} }
static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_vae3is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value) uint64_t value)
{ {
/* UNICORN: TODO: issue #642 // UNICORN: TODO: issue #642
#if 0
CPUState *other_cs; CPUState *other_cs;
uint64_t pageaddr = sextract64(value << 12, 0, 56); uint64_t pageaddr = sextract64(value << 12, 0, 56);
CPU_FOREACH(other_cs) { CPU_FOREACH(other_cs) {
tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S1E3, -1); tlb_flush_page_by_mmuidx(other_cs, pageaddr, (1 << ARMMMUIdx_S1E3));
} }
*/ #endif
} }
static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -2816,13 +2851,14 @@ static void tlbi_aa64_ipas2e1_write(CPUARMState *env, const ARMCPRegInfo *ri,
pageaddr = sextract64(value << 12, 0, 48); pageaddr = sextract64(value << 12, 0, 48);
tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdx_S2NS, -1); tlb_flush_page_by_mmuidx(cs, pageaddr, (1 << ARMMMUIdx_S2NS));
} }
static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value) uint64_t value)
{ {
/* UNICORN: TODO: issue #642 // UNICORN: TODO: issue #642
#if 0
CPUState *other_cs; CPUState *other_cs;
uint64_t pageaddr; uint64_t pageaddr;
@ -2833,9 +2869,9 @@ static void tlbi_aa64_ipas2e1is_write(CPUARMState *env, const ARMCPRegInfo *ri,
pageaddr = sextract64(value << 12, 0, 48); pageaddr = sextract64(value << 12, 0, 48);
CPU_FOREACH(other_cs) { CPU_FOREACH(other_cs) {
tlb_flush_page_by_mmuidx(other_cs, pageaddr, ARMMMUIdx_S2NS, -1); tlb_flush_page_by_mmuidx(other_cs, pageaddr, (1 << ARMMMUIdx_S2NS));
} }
*/ #endif
} }
static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri, static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri,

8
qemu/target/sparc/ldst_helper.c
View file

@ -1773,13 +1773,15 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
case 1: case 1:
env->dmmu.mmu_primary_context = val; env->dmmu.mmu_primary_context = val;
env->immu.mmu_primary_context = val; env->immu.mmu_primary_context = val;
tlb_flush_by_mmuidx(CPU(cpu), MMU_USER_IDX, MMU_KERNEL_IDX, -1); tlb_flush_by_mmuidx(CPU(cpu),
(1 << MMU_USER_IDX) | (1 << MMU_KERNEL_IDX));
break; break;
case 2: case 2:
env->dmmu.mmu_secondary_context = val; env->dmmu.mmu_secondary_context = val;
env->immu.mmu_secondary_context = val; env->immu.mmu_secondary_context = val;
tlb_flush_by_mmuidx(CPU(cpu), MMU_USER_SECONDARY_IDX, tlb_flush_by_mmuidx(CPU(cpu),
MMU_KERNEL_SECONDARY_IDX, -1); (1 << MMU_USER_SECONDARY_IDX) |
(1 << MMU_KERNEL_SECONDARY_IDX));
break; break;
default: default:
cpu_unassigned_access(cs, addr, true, false, 1, size); cpu_unassigned_access(cs, addr, true, false, 1, size);