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target-i386: disable LINT0 after reset

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Due to old Seabios bug, QEMU reenable LINT0 after reset. This bug is long gone
and therefore this hack is no longer needed. Since it violates the
specifications, it is removed.

Backports commit b8eb5512fd8a115f164edbbe897cdf8884920ccb from qemu
This commit is contained in:
Nadav Amit 2018-02-12 21:07:08 -05:00 committed by Lioncash
parent edbc6f199c
commit 4680ceca1d
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1 changed files with 0 additions and 9 deletions
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9
qemu/hw/intc/apic_common.c
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@ -191,15 +191,6 @@ static void apic_reset_common(struct uc_struct *uc, DeviceState *dev)
info->vapic_base_update(s);
apic_init_reset(uc, dev);
if (bsp) {
/*
* LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
* time typically by BIOS, so PIC interrupt can be delivered to the
* processor when local APIC is enabled.
*/
s->lvt[APIC_LVT_LINT0] = 0x700;
}
}
static int apic_common_realize(struct uc_struct *uc, DeviceState *dev, Error **errp)