mirror of
https://github.com/yuzu-emu/unicorn.git
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arm: Take DisasContext as a parameter instead of TCGContext where applicable
This is more future-friendly with qemu, as it's more generic.
This commit is contained in:
Lioncash
parent
766c70f608
commit
47b45f1bc2
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@ -347,11 +347,12 @@ typedef struct DisasCompare64 {
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TCGv_i64 value;
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} DisasCompare64;
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static void a64_test_cc(TCGContext *tcg_ctx, DisasCompare64 *c64, int cc)
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static void a64_test_cc(DisasContext *s, DisasCompare64 *c64, int cc)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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DisasCompare c32;
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arm_test_cc(tcg_ctx, &c32, cc);
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arm_test_cc(s, &c32, cc);
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/* Sign-extend the 32-bit value so that the GE/LT comparisons work
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* properly. The NE/EQ comparisons are also fine with this choice. */
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@ -359,11 +360,13 @@ static void a64_test_cc(TCGContext *tcg_ctx, DisasCompare64 *c64, int cc)
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c64->value = tcg_temp_new_i64(tcg_ctx);
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tcg_gen_ext_i32_i64(tcg_ctx, c64->value, c32.value);
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arm_free_cc(tcg_ctx, &c32);
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arm_free_cc(s, &c32);
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}
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static void a64_free_cc(TCGContext *tcg_ctx, DisasCompare64 *c64)
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static void a64_free_cc(DisasContext *s, DisasCompare64 *c64)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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tcg_temp_free_i64(tcg_ctx, c64->value);
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}
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@ -682,8 +685,9 @@ static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v)
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tcg_temp_free_i64(tcg_ctx, tmp);
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}
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TCGv_ptr get_fpstatus_ptr(TCGContext *tcg_ctx, bool is_f16)
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TCGv_ptr get_fpstatus_ptr(DisasContext *s, bool is_f16)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv_ptr statusptr = tcg_temp_new_ptr(tcg_ctx);
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int offset;
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@ -791,7 +795,7 @@ static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn,
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, is_fp16);
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TCGv_ptr fpst = get_fpstatus_ptr(s, is_fp16);
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tcg_gen_gvec_3_ptr(tcg_ctx, vec_full_reg_offset(s, rd),
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vec_full_reg_offset(s, rn),
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vec_full_reg_offset(s, rm), fpst,
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@ -802,17 +806,20 @@ static void gen_gvec_op3_fpst(DisasContext *s, bool is_q, int rd, int rn,
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/* Set ZF and NF based on a 64 bit result. This is alas fiddlier
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* than the 32 bit equivalent.
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*/
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static inline void gen_set_NZ64(TCGContext *tcg_ctx, TCGv_i64 result)
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static inline void gen_set_NZ64(DisasContext *s, TCGv_i64 result)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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tcg_gen_extr_i64_i32(tcg_ctx, tcg_ctx->cpu_ZF, tcg_ctx->cpu_NF, result);
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tcg_gen_or_i32(tcg_ctx, tcg_ctx->cpu_ZF, tcg_ctx->cpu_ZF, tcg_ctx->cpu_NF);
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}
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/* Set NZCV as for a logical operation: NZ as per result, CV cleared. */
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static inline void gen_logic_CC(TCGContext *tcg_ctx, int sf, TCGv_i64 result)
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static inline void gen_logic_CC(DisasContext *s, int sf, TCGv_i64 result)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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if (sf) {
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gen_set_NZ64(tcg_ctx, result);
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gen_set_NZ64(s, result);
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} else {
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tcg_gen_extrl_i64_i32(tcg_ctx, tcg_ctx->cpu_ZF, result);
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tcg_gen_mov_i32(tcg_ctx, tcg_ctx->cpu_NF, tcg_ctx->cpu_ZF);
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@ -836,7 +843,7 @@ static void gen_add_CC(DisasContext *s, int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv
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tcg_gen_extrl_i64_i32(tcg_ctx, tcg_ctx->cpu_CF, flag);
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gen_set_NZ64(tcg_ctx, result);
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gen_set_NZ64(s, result);
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tcg_gen_xor_i64(tcg_ctx, flag, result, t0);
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tcg_gen_xor_i64(tcg_ctx, tmp, t0, t1);
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@ -881,7 +888,7 @@ static void gen_sub_CC(DisasContext *s, int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv
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flag = tcg_temp_new_i64(tcg_ctx);
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tcg_gen_sub_i64(tcg_ctx, result, t0, t1);
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gen_set_NZ64(tcg_ctx, result);
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gen_set_NZ64(s, result);
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tcg_gen_setcond_i64(tcg_ctx, TCG_COND_GEU, flag, t0, t1);
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tcg_gen_extrl_i64_i32(tcg_ctx, tcg_ctx->cpu_CF, flag);
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@ -947,7 +954,7 @@ static void gen_adc_CC(DisasContext *s, int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv
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tcg_gen_add2_i64(tcg_ctx, result, cf_64, t0, tmp, cf_64, tmp);
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tcg_gen_add2_i64(tcg_ctx, result, cf_64, result, cf_64, t1, tmp);
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tcg_gen_extrl_i64_i32(tcg_ctx, tcg_ctx->cpu_CF, cf_64);
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gen_set_NZ64(tcg_ctx, result);
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gen_set_NZ64(s, result);
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tcg_gen_xor_i64(tcg_ctx, vf_64, result, t0);
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tcg_gen_xor_i64(tcg_ctx, tmp, t0, t1);
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@ -1514,7 +1521,7 @@ static void disas_cond_b_imm(DisasContext *s, uint32_t insn)
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if (cond < 0x0e) {
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/* genuinely conditional branches */
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TCGLabel *label_match = gen_new_label(tcg_ctx);
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arm_gen_test_cc(tcg_ctx, cond, label_match);
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arm_gen_test_cc(s, cond, label_match);
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gen_goto_tb(s, 0, s->pc);
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gen_set_label(tcg_ctx, label_match);
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gen_goto_tb(s, 1, addr);
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@ -3616,7 +3623,7 @@ static void disas_logic_imm(DisasContext *s, uint32_t insn)
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}
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if (opc == 3) { /* ANDS */
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gen_logic_CC(tcg_ctx, sf, tcg_rd);
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gen_logic_CC(s, sf, tcg_rd);
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}
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}
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@ -3995,7 +4002,7 @@ static void disas_logic_reg(DisasContext *s, uint32_t insn)
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}
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if (opc == 3) {
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gen_logic_CC(tcg_ctx, sf, tcg_rd);
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gen_logic_CC(s, sf, tcg_rd);
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}
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}
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@ -4313,9 +4320,9 @@ static void disas_cc(DisasContext *s, uint32_t insn)
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/* Set T0 = !COND. */
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tcg_t0 = tcg_temp_new_i32(tcg_ctx);
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arm_test_cc(tcg_ctx, &c, cond);
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arm_test_cc(s, &c, cond);
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tcg_gen_setcondi_i32(tcg_ctx, tcg_invert_cond(c.cond), tcg_t0, c.value, 0);
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arm_free_cc(tcg_ctx, &c);
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arm_free_cc(s, &c);
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/* Load the arguments for the new comparison. */
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if (is_imm) {
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@ -4414,7 +4421,7 @@ static void disas_cond_select(DisasContext *s, uint32_t insn)
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tcg_rd = cpu_reg(s, rd);
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a64_test_cc(tcg_ctx, &c, cond);
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a64_test_cc(s, &c, cond);
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zero = tcg_const_i64(tcg_ctx, 0);
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if (rn == 31 && rm == 31 && (else_inc ^ else_inv)) {
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@ -4438,7 +4445,7 @@ static void disas_cond_select(DisasContext *s, uint32_t insn)
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}
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tcg_temp_free_i64(tcg_ctx, zero);
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a64_free_cc(tcg_ctx, &c);
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a64_free_cc(s, &c);
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if (!sf) {
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tcg_gen_ext32u_i64(tcg_ctx, tcg_rd, tcg_rd);
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@ -4806,7 +4813,7 @@ static void handle_fp_compare(DisasContext *s, int size,
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv_i64 tcg_flags = tcg_temp_new_i64(tcg_ctx);
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TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, size == MO_16);
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TCGv_ptr fpst = get_fpstatus_ptr(s, size == MO_16);
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if (size == MO_64) {
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TCGv_i64 tcg_vn, tcg_vm;
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@ -4966,7 +4973,7 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t insn)
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if (cond < 0x0e) { /* not always */
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TCGLabel *label_match = gen_new_label(tcg_ctx);
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label_continue = gen_new_label(tcg_ctx);
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arm_gen_test_cc(tcg_ctx, cond, label_match);
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arm_gen_test_cc(s, cond, label_match);
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/* nomatch: */
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tcg_flags = tcg_const_i64(tcg_ctx, nzcv << 28);
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gen_set_nzcv(tcg_ctx, tcg_flags);
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@ -5036,12 +5043,12 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
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read_vec_element(s, t_true, rn, 0, sz);
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read_vec_element(s, t_false, rm, 0, sz);
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a64_test_cc(tcg_ctx, &c, cond);
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a64_test_cc(s, &c, cond);
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t_zero = tcg_const_i64(tcg_ctx, 0);
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tcg_gen_movcond_i64(tcg_ctx, c.cond, t_true, c.value, t_zero, t_true, t_false);
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tcg_temp_free_i64(tcg_ctx, t_zero);
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tcg_temp_free_i64(tcg_ctx, t_false);
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a64_free_cc(tcg_ctx, &c);
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a64_free_cc(s, &c);
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/* Note that sregs & hregs write back zeros to the high bits,
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and we've already done the zero-extension. */
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@ -5068,7 +5075,7 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
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tcg_gen_xori_i32(tcg_ctx, tcg_res, tcg_op, 0x8000);
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break;
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case 0x3: /* FSQRT */
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fpst = get_fpstatus_ptr(tcg_ctx, true);
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fpst = get_fpstatus_ptr(s, true);
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gen_helper_sqrt_f16(tcg_ctx, tcg_res, tcg_op, fpst);
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break;
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case 0x8: /* FRINTN */
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@ -5078,7 +5085,7 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
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case 0xc: /* FRINTA */
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{
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TCGv_i32 tcg_rmode = tcg_const_i32(tcg_ctx, arm_rmode_to_sf(opcode & 7));
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fpst = get_fpstatus_ptr(tcg_ctx, true);
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fpst = get_fpstatus_ptr(s, true);
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gen_helper_set_rmode(tcg_ctx, tcg_rmode, tcg_rmode, fpst);
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gen_helper_advsimd_rinth(tcg_ctx, tcg_res, tcg_op, fpst);
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@ -5088,11 +5095,11 @@ static void handle_fp_1src_half(DisasContext *s, int opcode, int rd, int rn)
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break;
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}
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case 0xe: /* FRINTX */
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fpst = get_fpstatus_ptr(tcg_ctx, true);
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fpst = get_fpstatus_ptr(s, true);
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gen_helper_advsimd_rinth_exact(tcg_ctx, tcg_res, tcg_op, fpst);
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break;
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case 0xf: /* FRINTI */
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fpst = get_fpstatus_ptr(tcg_ctx, true);
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fpst = get_fpstatus_ptr(s, true);
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gen_helper_advsimd_rinth(tcg_ctx, tcg_res, tcg_op, fpst);
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break;
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default:
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@ -5116,7 +5123,7 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn)
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TCGv_i32 tcg_op;
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TCGv_i32 tcg_res;
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fpst = get_fpstatus_ptr(tcg_ctx, false);
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fpst = get_fpstatus_ptr(s, false);
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tcg_op = read_fp_sreg(s, rn);
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tcg_res = tcg_temp_new_i32(tcg_ctx);
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@ -5179,7 +5186,7 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn)
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return;
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}
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fpst = get_fpstatus_ptr(tcg_ctx, false);
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fpst = get_fpstatus_ptr(s, false);
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tcg_op = read_fp_dreg(s, rn);
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tcg_res = tcg_temp_new_i64(tcg_ctx);
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@ -5242,8 +5249,8 @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
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} else {
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/* Single to half */
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TCGv_i32 tcg_rd = tcg_temp_new_i32(tcg_ctx);
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TCGv_i32 ahp = get_ahp_flag(tcg_ctx);
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TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, false);
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TCGv_i32 ahp = get_ahp_flag(s);
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TCGv_ptr fpst = get_fpstatus_ptr(s, false);
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gen_helper_vfp_fcvt_f32_to_f16(tcg_ctx, tcg_rd, tcg_rn, fpst, ahp);
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/* write_fp_sreg is OK here because top half of tcg_rd is zero */
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@ -5263,8 +5270,8 @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
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/* Double to single */
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gen_helper_vfp_fcvtsd(tcg_ctx, tcg_rd, tcg_rn, tcg_ctx->cpu_env);
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} else {
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TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, false);
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TCGv_i32 ahp = get_ahp_flag(tcg_ctx);
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TCGv_ptr fpst = get_fpstatus_ptr(s, false);
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TCGv_i32 ahp = get_ahp_flag(s);
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/* Double to half */
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gen_helper_vfp_fcvt_f64_to_f16(tcg_ctx, tcg_rd, tcg_rn, fpst, ahp);
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/* write_fp_sreg is OK here because top half of tcg_rd is zero */
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@ -5279,8 +5286,8 @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
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case 0x3:
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{
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TCGv_i32 tcg_rn = read_fp_sreg(s, rn);
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TCGv_ptr tcg_fpst = get_fpstatus_ptr(tcg_ctx, false);
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TCGv_i32 tcg_ahp = get_ahp_flag(tcg_ctx);
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TCGv_ptr tcg_fpst = get_fpstatus_ptr(s, false);
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TCGv_i32 tcg_ahp = get_ahp_flag(s);
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tcg_gen_ext16u_i32(tcg_ctx, tcg_rn, tcg_rn);
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if (dtype == 0) {
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/* Half to single */
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@ -5386,7 +5393,7 @@ static void handle_fp_2src_single(DisasContext *s, int opcode,
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TCGv_ptr fpst;
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tcg_res = tcg_temp_new_i32(tcg_ctx);
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fpst = get_fpstatus_ptr(tcg_ctx, false);
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fpst = get_fpstatus_ptr(s, false);
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tcg_op1 = read_fp_sreg(s, rn);
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tcg_op2 = read_fp_sreg(s, rm);
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@ -5440,7 +5447,7 @@ static void handle_fp_2src_double(DisasContext *s, int opcode,
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TCGv_ptr fpst;
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tcg_res = tcg_temp_new_i64(tcg_ctx);
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fpst = get_fpstatus_ptr(tcg_ctx, false);
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fpst = get_fpstatus_ptr(s, false);
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tcg_op1 = read_fp_dreg(s, rn);
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tcg_op2 = read_fp_dreg(s, rm);
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@ -5495,7 +5502,7 @@ static void handle_fp_2src_half(DisasContext *s, int opcode,
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TCGv_ptr fpst;
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tcg_res = tcg_temp_new_i32(tcg_ctx);
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fpst = get_fpstatus_ptr(tcg_ctx, true);
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fpst = get_fpstatus_ptr(s, true);
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tcg_op1 = read_fp_hreg(s, rn);
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tcg_op2 = read_fp_hreg(s, rm);
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@ -5594,7 +5601,7 @@ static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
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TCGv_i32 tcg_res = tcg_temp_new_i32(tcg_ctx);
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TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, false);
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TCGv_ptr fpst = get_fpstatus_ptr(s, false);
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tcg_op1 = read_fp_sreg(s, rn);
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tcg_op2 = read_fp_sreg(s, rm);
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@ -5633,7 +5640,7 @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv_i64 tcg_op1, tcg_op2, tcg_op3;
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TCGv_i64 tcg_res = tcg_temp_new_i64(tcg_ctx);
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TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, false);
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TCGv_ptr fpst = get_fpstatus_ptr(s, false);
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tcg_op1 = read_fp_dreg(s, rn);
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tcg_op2 = read_fp_dreg(s, rm);
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@ -5673,7 +5680,7 @@ static void handle_fp_3src_half(DisasContext *s, bool o0, bool o1,
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|||
|
||||
TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
|
||||
TCGv_i32 tcg_res = tcg_temp_new_i32(tcg_ctx);
|
||||
TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, true);
|
||||
TCGv_ptr fpst = get_fpstatus_ptr(s, true);
|
||||
|
||||
tcg_op1 = read_fp_hreg(s, rn);
|
||||
tcg_op2 = read_fp_hreg(s, rm);
|
||||
|
|
@ -5840,7 +5847,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode,
|
|||
TCGv_i32 tcg_shift, tcg_single;
|
||||
TCGv_i64 tcg_double;
|
||||
|
||||
tcg_fpstatus = get_fpstatus_ptr(tcg_ctx, type == 3);
|
||||
tcg_fpstatus = get_fpstatus_ptr(s, type == 3);
|
||||
|
||||
tcg_shift = tcg_const_i32(tcg_ctx, 64 - scale);
|
||||
|
||||
|
|
@ -6706,7 +6713,7 @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
|
|||
* Note that correct NaN propagation requires that we do these
|
||||
* operations in exactly the order specified by the pseudocode.
|
||||
*/
|
||||
TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, size == MO_16);
|
||||
TCGv_ptr fpst = get_fpstatus_ptr(s, size == MO_16);
|
||||
int fpopcode = opcode | is_min << 4 | is_u << 5;
|
||||
int vmap = (1 << elements) - 1;
|
||||
TCGv_i32 tcg_res32 = do_reduction_op(s, fpopcode, rn, esize,
|
||||
|
|
@ -7218,7 +7225,7 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
|
|||
return;
|
||||
}
|
||||
|
||||
fpst = get_fpstatus_ptr(tcg_ctx, size == MO_16);
|
||||
fpst = get_fpstatus_ptr(s, size == MO_16);
|
||||
break;
|
||||
default:
|
||||
unallocated_encoding(s);
|
||||
|
|
@ -7737,7 +7744,7 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn,
|
|||
int fracbits, int size)
|
||||
{
|
||||
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
||||
TCGv_ptr tcg_fpst = get_fpstatus_ptr(tcg_ctx, size == MO_16);
|
||||
TCGv_ptr tcg_fpst = get_fpstatus_ptr(s, size == MO_16);
|
||||
TCGv_i32 tcg_shift = NULL;
|
||||
|
||||
TCGMemOp mop = size | (is_signed ? MO_SIGN : 0);
|
||||
|
|
@ -7919,7 +7926,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar,
|
|||
assert(!(is_scalar && is_q));
|
||||
|
||||
tcg_rmode = tcg_const_i32(tcg_ctx, arm_rmode_to_sf(FPROUNDING_ZERO));
|
||||
tcg_fpstatus = get_fpstatus_ptr(tcg_ctx, size == MO_16);
|
||||
tcg_fpstatus = get_fpstatus_ptr(s, size == MO_16);
|
||||
gen_helper_set_rmode(tcg_ctx, tcg_rmode, tcg_rmode, tcg_fpstatus);
|
||||
fracbits = (16 << size) - immhb;
|
||||
tcg_shift = tcg_const_i32(tcg_ctx, fracbits);
|
||||
|
|
@ -8283,7 +8290,7 @@ static void handle_3same_float(DisasContext *s, int size, int elements,
|
|||
{
|
||||
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
||||
int pass;
|
||||
TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, false);
|
||||
TCGv_ptr fpst = get_fpstatus_ptr(s, false);
|
||||
|
||||
for (pass = 0; pass < elements; pass++) {
|
||||
if (size) {
|
||||
|
|
@ -8678,7 +8685,7 @@ static void disas_simd_scalar_three_reg_same_fp16(DisasContext *s,
|
|||
return;
|
||||
}
|
||||
|
||||
fpst = get_fpstatus_ptr(tcg_ctx, true);
|
||||
fpst = get_fpstatus_ptr(s, true);
|
||||
|
||||
tcg_op1 = read_fp_hreg(s, rn);
|
||||
tcg_op2 = read_fp_hreg(s, rm);
|
||||
|
|
@ -8930,7 +8937,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode,
|
|||
return;
|
||||
}
|
||||
|
||||
fpst = get_fpstatus_ptr(tcg_ctx, size == MO_16);
|
||||
fpst = get_fpstatus_ptr(s, size == MO_16);
|
||||
|
||||
if (is_double) {
|
||||
TCGv_i64 tcg_op = tcg_temp_new_i64(tcg_ctx);
|
||||
|
|
@ -9061,7 +9068,7 @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode,
|
|||
{
|
||||
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
||||
bool is_double = (size == 3);
|
||||
TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, false);
|
||||
TCGv_ptr fpst = get_fpstatus_ptr(s, false);
|
||||
|
||||
if (is_double) {
|
||||
TCGv_i64 tcg_op = tcg_temp_new_i64(tcg_ctx);
|
||||
|
|
@ -9203,8 +9210,8 @@ static void handle_2misc_narrow(DisasContext *s, bool scalar,
|
|||
} else {
|
||||
TCGv_i32 tcg_lo = tcg_temp_new_i32(tcg_ctx);
|
||||
TCGv_i32 tcg_hi = tcg_temp_new_i32(tcg_ctx);
|
||||
TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, false);
|
||||
TCGv_i32 ahp = get_ahp_flag(tcg_ctx);
|
||||
TCGv_ptr fpst = get_fpstatus_ptr(s, false);
|
||||
TCGv_i32 ahp = get_ahp_flag(s);
|
||||
|
||||
tcg_gen_extr_i64_i32(tcg_ctx, tcg_lo, tcg_hi, tcg_op);
|
||||
gen_helper_vfp_fcvt_f32_to_f16(tcg_ctx, tcg_lo, tcg_lo, fpst, ahp);
|
||||
|
|
@ -9467,7 +9474,7 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn)
|
|||
|
||||
if (is_fcvt) {
|
||||
tcg_rmode = tcg_const_i32(tcg_ctx, arm_rmode_to_sf(rmode));
|
||||
tcg_fpstatus = get_fpstatus_ptr(tcg_ctx, false);
|
||||
tcg_fpstatus = get_fpstatus_ptr(s, false);
|
||||
gen_helper_set_rmode(tcg_ctx, tcg_rmode, tcg_rmode, tcg_fpstatus);
|
||||
} else {
|
||||
tcg_rmode = NULL;
|
||||
|
|
@ -10672,7 +10679,7 @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode,
|
|||
|
||||
/* Floating point operations need fpst */
|
||||
if (opcode >= 0x58) {
|
||||
fpst = get_fpstatus_ptr(tcg_ctx, false);
|
||||
fpst = get_fpstatus_ptr(s, false);
|
||||
} else {
|
||||
fpst = NULL;
|
||||
}
|
||||
|
|
@ -11406,7 +11413,7 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
|
|||
break;
|
||||
}
|
||||
|
||||
fpst = get_fpstatus_ptr(tcg_ctx, true);
|
||||
fpst = get_fpstatus_ptr(s, true);
|
||||
|
||||
if (pairwise) {
|
||||
int maxpass = is_q ? 8 : 4;
|
||||
|
|
@ -11716,8 +11723,8 @@ static void handle_2misc_widening(DisasContext *s, int opcode, bool is_q,
|
|||
/* 16 -> 32 bit fp conversion */
|
||||
int srcelt = is_q ? 4 : 0;
|
||||
TCGv_i32 tcg_res[4];
|
||||
TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, false);
|
||||
TCGv_i32 ahp = get_ahp_flag(tcg_ctx);
|
||||
TCGv_ptr fpst = get_fpstatus_ptr(s, false);
|
||||
TCGv_i32 ahp = get_ahp_flag(s);
|
||||
|
||||
for (pass = 0; pass < 4; pass++) {
|
||||
tcg_res[pass] = tcg_temp_new_i32(tcg_ctx);
|
||||
|
|
@ -12181,7 +12188,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
|
|||
}
|
||||
|
||||
if (need_fpstatus || need_rmode) {
|
||||
tcg_fpstatus = get_fpstatus_ptr(tcg_ctx, false);
|
||||
tcg_fpstatus = get_fpstatus_ptr(s, false);
|
||||
} else {
|
||||
tcg_fpstatus = NULL;
|
||||
}
|
||||
|
|
@ -12621,7 +12628,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn)
|
|||
}
|
||||
|
||||
if (need_rmode || need_fpst) {
|
||||
tcg_fpstatus = get_fpstatus_ptr(tcg_ctx, true);
|
||||
tcg_fpstatus = get_fpstatus_ptr(s, true);
|
||||
}
|
||||
|
||||
if (need_rmode) {
|
||||
|
|
@ -12920,7 +12927,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn)
|
|||
}
|
||||
|
||||
if (is_fp) {
|
||||
fpst = get_fpstatus_ptr(tcg_ctx, is_fp16);
|
||||
fpst = get_fpstatus_ptr(s, is_fp16);
|
||||
} else {
|
||||
fpst = NULL;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -36,7 +36,7 @@ TCGv_i64 cpu_reg_sp(DisasContext *s, int reg);
|
|||
TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf);
|
||||
TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf);
|
||||
void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v);
|
||||
TCGv_ptr get_fpstatus_ptr(TCGContext *, bool);
|
||||
TCGv_ptr get_fpstatus_ptr(DisasContext *, bool);
|
||||
bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn,
|
||||
unsigned int imms, unsigned int immr);
|
||||
uint64_t vfp_expand_imm(int size, uint8_t imm8);
|
||||
|
|
|
|||
|
|
@ -3627,7 +3627,7 @@ static bool trans_FMLA_zzxz(DisasContext *s, arg_FMLA_zzxz *a, uint32_t insn)
|
|||
if (sve_access_check(s)) {
|
||||
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
||||
unsigned vsz = vec_full_reg_size(s);
|
||||
TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16);
|
||||
TCGv_ptr status = get_fpstatus_ptr(s, a->esz == MO_16);
|
||||
tcg_gen_gvec_4_ptr(tcg_ctx, vec_full_reg_offset(s, a->rd),
|
||||
vec_full_reg_offset(s, a->rn),
|
||||
vec_full_reg_offset(s, a->rm),
|
||||
|
|
@ -3654,7 +3654,7 @@ static bool trans_FMUL_zzx(DisasContext *s, arg_FMUL_zzx *a, uint32_t insn)
|
|||
if (sve_access_check(s)) {
|
||||
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
||||
unsigned vsz = vec_full_reg_size(s);
|
||||
TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16);
|
||||
TCGv_ptr status = get_fpstatus_ptr(s, a->esz == MO_16);
|
||||
tcg_gen_gvec_3_ptr(tcg_ctx, vec_full_reg_offset(s, a->rd),
|
||||
vec_full_reg_offset(s, a->rn),
|
||||
vec_full_reg_offset(s, a->rm),
|
||||
|
|
@ -3687,7 +3687,7 @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a,
|
|||
|
||||
tcg_gen_addi_ptr(tcg_ctx, t_zn, tcg_ctx->cpu_env, vec_full_reg_offset(s, a->rn));
|
||||
tcg_gen_addi_ptr(tcg_ctx, t_pg, tcg_ctx->cpu_env, pred_full_reg_offset(s, a->pg));
|
||||
status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16);
|
||||
status = get_fpstatus_ptr(s, a->esz == MO_16);
|
||||
|
||||
fn(tcg_ctx, temp, t_zn, t_pg, status, t_desc);
|
||||
tcg_temp_free_ptr(tcg_ctx, t_zn);
|
||||
|
|
@ -3730,7 +3730,7 @@ static void do_zz_fp(DisasContext *s, arg_rr_esz *a, gen_helper_gvec_2_ptr *fn)
|
|||
{
|
||||
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
||||
unsigned vsz = vec_full_reg_size(s);
|
||||
TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16);
|
||||
TCGv_ptr status = get_fpstatus_ptr(s, a->esz == MO_16);
|
||||
|
||||
tcg_gen_gvec_2_ptr(tcg_ctx, vec_full_reg_offset(s, a->rd),
|
||||
vec_full_reg_offset(s, a->rn),
|
||||
|
|
@ -3779,7 +3779,7 @@ static void do_ppz_fp(DisasContext *s, arg_rpr_esz *a,
|
|||
{
|
||||
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
||||
unsigned vsz = vec_full_reg_size(s);
|
||||
TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16);
|
||||
TCGv_ptr status = get_fpstatus_ptr(s, a->esz == MO_16);
|
||||
|
||||
tcg_gen_gvec_3_ptr(tcg_ctx, pred_full_reg_offset(s, a->rd),
|
||||
vec_full_reg_offset(s, a->rn),
|
||||
|
|
@ -3832,7 +3832,7 @@ static bool trans_FTMAD(DisasContext *s, arg_FTMAD *a, uint32_t insn)
|
|||
if (sve_access_check(s)) {
|
||||
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
||||
unsigned vsz = vec_full_reg_size(s);
|
||||
TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16);
|
||||
TCGv_ptr status = get_fpstatus_ptr(s, a->esz == MO_16);
|
||||
tcg_gen_gvec_3_ptr(tcg_ctx, vec_full_reg_offset(s, a->rd),
|
||||
vec_full_reg_offset(s, a->rn),
|
||||
vec_full_reg_offset(s, a->rm),
|
||||
|
|
@ -3873,7 +3873,7 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_esz *a, uint32_t insn)
|
|||
t_pg = tcg_temp_new_ptr(tcg_ctx);
|
||||
tcg_gen_addi_ptr(tcg_ctx, t_rm, tcg_ctx->cpu_env, vec_full_reg_offset(s, a->rm));
|
||||
tcg_gen_addi_ptr(tcg_ctx, t_pg, tcg_ctx->cpu_env, pred_full_reg_offset(s, a->pg));
|
||||
t_fpst = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16);
|
||||
t_fpst = get_fpstatus_ptr(s, a->esz == MO_16);
|
||||
t_desc = tcg_const_i32(tcg_ctx, simd_desc(vsz, vsz, 0));
|
||||
|
||||
fns[a->esz - 1](tcg_ctx, t_val, t_val, t_rm, t_pg, t_fpst, t_desc);
|
||||
|
|
@ -3901,7 +3901,7 @@ static bool do_zzz_fp(DisasContext *s, arg_rrr_esz *a,
|
|||
if (sve_access_check(s)) {
|
||||
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
||||
unsigned vsz = vec_full_reg_size(s);
|
||||
TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16);
|
||||
TCGv_ptr status = get_fpstatus_ptr(s, a->esz == MO_16);
|
||||
tcg_gen_gvec_3_ptr(tcg_ctx, vec_full_reg_offset(s, a->rd),
|
||||
vec_full_reg_offset(s, a->rn),
|
||||
vec_full_reg_offset(s, a->rm),
|
||||
|
|
@ -3944,7 +3944,7 @@ static bool do_zpzz_fp(DisasContext *s, arg_rprr_esz *a,
|
|||
if (sve_access_check(s)) {
|
||||
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
||||
unsigned vsz = vec_full_reg_size(s);
|
||||
TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16);
|
||||
TCGv_ptr status = get_fpstatus_ptr(s, a->esz == MO_16);
|
||||
tcg_gen_gvec_4_ptr(tcg_ctx, vec_full_reg_offset(s, a->rd),
|
||||
vec_full_reg_offset(s, a->rn),
|
||||
vec_full_reg_offset(s, a->rm),
|
||||
|
|
@ -3997,7 +3997,7 @@ static void do_fp_scalar(DisasContext *s, int zd, int zn, int pg, bool is_fp16,
|
|||
tcg_gen_addi_ptr(tcg_ctx, t_zn, tcg_ctx->cpu_env, vec_full_reg_offset(s, zn));
|
||||
tcg_gen_addi_ptr(tcg_ctx, t_pg, tcg_ctx->cpu_env, pred_full_reg_offset(s, pg));
|
||||
|
||||
status = get_fpstatus_ptr(tcg_ctx, is_fp16);
|
||||
status = get_fpstatus_ptr(s, is_fp16);
|
||||
desc = tcg_const_i32(tcg_ctx, simd_desc(vsz, vsz, 0));
|
||||
fn(tcg_ctx, t_zd, t_zn, t_pg, scalar, status, desc);
|
||||
|
||||
|
|
@ -4064,7 +4064,7 @@ static bool do_fp_cmp(DisasContext *s, arg_rprr_esz *a,
|
|||
if (sve_access_check(s)) {
|
||||
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
||||
unsigned vsz = vec_full_reg_size(s);
|
||||
TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16);
|
||||
TCGv_ptr status = get_fpstatus_ptr(s, a->esz == MO_16);
|
||||
tcg_gen_gvec_4_ptr(tcg_ctx, pred_full_reg_offset(s, a->rd),
|
||||
vec_full_reg_offset(s, a->rn),
|
||||
vec_full_reg_offset(s, a->rm),
|
||||
|
|
@ -4110,7 +4110,7 @@ static bool trans_FCADD(DisasContext *s, arg_FCADD *a, uint32_t insn)
|
|||
if (sve_access_check(s)) {
|
||||
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
||||
unsigned vsz = vec_full_reg_size(s);
|
||||
TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16);
|
||||
TCGv_ptr status = get_fpstatus_ptr(s, a->esz == MO_16);
|
||||
tcg_gen_gvec_4_ptr(tcg_ctx, vec_full_reg_offset(s, a->rd),
|
||||
vec_full_reg_offset(s, a->rn),
|
||||
vec_full_reg_offset(s, a->rm),
|
||||
|
|
@ -4221,7 +4221,7 @@ static bool trans_FCMLA_zzxz(DisasContext *s, arg_FCMLA_zzxz *a, uint32_t insn)
|
|||
if (sve_access_check(s)) {
|
||||
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
||||
unsigned vsz = vec_full_reg_size(s);
|
||||
TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16);
|
||||
TCGv_ptr status = get_fpstatus_ptr(s, a->esz == MO_16);
|
||||
tcg_gen_gvec_3_ptr(tcg_ctx, vec_full_reg_offset(s, a->rd),
|
||||
vec_full_reg_offset(s, a->rn),
|
||||
vec_full_reg_offset(s, a->rm),
|
||||
|
|
@ -4243,7 +4243,7 @@ static bool do_zpz_ptr(DisasContext *s, int rd, int rn, int pg,
|
|||
if (sve_access_check(s)) {
|
||||
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
||||
unsigned vsz = vec_full_reg_size(s);
|
||||
TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, is_fp16);
|
||||
TCGv_ptr status = get_fpstatus_ptr(s, is_fp16);
|
||||
tcg_gen_gvec_3_ptr(tcg_ctx, vec_full_reg_offset(s, rd),
|
||||
vec_full_reg_offset(s, rn),
|
||||
pred_full_reg_offset(s, pg),
|
||||
|
|
@ -4390,7 +4390,7 @@ static bool do_frint_mode(DisasContext *s, arg_rpr_esz *a, int mode)
|
|||
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
||||
unsigned vsz = vec_full_reg_size(s);
|
||||
TCGv_i32 tmode = tcg_const_i32(tcg_ctx, mode);
|
||||
TCGv_ptr status = get_fpstatus_ptr(tcg_ctx, a->esz == MO_16);
|
||||
TCGv_ptr status = get_fpstatus_ptr(s, a->esz == MO_16);
|
||||
|
||||
gen_helper_set_rmode(tcg_ctx, tmode, tmode, status);
|
||||
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load diff
|
|
@ -171,14 +171,15 @@ static inline void gen_a64_set_pc_im(DisasContext *s, uint64_t val)
|
|||
}
|
||||
#endif
|
||||
|
||||
void arm_test_cc(TCGContext *tcg_ctx, DisasCompare *cmp, int cc);
|
||||
void arm_free_cc(TCGContext *tcg_ctx, DisasCompare *cmp);
|
||||
void arm_jump_cc(TCGContext *tcg_ctx, DisasCompare *cmp, TCGLabel *label);
|
||||
void arm_gen_test_cc(TCGContext *tcg_ctx, int cc, TCGLabel *label);
|
||||
void arm_test_cc(DisasContext *s, DisasCompare *cmp, int cc);
|
||||
void arm_free_cc(DisasContext *s, DisasCompare *cmp);
|
||||
void arm_jump_cc(DisasContext *s, DisasCompare *cmp, TCGLabel *label);
|
||||
void arm_gen_test_cc(DisasContext *s, int cc, TCGLabel *label);
|
||||
|
||||
/* Return state of Alternate Half-precision flag, caller frees result */
|
||||
static inline TCGv_i32 get_ahp_flag(TCGContext *tcg_ctx)
|
||||
static inline TCGv_i32 get_ahp_flag(DisasContext *s)
|
||||
{
|
||||
TCGContext *tcg_ctx = s->uc->tcg_ctx;
|
||||
TCGv_i32 ret = tcg_temp_new_i32(tcg_ctx);
|
||||
|
||||
tcg_gen_ld_i32(tcg_ctx, ret, tcg_ctx->cpu_env,
|
||||
|
|
|
|||
Loading…
Reference in a new issue