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https://github.com/yuzu-emu/unicorn.git
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uc_x86_mmr type available in qemu/target-i386/unicorn.c
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59f7bf3be7
commit
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@ -10,12 +10,12 @@ extern "C" {
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//Memory-Management Register fields (idtr, gdtr, ldtr, tr)
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//borrow from SegmentCache in qemu/target-i386/cpu.h
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typedef struct x86_mmr {
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uint32_t selector;
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uint64_t base; /* handle 32 or 64 bit CPUs */
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typedef struct uc_x86_mmr {
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uint16_t selector; /* not used by gdtr and idtr */
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uint64_t base; /* handle 32 or 64 bit CPUs */
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uint32_t limit;
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uint32_t flags;
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} x86_mmr;
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uint32_t flags; /* not used by gdtr and idtr */
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} uc_x86_mmr;
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// Callback function for tracing SYSCALL/SYSENTER (for uc_hook_intr())
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// @user_data: user data passed to tracing APIs.
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@ -699,7 +699,7 @@ typedef enum {
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typedef struct SegmentCache {
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uint32_t selector;
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uint64_t base; /* handle 32 or 64 bit CPUs */
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target_ulong base;
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uint32_t limit;
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uint32_t flags;
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} SegmentCache;
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@ -9,6 +9,7 @@
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#include "tcg.h"
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#include "unicorn_common.h"
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#include <unicorn/x86.h> /* needed for uc_x86_mmr */
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#define READ_QWORD(x) ((uint64)x)
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#define READ_DWORD(x) (x & 0xffffffff)
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@ -278,24 +279,24 @@ int x86_reg_read(struct uc_struct *uc, unsigned int regid, void *value)
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*(int32_t *)value = X86_CPU(uc, mycpu)->env.segs[R_GS].base;
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break;
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case UC_X86_REG_IDTR:
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((SegmentCache *)value)->limit = (uint16_t)X86_CPU(uc, mycpu)->env.idt.limit;
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((SegmentCache *)value)->base = (uint32_t)X86_CPU(uc, mycpu)->env.idt.base;
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((uc_x86_mmr *)value)->limit = (uint16_t)X86_CPU(uc, mycpu)->env.idt.limit;
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((uc_x86_mmr *)value)->base = (uint32_t)X86_CPU(uc, mycpu)->env.idt.base;
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break;
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case UC_X86_REG_GDTR:
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((SegmentCache *)value)->limit = (uint16_t)X86_CPU(uc, mycpu)->env.gdt.limit;
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((SegmentCache *)value)->base = (uint32_t)X86_CPU(uc, mycpu)->env.gdt.base;
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((uc_x86_mmr *)value)->limit = (uint16_t)X86_CPU(uc, mycpu)->env.gdt.limit;
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((uc_x86_mmr *)value)->base = (uint32_t)X86_CPU(uc, mycpu)->env.gdt.base;
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break;
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case UC_X86_REG_LDTR:
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((SegmentCache *)value)->limit = X86_CPU(uc, mycpu)->env.ldt.limit;
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((SegmentCache *)value)->base = (uint32_t)X86_CPU(uc, mycpu)->env.ldt.base;
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((SegmentCache *)value)->selector = (uint16_t)X86_CPU(uc, mycpu)->env.ldt.selector;
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((SegmentCache *)value)->flags = X86_CPU(uc, mycpu)->env.ldt.flags;
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((uc_x86_mmr *)value)->limit = X86_CPU(uc, mycpu)->env.ldt.limit;
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((uc_x86_mmr *)value)->base = (uint32_t)X86_CPU(uc, mycpu)->env.ldt.base;
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((uc_x86_mmr *)value)->selector = (uint16_t)X86_CPU(uc, mycpu)->env.ldt.selector;
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((uc_x86_mmr *)value)->flags = X86_CPU(uc, mycpu)->env.ldt.flags;
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break;
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case UC_X86_REG_TR:
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((SegmentCache *)value)->limit = X86_CPU(uc, mycpu)->env.tr.limit;
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((SegmentCache *)value)->base = (uint32_t)X86_CPU(uc, mycpu)->env.tr.base;
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((SegmentCache *)value)->selector = (uint16_t)X86_CPU(uc, mycpu)->env.tr.selector;
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((SegmentCache *)value)->flags = X86_CPU(uc, mycpu)->env.tr.flags;
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((uc_x86_mmr *)value)->limit = X86_CPU(uc, mycpu)->env.tr.limit;
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((uc_x86_mmr *)value)->base = (uint32_t)X86_CPU(uc, mycpu)->env.tr.base;
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((uc_x86_mmr *)value)->selector = (uint16_t)X86_CPU(uc, mycpu)->env.tr.selector;
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((uc_x86_mmr *)value)->flags = X86_CPU(uc, mycpu)->env.tr.flags;
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break;
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}
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break;
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@ -546,24 +547,24 @@ int x86_reg_read(struct uc_struct *uc, unsigned int regid, void *value)
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*(int8_t *)value = READ_BYTE_L(X86_CPU(uc, mycpu)->env.regs[15]);
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break;
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case UC_X86_REG_IDTR:
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((SegmentCache *)value)->limit = (uint16_t)X86_CPU(uc, mycpu)->env.idt.limit;
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((SegmentCache *)value)->base = X86_CPU(uc, mycpu)->env.idt.base;
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((uc_x86_mmr *)value)->limit = (uint16_t)X86_CPU(uc, mycpu)->env.idt.limit;
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((uc_x86_mmr *)value)->base = X86_CPU(uc, mycpu)->env.idt.base;
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break;
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case UC_X86_REG_GDTR:
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((SegmentCache *)value)->limit = (uint16_t)X86_CPU(uc, mycpu)->env.gdt.limit;
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((SegmentCache *)value)->base = X86_CPU(uc, mycpu)->env.gdt.base;
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((uc_x86_mmr *)value)->limit = (uint16_t)X86_CPU(uc, mycpu)->env.gdt.limit;
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((uc_x86_mmr *)value)->base = X86_CPU(uc, mycpu)->env.gdt.base;
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break;
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case UC_X86_REG_LDTR:
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((SegmentCache *)value)->limit = X86_CPU(uc, mycpu)->env.ldt.limit;
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((SegmentCache *)value)->base = X86_CPU(uc, mycpu)->env.ldt.base;
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((SegmentCache *)value)->selector = (uint16_t)X86_CPU(uc, mycpu)->env.ldt.selector;
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((SegmentCache *)value)->flags = X86_CPU(uc, mycpu)->env.ldt.flags;
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((uc_x86_mmr *)value)->limit = X86_CPU(uc, mycpu)->env.ldt.limit;
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((uc_x86_mmr *)value)->base = X86_CPU(uc, mycpu)->env.ldt.base;
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((uc_x86_mmr *)value)->selector = (uint16_t)X86_CPU(uc, mycpu)->env.ldt.selector;
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((uc_x86_mmr *)value)->flags = X86_CPU(uc, mycpu)->env.ldt.flags;
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break;
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case UC_X86_REG_TR:
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((SegmentCache *)value)->limit = X86_CPU(uc, mycpu)->env.tr.limit;
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((SegmentCache *)value)->base = X86_CPU(uc, mycpu)->env.tr.base;
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((SegmentCache *)value)->selector = (uint16_t)X86_CPU(uc, mycpu)->env.tr.selector;
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((SegmentCache *)value)->flags = X86_CPU(uc, mycpu)->env.tr.flags;
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((uc_x86_mmr *)value)->limit = X86_CPU(uc, mycpu)->env.tr.limit;
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((uc_x86_mmr *)value)->base = X86_CPU(uc, mycpu)->env.tr.base;
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((uc_x86_mmr *)value)->selector = (uint16_t)X86_CPU(uc, mycpu)->env.tr.selector;
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((uc_x86_mmr *)value)->flags = X86_CPU(uc, mycpu)->env.tr.flags;
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break;
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}
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break;
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@ -725,24 +726,24 @@ int x86_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
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X86_CPU(uc, mycpu)->env.segs[R_GS].base = *(uint32_t *)value;
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break;
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case UC_X86_REG_IDTR:
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X86_CPU(uc, mycpu)->env.idt.limit = (uint16_t)((SegmentCache *)value)->limit;
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X86_CPU(uc, mycpu)->env.idt.base = (uint32_t)((SegmentCache *)value)->base;
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X86_CPU(uc, mycpu)->env.idt.limit = (uint16_t)((uc_x86_mmr *)value)->limit;
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X86_CPU(uc, mycpu)->env.idt.base = (uint32_t)((uc_x86_mmr *)value)->base;
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break;
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case UC_X86_REG_GDTR:
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X86_CPU(uc, mycpu)->env.gdt.limit = (uint16_t)((SegmentCache *)value)->limit;
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X86_CPU(uc, mycpu)->env.gdt.base = (uint32_t)((SegmentCache *)value)->base;
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X86_CPU(uc, mycpu)->env.gdt.limit = (uint16_t)((uc_x86_mmr *)value)->limit;
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X86_CPU(uc, mycpu)->env.gdt.base = (uint32_t)((uc_x86_mmr *)value)->base;
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break;
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case UC_X86_REG_LDTR:
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X86_CPU(uc, mycpu)->env.ldt.limit = ((SegmentCache *)value)->limit;
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X86_CPU(uc, mycpu)->env.ldt.base = (uint32_t)((SegmentCache *)value)->base;
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X86_CPU(uc, mycpu)->env.ldt.selector = (uint16_t)((SegmentCache *)value)->selector;
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X86_CPU(uc, mycpu)->env.ldt.flags = ((SegmentCache *)value)->flags;
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X86_CPU(uc, mycpu)->env.ldt.limit = (uint16_t)((uc_x86_mmr *)value)->limit;
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X86_CPU(uc, mycpu)->env.ldt.base = (uint32_t)((uc_x86_mmr *)value)->base;
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X86_CPU(uc, mycpu)->env.ldt.selector = (uint16_t)((uc_x86_mmr *)value)->selector;
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X86_CPU(uc, mycpu)->env.ldt.flags = ((uc_x86_mmr *)value)->flags;
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break;
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case UC_X86_REG_TR:
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X86_CPU(uc, mycpu)->env.tr.limit = ((SegmentCache *)value)->limit;
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X86_CPU(uc, mycpu)->env.tr.base = (uint32_t)((SegmentCache *)value)->base;
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X86_CPU(uc, mycpu)->env.tr.selector = (uint16_t)((SegmentCache *)value)->selector;
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X86_CPU(uc, mycpu)->env.tr.flags = ((SegmentCache *)value)->flags;
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X86_CPU(uc, mycpu)->env.tr.limit = (uint16_t)((uc_x86_mmr *)value)->limit;
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X86_CPU(uc, mycpu)->env.tr.base = (uint32_t)((uc_x86_mmr *)value)->base;
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X86_CPU(uc, mycpu)->env.tr.selector = (uint16_t)((uc_x86_mmr *)value)->selector;
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X86_CPU(uc, mycpu)->env.tr.flags = ((uc_x86_mmr *)value)->flags;
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break;
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}
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break;
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@ -1003,24 +1004,24 @@ int x86_reg_write(struct uc_struct *uc, unsigned int regid, const void *value)
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WRITE_BYTE_L(X86_CPU(uc, mycpu)->env.regs[15], *(uint8_t *)value);
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break;
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case UC_X86_REG_IDTR:
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X86_CPU(uc, mycpu)->env.idt.limit = (uint16_t)((SegmentCache *)value)->limit;
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X86_CPU(uc, mycpu)->env.idt.base = ((SegmentCache *)value)->base;
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X86_CPU(uc, mycpu)->env.idt.limit = (uint16_t)((uc_x86_mmr *)value)->limit;
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X86_CPU(uc, mycpu)->env.idt.base = ((uc_x86_mmr *)value)->base;
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break;
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case UC_X86_REG_GDTR:
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X86_CPU(uc, mycpu)->env.gdt.limit = (uint16_t)((SegmentCache *)value)->limit;
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X86_CPU(uc, mycpu)->env.gdt.base = ((SegmentCache *)value)->base;
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X86_CPU(uc, mycpu)->env.gdt.limit = (uint16_t)((uc_x86_mmr *)value)->limit;
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X86_CPU(uc, mycpu)->env.gdt.base = ((uc_x86_mmr *)value)->base;
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break;
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case UC_X86_REG_LDTR:
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X86_CPU(uc, mycpu)->env.ldt.limit = ((SegmentCache *)value)->limit;
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X86_CPU(uc, mycpu)->env.ldt.base = ((SegmentCache *)value)->base;
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X86_CPU(uc, mycpu)->env.ldt.selector = (uint16_t)((SegmentCache *)value)->selector;
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X86_CPU(uc, mycpu)->env.ldt.flags = ((SegmentCache *)value)->flags;
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X86_CPU(uc, mycpu)->env.ldt.limit = ((uc_x86_mmr *)value)->limit;
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X86_CPU(uc, mycpu)->env.ldt.base = ((uc_x86_mmr *)value)->base;
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X86_CPU(uc, mycpu)->env.ldt.selector = (uint16_t)((uc_x86_mmr *)value)->selector;
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X86_CPU(uc, mycpu)->env.ldt.flags = ((uc_x86_mmr *)value)->flags;
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break;
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case UC_X86_REG_TR:
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X86_CPU(uc, mycpu)->env.tr.limit = ((SegmentCache *)value)->limit;
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X86_CPU(uc, mycpu)->env.tr.base = ((SegmentCache *)value)->base;
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X86_CPU(uc, mycpu)->env.tr.selector = (uint16_t)((SegmentCache *)value)->selector;
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X86_CPU(uc, mycpu)->env.tr.flags = ((SegmentCache *)value)->flags;
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X86_CPU(uc, mycpu)->env.tr.limit = ((uc_x86_mmr *)value)->limit;
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X86_CPU(uc, mycpu)->env.tr.base = ((uc_x86_mmr *)value)->base;
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X86_CPU(uc, mycpu)->env.tr.selector = (uint16_t)((uc_x86_mmr *)value)->selector;
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X86_CPU(uc, mycpu)->env.tr.flags = ((uc_x86_mmr *)value)->flags;
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break;
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}
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break;
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@ -47,10 +47,10 @@ static void test_idt_gdt_i386(/*void **state*/)
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uc_engine *uc;
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uc_err err;
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uint8_t buf[6];
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x86_mmr idt;
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x86_mmr gdt;
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x86_mmr ldt;
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x86_mmr tr;
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uc_x86_mmr idt;
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uc_x86_mmr gdt;
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uc_x86_mmr ldt;
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uc_x86_mmr tr;
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const uint8_t code[] = "\x0f\x01\x0c\x24\x0f\x01\x44\x24\x06"; // sidt [esp]; sgdt [esp+6]
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const uint64_t address = 0x1000000;
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