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arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16

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The fprintf is only there for debugging as the skeleton is added to,
it will be removed once the skeleton is complete.

Backports commit 372087348d561e7f4051d7b32609bda417092ddf from qemu
This commit is contained in:
Alex Bennée 2018-03-08 12:54:44 -05:00 committed by Lioncash
parent 2f850606e9
commit 4a6a41d2c5
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GPG key ID: 4E3C3CC1031BA9C7
6 changed files with 48 additions and 1 deletions
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4
qemu/aarch64.h
View file

@ -3720,10 +3720,14 @@
#define arm_set_cpu_off arm_set_cpu_off_aarch64
#define arm_set_cpu_on arm_set_cpu_on_aarch64
#define gen_a64_set_pc_im gen_a64_set_pc_im_aarch64
#define helper_advsimd_addh helper_advsimd_addh_aarch64
#define helper_advsimd_divh helper_advsimd_divh_aarch64
#define helper_advsimd_maxh helper_advsimd_maxh_aarch64
#define helper_advsimd_maxnumh helper_advsimd_maxnumh_aarch64
#define helper_advsimd_minh helper_advsimd_minh_aarch64
#define helper_advsimd_minnumh helper_advsimd_minnumh_aarch64
#define helper_advsimd_mulh helper_advsimd_mulh_aarch64
#define helper_advsimd_subh helper_advsimd_subh_aarch64
#define helper_crc32_64 helper_crc32_64_aarch64
#define helper_crc32c_64 helper_crc32c_64_aarch64
#define helper_fcvtx_f64_to_f32 helper_fcvtx_f64_to_f32_aarch64

4
qemu/aarch64eb.h
View file

@ -3720,10 +3720,14 @@
#define arm_set_cpu_off arm_set_cpu_off_aarch64eb
#define arm_set_cpu_on arm_set_cpu_on_aarch64eb
#define gen_a64_set_pc_im gen_a64_set_pc_im_aarch64eb
#define helper_advsimd_addh helper_advsimd_addh_aarch64eb
#define helper_advsimd_divh helper_advsimd_divh_aarch64eb
#define helper_advsimd_maxh helper_advsimd_maxh_aarch64eb
#define helper_advsimd_maxnumh helper_advsimd_maxnumh_aarch64eb
#define helper_advsimd_minh helper_advsimd_minh_aarch64eb
#define helper_advsimd_minnumh helper_advsimd_minnumh_aarch64eb
#define helper_advsimd_mulh helper_advsimd_mulh_aarch64eb
#define helper_advsimd_subh helper_advsimd_subh_aarch64eb
#define helper_crc32_64 helper_crc32_64_aarch64eb
#define helper_crc32c_64 helper_crc32c_64_aarch64eb
#define helper_fcvtx_f64_to_f32 helper_fcvtx_f64_to_f32_aarch64eb

4
qemu/header_gen.py
View file

@ -3740,10 +3740,14 @@ aarch64_symbols = (
'arm_set_cpu_off',
'arm_set_cpu_on',
'gen_a64_set_pc_im',
'helper_advsimd_addh',
'helper_advsimd_divh',
'helper_advsimd_maxh',
'helper_advsimd_maxnumh',
'helper_advsimd_minh',
'helper_advsimd_minnumh',
'helper_advsimd_mulh',
'helper_advsimd_subh',
'helper_crc32_64',
'helper_crc32c_64',
'helper_fcvtx_f64_to_f32',

4
qemu/target/arm/helper-a64.c
View file

@ -632,6 +632,10 @@ float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
return float16_ ## name(a, b, fpst); \
}
ADVSIMD_HALFOP(add)
ADVSIMD_HALFOP(sub)
ADVSIMD_HALFOP(mul)
ADVSIMD_HALFOP(div)
ADVSIMD_HALFOP(min)
ADVSIMD_HALFOP(max)
ADVSIMD_HALFOP(minnum)

5
qemu/target/arm/helper-a64.h
View file

@ -48,4 +48,7 @@ DEF_HELPER_FLAGS_3(advsimd_maxh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
DEF_HELPER_FLAGS_3(advsimd_minh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
DEF_HELPER_FLAGS_3(advsimd_maxnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
DEF_HELPER_FLAGS_3(advsimd_minnumh, TCG_CALL_NO_RWG, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_addh, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_subh, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_mulh, f16, f16, f16, ptr)
DEF_HELPER_3(advsimd_divh, f16, f16, f16, ptr)

28
qemu/target/arm/translate-a64.c
View file

@ -10435,6 +10435,34 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn)
read_vec_element_i32(s, tcg_op2, rm, pass, MO_16);
switch (fpopcode) {
case 0x0: /* FMAXNM */
gen_helper_advsimd_maxnumh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x2: /* FADD */
gen_helper_advsimd_addh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x6: /* FMAX */
gen_helper_advsimd_maxh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x8: /* FMINNM */
gen_helper_advsimd_minnumh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0xa: /* FSUB */
gen_helper_advsimd_subh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0xe: /* FMIN */
gen_helper_advsimd_minh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x13: /* FMUL */
gen_helper_advsimd_mulh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x17: /* FDIV */
gen_helper_advsimd_divh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x1a: /* FABD */
gen_helper_advsimd_subh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
tcg_gen_andi_i32(tcg_ctx, tcg_res, tcg_res, 0x7fff);
break;
default:
fprintf(stderr, "%s: insn %#04x, fpop %#2x @ %#" PRIx64 "\n",
__func__, insn, fpopcode, s->pc);