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tcg: Move some opcode generation functions out of line

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Some of these functions are really quite large.  We have a number of
things that ought to be circularly dependent, but we duplicated code
to break that chain for the inlines.

This saved 25% of the code size of one of the translators I examined.
This commit is contained in:
Richard Henderson 2018-02-08 15:19:28 -05:00 committed by Lioncash
parent cb7b19ad26
commit 500c546444
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
19 changed files with 3221 additions and 2279 deletions
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2
qemu/Makefile.target
View file

@ -41,7 +41,7 @@ all: $(PROGS)
#########################################################
# cpu emulator library
obj-y = exec.o translate-all.o cpu-exec.o
obj-y += tcg/tcg.o tcg/optimize.o
obj-y += tcg/tcg.o tcg/tcg-op.o tcg/optimize.o
obj-y += fpu/softfloat.o
obj-y += target-$(TARGET_BASE_ARCH)/

63
qemu/aarch64.h
View file

@ -2690,11 +2690,13 @@
#define tcg_func_start tcg_func_start_aarch64
#define tcg_gen_abs_i32 tcg_gen_abs_i32_aarch64
#define tcg_gen_add2_i32 tcg_gen_add2_i32_aarch64
#define tcg_gen_add2_i64 tcg_gen_add2_i64_aarch64
#define tcg_gen_add_i32 tcg_gen_add_i32_aarch64
#define tcg_gen_add_i64 tcg_gen_add_i64_aarch64
#define tcg_gen_addi_i32 tcg_gen_addi_i32_aarch64
#define tcg_gen_addi_i64 tcg_gen_addi_i64_aarch64
#define tcg_gen_andc_i32 tcg_gen_andc_i32_aarch64
#define tcg_gen_andc_i64 tcg_gen_andc_i64_aarch64
#define tcg_gen_and_i32 tcg_gen_and_i32_aarch64
#define tcg_gen_and_i64 tcg_gen_and_i64_aarch64
#define tcg_gen_andi_i32 tcg_gen_andi_i32_aarch64
@ -2703,8 +2705,12 @@
#define tcg_gen_brcond_i32 tcg_gen_brcond_i32_aarch64
#define tcg_gen_brcond_i64 tcg_gen_brcond_i64_aarch64
#define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_aarch64
#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_aarch64
#define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_aarch64
#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_aarch64
#define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_aarch64
#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_aarch64
#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_aarch64
#define tcg_gen_callN tcg_gen_callN_aarch64
#define tcg_gen_code tcg_gen_code_aarch64
#define tcg_gen_code_common tcg_gen_code_common_aarch64
@ -2712,16 +2718,36 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_aarch64
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_aarch64
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_aarch64
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_aarch64
#define tcg_gen_discard_i64 tcg_gen_discard_i64_aarch64
#define tcg_gen_div_i32 tcg_gen_div_i32_aarch64
#define tcg_gen_div_i64 tcg_gen_div_i64_aarch64
#define tcg_gen_divu_i32 tcg_gen_divu_i32_aarch64
#define tcg_gen_divu_i64 tcg_gen_divu_i64_aarch64
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_aarch64
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_aarch64
#define tcg_gen_exit_tb tcg_gen_exit_tb_aarch64
#define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_aarch64
#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_aarch64
#define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_aarch64
#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_aarch64
#define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_aarch64
#define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_aarch64
#define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_aarch64
#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_aarch64
#define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_aarch64
#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_aarch64
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_aarch64
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_aarch64
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_aarch64
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_aarch64
#define tcg_gen_goto_tb tcg_gen_goto_tb_aarch64
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_aarch64
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_aarch64
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_aarch64
#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_aarch64
#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_aarch64
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_aarch64
#define tcg_gen_ld_i32 tcg_gen_ld_i32_aarch64
#define tcg_gen_ld_i64 tcg_gen_ld_i64_aarch64
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_aarch64
@ -2733,12 +2759,28 @@
#define tcg_gen_movi_i32 tcg_gen_movi_i32_aarch64
#define tcg_gen_movi_i64 tcg_gen_movi_i64_aarch64
#define tcg_gen_mul_i32 tcg_gen_mul_i32_aarch64
#define tcg_gen_mul_i64 tcg_gen_mul_i64_aarch64
#define tcg_gen_muli_i32 tcg_gen_muli_i32_aarch64
#define tcg_gen_muli_i64 tcg_gen_muli_i64_aarch64
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_aarch64
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_aarch64
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_aarch64
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_aarch64
#define tcg_gen_nand_i32 tcg_gen_nand_i32_aarch64
#define tcg_gen_nand_i64 tcg_gen_nand_i64_aarch64
#define tcg_gen_neg_i32 tcg_gen_neg_i32_aarch64
#define tcg_gen_neg_i64 tcg_gen_neg_i64_aarch64
#define tcg_gen_nor_i32 tcg_gen_nor_i32_aarch64
#define tcg_gen_nor_i64 tcg_gen_nor_i64_aarch64
#define tcg_gen_not_i32 tcg_gen_not_i32_aarch64
#define tcg_gen_not_i64 tcg_gen_not_i64_aarch64
#define tcg_gen_op0 tcg_gen_op0_aarch64
#define tcg_gen_op1 tcg_gen_op1_aarch64
#define tcg_gen_op2 tcg_gen_op2_aarch64
#define tcg_gen_op3 tcg_gen_op3_aarch64
#define tcg_gen_op4 tcg_gen_op4_aarch64
#define tcg_gen_op5 tcg_gen_op5_aarch64
#define tcg_gen_op6 tcg_gen_op6_aarch64
#define tcg_gen_op1i tcg_gen_op1i_aarch64
#define tcg_gen_op2_i32 tcg_gen_op2_i32_aarch64
#define tcg_gen_op2_i64 tcg_gen_op2_i64_aarch64
@ -2755,20 +2797,35 @@
#define tcg_gen_op6i_i32 tcg_gen_op6i_i32_aarch64
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_aarch64
#define tcg_gen_orc_i32 tcg_gen_orc_i32_aarch64
#define tcg_gen_orc_i64 tcg_gen_orc_i64_aarch64
#define tcg_gen_or_i32 tcg_gen_or_i32_aarch64
#define tcg_gen_or_i64 tcg_gen_or_i64_aarch64
#define tcg_gen_ori_i32 tcg_gen_ori_i32_aarch64
#define tcg_gen_ori_i64 tcg_gen_ori_i64_aarch64
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_aarch64
#define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_aarch64
#define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_aarch64
#define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_aarch64
#define tcg_gen_rem_i32 tcg_gen_rem_i32_aarch64
#define tcg_gen_rem_i64 tcg_gen_rem_i64_aarch64
#define tcg_gen_remu_i32 tcg_gen_remu_i32_aarch64
#define tcg_gen_remu_i64 tcg_gen_remu_i64_aarch64
#define tcg_gen_rotl_i32 tcg_gen_rotl_i32_aarch64
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_aarch64
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_aarch64
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_aarch64
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_aarch64
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_aarch64
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_aarch64
#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_aarch64
#define tcg_gen_sar_i32 tcg_gen_sar_i32_aarch64
#define tcg_gen_sar_i64 tcg_gen_sar_i64_aarch64
#define tcg_gen_sari_i32 tcg_gen_sari_i32_aarch64
#define tcg_gen_sari_i64 tcg_gen_sari_i64_aarch64
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_aarch64
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_aarch64
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_aarch64
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_aarch64
#define tcg_gen_shl_i32 tcg_gen_shl_i32_aarch64
#define tcg_gen_shl_i64 tcg_gen_shl_i64_aarch64
#define tcg_gen_shli_i32 tcg_gen_shli_i32_aarch64
@ -2780,14 +2837,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_aarch64
#define tcg_gen_st_i32 tcg_gen_st_i32_aarch64
#define tcg_gen_st_i64 tcg_gen_st_i64_aarch64
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_aarch64
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_aarch64
#define tcg_gen_sub_i32 tcg_gen_sub_i32_aarch64
#define tcg_gen_sub_i64 tcg_gen_sub_i64_aarch64
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_aarch64
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_aarch64
#define tcg_gen_subi_i32 tcg_gen_subi_i32_aarch64
#define tcg_gen_subi_i64 tcg_gen_subi_i64_aarch64
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_aarch64
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_aarch64
#define tcg_gen_xor_i32 tcg_gen_xor_i32_aarch64
#define tcg_gen_xor_i64 tcg_gen_xor_i64_aarch64
#define tcg_gen_xori_i32 tcg_gen_xori_i32_aarch64
#define tcg_gen_xori_i64 tcg_gen_xori_i64_aarch64
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_aarch64
#define tcg_get_arg_str_i64 tcg_get_arg_str_i64_aarch64
#define tcg_get_arg_str_idx tcg_get_arg_str_idx_aarch64

63
qemu/aarch64eb.h
View file

@ -2690,11 +2690,13 @@
#define tcg_func_start tcg_func_start_aarch64eb
#define tcg_gen_abs_i32 tcg_gen_abs_i32_aarch64eb
#define tcg_gen_add2_i32 tcg_gen_add2_i32_aarch64eb
#define tcg_gen_add2_i64 tcg_gen_add2_i64_aarch64eb
#define tcg_gen_add_i32 tcg_gen_add_i32_aarch64eb
#define tcg_gen_add_i64 tcg_gen_add_i64_aarch64eb
#define tcg_gen_addi_i32 tcg_gen_addi_i32_aarch64eb
#define tcg_gen_addi_i64 tcg_gen_addi_i64_aarch64eb
#define tcg_gen_andc_i32 tcg_gen_andc_i32_aarch64eb
#define tcg_gen_andc_i64 tcg_gen_andc_i64_aarch64eb
#define tcg_gen_and_i32 tcg_gen_and_i32_aarch64eb
#define tcg_gen_and_i64 tcg_gen_and_i64_aarch64eb
#define tcg_gen_andi_i32 tcg_gen_andi_i32_aarch64eb
@ -2703,8 +2705,12 @@
#define tcg_gen_brcond_i32 tcg_gen_brcond_i32_aarch64eb
#define tcg_gen_brcond_i64 tcg_gen_brcond_i64_aarch64eb
#define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_aarch64eb
#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_aarch64eb
#define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_aarch64eb
#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_aarch64eb
#define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_aarch64eb
#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_aarch64eb
#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_aarch64eb
#define tcg_gen_callN tcg_gen_callN_aarch64eb
#define tcg_gen_code tcg_gen_code_aarch64eb
#define tcg_gen_code_common tcg_gen_code_common_aarch64eb
@ -2712,16 +2718,36 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_aarch64eb
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_aarch64eb
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_aarch64eb
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_aarch64eb
#define tcg_gen_discard_i64 tcg_gen_discard_i64_aarch64eb
#define tcg_gen_div_i32 tcg_gen_div_i32_aarch64eb
#define tcg_gen_div_i64 tcg_gen_div_i64_aarch64eb
#define tcg_gen_divu_i32 tcg_gen_divu_i32_aarch64eb
#define tcg_gen_divu_i64 tcg_gen_divu_i64_aarch64eb
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_aarch64eb
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_aarch64eb
#define tcg_gen_exit_tb tcg_gen_exit_tb_aarch64eb
#define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_aarch64eb
#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_aarch64eb
#define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_aarch64eb
#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_aarch64eb
#define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_aarch64eb
#define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_aarch64eb
#define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_aarch64eb
#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_aarch64eb
#define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_aarch64eb
#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_aarch64eb
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_aarch64eb
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_aarch64eb
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_aarch64eb
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_aarch64eb
#define tcg_gen_goto_tb tcg_gen_goto_tb_aarch64eb
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_aarch64eb
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_aarch64eb
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_aarch64eb
#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_aarch64eb
#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_aarch64eb
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_aarch64eb
#define tcg_gen_ld_i32 tcg_gen_ld_i32_aarch64eb
#define tcg_gen_ld_i64 tcg_gen_ld_i64_aarch64eb
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_aarch64eb
@ -2733,12 +2759,28 @@
#define tcg_gen_movi_i32 tcg_gen_movi_i32_aarch64eb
#define tcg_gen_movi_i64 tcg_gen_movi_i64_aarch64eb
#define tcg_gen_mul_i32 tcg_gen_mul_i32_aarch64eb
#define tcg_gen_mul_i64 tcg_gen_mul_i64_aarch64eb
#define tcg_gen_muli_i32 tcg_gen_muli_i32_aarch64eb
#define tcg_gen_muli_i64 tcg_gen_muli_i64_aarch64eb
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_aarch64eb
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_aarch64eb
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_aarch64eb
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_aarch64eb
#define tcg_gen_nand_i32 tcg_gen_nand_i32_aarch64eb
#define tcg_gen_nand_i64 tcg_gen_nand_i64_aarch64eb
#define tcg_gen_neg_i32 tcg_gen_neg_i32_aarch64eb
#define tcg_gen_neg_i64 tcg_gen_neg_i64_aarch64eb
#define tcg_gen_nor_i32 tcg_gen_nor_i32_aarch64eb
#define tcg_gen_nor_i64 tcg_gen_nor_i64_aarch64eb
#define tcg_gen_not_i32 tcg_gen_not_i32_aarch64eb
#define tcg_gen_not_i64 tcg_gen_not_i64_aarch64eb
#define tcg_gen_op0 tcg_gen_op0_aarch64eb
#define tcg_gen_op1 tcg_gen_op1_aarch64eb
#define tcg_gen_op2 tcg_gen_op2_aarch64eb
#define tcg_gen_op3 tcg_gen_op3_aarch64eb
#define tcg_gen_op4 tcg_gen_op4_aarch64eb
#define tcg_gen_op5 tcg_gen_op5_aarch64eb
#define tcg_gen_op6 tcg_gen_op6_aarch64eb
#define tcg_gen_op1i tcg_gen_op1i_aarch64eb
#define tcg_gen_op2_i32 tcg_gen_op2_i32_aarch64eb
#define tcg_gen_op2_i64 tcg_gen_op2_i64_aarch64eb
@ -2755,20 +2797,35 @@
#define tcg_gen_op6i_i32 tcg_gen_op6i_i32_aarch64eb
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_aarch64eb
#define tcg_gen_orc_i32 tcg_gen_orc_i32_aarch64eb
#define tcg_gen_orc_i64 tcg_gen_orc_i64_aarch64eb
#define tcg_gen_or_i32 tcg_gen_or_i32_aarch64eb
#define tcg_gen_or_i64 tcg_gen_or_i64_aarch64eb
#define tcg_gen_ori_i32 tcg_gen_ori_i32_aarch64eb
#define tcg_gen_ori_i64 tcg_gen_ori_i64_aarch64eb
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_aarch64eb
#define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_aarch64eb
#define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_aarch64eb
#define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_aarch64eb
#define tcg_gen_rem_i32 tcg_gen_rem_i32_aarch64eb
#define tcg_gen_rem_i64 tcg_gen_rem_i64_aarch64eb
#define tcg_gen_remu_i32 tcg_gen_remu_i32_aarch64eb
#define tcg_gen_remu_i64 tcg_gen_remu_i64_aarch64eb
#define tcg_gen_rotl_i32 tcg_gen_rotl_i32_aarch64eb
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_aarch64eb
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_aarch64eb
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_aarch64eb
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_aarch64eb
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_aarch64eb
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_aarch64eb
#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_aarch64eb
#define tcg_gen_sar_i32 tcg_gen_sar_i32_aarch64eb
#define tcg_gen_sar_i64 tcg_gen_sar_i64_aarch64eb
#define tcg_gen_sari_i32 tcg_gen_sari_i32_aarch64eb
#define tcg_gen_sari_i64 tcg_gen_sari_i64_aarch64eb
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_aarch64eb
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_aarch64eb
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_aarch64eb
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_aarch64eb
#define tcg_gen_shl_i32 tcg_gen_shl_i32_aarch64eb
#define tcg_gen_shl_i64 tcg_gen_shl_i64_aarch64eb
#define tcg_gen_shli_i32 tcg_gen_shli_i32_aarch64eb
@ -2780,14 +2837,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_aarch64eb
#define tcg_gen_st_i32 tcg_gen_st_i32_aarch64eb
#define tcg_gen_st_i64 tcg_gen_st_i64_aarch64eb
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_aarch64eb
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_aarch64eb
#define tcg_gen_sub_i32 tcg_gen_sub_i32_aarch64eb
#define tcg_gen_sub_i64 tcg_gen_sub_i64_aarch64eb
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_aarch64eb
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_aarch64eb
#define tcg_gen_subi_i32 tcg_gen_subi_i32_aarch64eb
#define tcg_gen_subi_i64 tcg_gen_subi_i64_aarch64eb
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_aarch64eb
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_aarch64eb
#define tcg_gen_xor_i32 tcg_gen_xor_i32_aarch64eb
#define tcg_gen_xor_i64 tcg_gen_xor_i64_aarch64eb
#define tcg_gen_xori_i32 tcg_gen_xori_i32_aarch64eb
#define tcg_gen_xori_i64 tcg_gen_xori_i64_aarch64eb
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_aarch64eb
#define tcg_get_arg_str_i64 tcg_get_arg_str_i64_aarch64eb
#define tcg_get_arg_str_idx tcg_get_arg_str_idx_aarch64eb

63
qemu/arm.h
View file

@ -2690,11 +2690,13 @@
#define tcg_func_start tcg_func_start_arm
#define tcg_gen_abs_i32 tcg_gen_abs_i32_arm
#define tcg_gen_add2_i32 tcg_gen_add2_i32_arm
#define tcg_gen_add2_i64 tcg_gen_add2_i64_arm
#define tcg_gen_add_i32 tcg_gen_add_i32_arm
#define tcg_gen_add_i64 tcg_gen_add_i64_arm
#define tcg_gen_addi_i32 tcg_gen_addi_i32_arm
#define tcg_gen_addi_i64 tcg_gen_addi_i64_arm
#define tcg_gen_andc_i32 tcg_gen_andc_i32_arm
#define tcg_gen_andc_i64 tcg_gen_andc_i64_arm
#define tcg_gen_and_i32 tcg_gen_and_i32_arm
#define tcg_gen_and_i64 tcg_gen_and_i64_arm
#define tcg_gen_andi_i32 tcg_gen_andi_i32_arm
@ -2703,8 +2705,12 @@
#define tcg_gen_brcond_i32 tcg_gen_brcond_i32_arm
#define tcg_gen_brcond_i64 tcg_gen_brcond_i64_arm
#define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_arm
#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_arm
#define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_arm
#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_arm
#define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_arm
#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_arm
#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_arm
#define tcg_gen_callN tcg_gen_callN_arm
#define tcg_gen_code tcg_gen_code_arm
#define tcg_gen_code_common tcg_gen_code_common_arm
@ -2712,16 +2718,36 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_arm
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_arm
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_arm
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_arm
#define tcg_gen_discard_i64 tcg_gen_discard_i64_arm
#define tcg_gen_div_i32 tcg_gen_div_i32_arm
#define tcg_gen_div_i64 tcg_gen_div_i64_arm
#define tcg_gen_divu_i32 tcg_gen_divu_i32_arm
#define tcg_gen_divu_i64 tcg_gen_divu_i64_arm
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_arm
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_arm
#define tcg_gen_exit_tb tcg_gen_exit_tb_arm
#define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_arm
#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_arm
#define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_arm
#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_arm
#define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_arm
#define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_arm
#define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_arm
#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_arm
#define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_arm
#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_arm
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_arm
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_arm
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_arm
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_arm
#define tcg_gen_goto_tb tcg_gen_goto_tb_arm
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_arm
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_arm
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_arm
#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_arm
#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_arm
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_arm
#define tcg_gen_ld_i32 tcg_gen_ld_i32_arm
#define tcg_gen_ld_i64 tcg_gen_ld_i64_arm
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_arm
@ -2733,12 +2759,28 @@
#define tcg_gen_movi_i32 tcg_gen_movi_i32_arm
#define tcg_gen_movi_i64 tcg_gen_movi_i64_arm
#define tcg_gen_mul_i32 tcg_gen_mul_i32_arm
#define tcg_gen_mul_i64 tcg_gen_mul_i64_arm
#define tcg_gen_muli_i32 tcg_gen_muli_i32_arm
#define tcg_gen_muli_i64 tcg_gen_muli_i64_arm
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_arm
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_arm
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_arm
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_arm
#define tcg_gen_nand_i32 tcg_gen_nand_i32_arm
#define tcg_gen_nand_i64 tcg_gen_nand_i64_arm
#define tcg_gen_neg_i32 tcg_gen_neg_i32_arm
#define tcg_gen_neg_i64 tcg_gen_neg_i64_arm
#define tcg_gen_nor_i32 tcg_gen_nor_i32_arm
#define tcg_gen_nor_i64 tcg_gen_nor_i64_arm
#define tcg_gen_not_i32 tcg_gen_not_i32_arm
#define tcg_gen_not_i64 tcg_gen_not_i64_arm
#define tcg_gen_op0 tcg_gen_op0_arm
#define tcg_gen_op1 tcg_gen_op1_arm
#define tcg_gen_op2 tcg_gen_op2_arm
#define tcg_gen_op3 tcg_gen_op3_arm
#define tcg_gen_op4 tcg_gen_op4_arm
#define tcg_gen_op5 tcg_gen_op5_arm
#define tcg_gen_op6 tcg_gen_op6_arm
#define tcg_gen_op1i tcg_gen_op1i_arm
#define tcg_gen_op2_i32 tcg_gen_op2_i32_arm
#define tcg_gen_op2_i64 tcg_gen_op2_i64_arm
@ -2755,20 +2797,35 @@
#define tcg_gen_op6i_i32 tcg_gen_op6i_i32_arm
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_arm
#define tcg_gen_orc_i32 tcg_gen_orc_i32_arm
#define tcg_gen_orc_i64 tcg_gen_orc_i64_arm
#define tcg_gen_or_i32 tcg_gen_or_i32_arm
#define tcg_gen_or_i64 tcg_gen_or_i64_arm
#define tcg_gen_ori_i32 tcg_gen_ori_i32_arm
#define tcg_gen_ori_i64 tcg_gen_ori_i64_arm
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_arm
#define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_arm
#define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_arm
#define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_arm
#define tcg_gen_rem_i32 tcg_gen_rem_i32_arm
#define tcg_gen_rem_i64 tcg_gen_rem_i64_arm
#define tcg_gen_remu_i32 tcg_gen_remu_i32_arm
#define tcg_gen_remu_i64 tcg_gen_remu_i64_arm
#define tcg_gen_rotl_i32 tcg_gen_rotl_i32_arm
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_arm
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_arm
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_arm
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_arm
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_arm
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_arm
#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_arm
#define tcg_gen_sar_i32 tcg_gen_sar_i32_arm
#define tcg_gen_sar_i64 tcg_gen_sar_i64_arm
#define tcg_gen_sari_i32 tcg_gen_sari_i32_arm
#define tcg_gen_sari_i64 tcg_gen_sari_i64_arm
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_arm
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_arm
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_arm
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_arm
#define tcg_gen_shl_i32 tcg_gen_shl_i32_arm
#define tcg_gen_shl_i64 tcg_gen_shl_i64_arm
#define tcg_gen_shli_i32 tcg_gen_shli_i32_arm
@ -2780,14 +2837,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_arm
#define tcg_gen_st_i32 tcg_gen_st_i32_arm
#define tcg_gen_st_i64 tcg_gen_st_i64_arm
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_arm
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_arm
#define tcg_gen_sub_i32 tcg_gen_sub_i32_arm
#define tcg_gen_sub_i64 tcg_gen_sub_i64_arm
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_arm
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_arm
#define tcg_gen_subi_i32 tcg_gen_subi_i32_arm
#define tcg_gen_subi_i64 tcg_gen_subi_i64_arm
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_arm
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_arm
#define tcg_gen_xor_i32 tcg_gen_xor_i32_arm
#define tcg_gen_xor_i64 tcg_gen_xor_i64_arm
#define tcg_gen_xori_i32 tcg_gen_xori_i32_arm
#define tcg_gen_xori_i64 tcg_gen_xori_i64_arm
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_arm
#define tcg_get_arg_str_i64 tcg_get_arg_str_i64_arm
#define tcg_get_arg_str_idx tcg_get_arg_str_idx_arm

63
qemu/armeb.h
View file

@ -2690,11 +2690,13 @@
#define tcg_func_start tcg_func_start_armeb
#define tcg_gen_abs_i32 tcg_gen_abs_i32_armeb
#define tcg_gen_add2_i32 tcg_gen_add2_i32_armeb
#define tcg_gen_add2_i64 tcg_gen_add2_i64_armeb
#define tcg_gen_add_i32 tcg_gen_add_i32_armeb
#define tcg_gen_add_i64 tcg_gen_add_i64_armeb
#define tcg_gen_addi_i32 tcg_gen_addi_i32_armeb
#define tcg_gen_addi_i64 tcg_gen_addi_i64_armeb
#define tcg_gen_andc_i32 tcg_gen_andc_i32_armeb
#define tcg_gen_andc_i64 tcg_gen_andc_i64_armeb
#define tcg_gen_and_i32 tcg_gen_and_i32_armeb
#define tcg_gen_and_i64 tcg_gen_and_i64_armeb
#define tcg_gen_andi_i32 tcg_gen_andi_i32_armeb
@ -2703,8 +2705,12 @@
#define tcg_gen_brcond_i32 tcg_gen_brcond_i32_armeb
#define tcg_gen_brcond_i64 tcg_gen_brcond_i64_armeb
#define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_armeb
#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_armeb
#define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_armeb
#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_armeb
#define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_armeb
#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_armeb
#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_armeb
#define tcg_gen_callN tcg_gen_callN_armeb
#define tcg_gen_code tcg_gen_code_armeb
#define tcg_gen_code_common tcg_gen_code_common_armeb
@ -2712,16 +2718,36 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_armeb
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_armeb
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_armeb
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_armeb
#define tcg_gen_discard_i64 tcg_gen_discard_i64_armeb
#define tcg_gen_div_i32 tcg_gen_div_i32_armeb
#define tcg_gen_div_i64 tcg_gen_div_i64_armeb
#define tcg_gen_divu_i32 tcg_gen_divu_i32_armeb
#define tcg_gen_divu_i64 tcg_gen_divu_i64_armeb
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_armeb
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_armeb
#define tcg_gen_exit_tb tcg_gen_exit_tb_armeb
#define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_armeb
#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_armeb
#define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_armeb
#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_armeb
#define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_armeb
#define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_armeb
#define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_armeb
#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_armeb
#define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_armeb
#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_armeb
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_armeb
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_armeb
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_armeb
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_armeb
#define tcg_gen_goto_tb tcg_gen_goto_tb_armeb
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_armeb
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_armeb
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_armeb
#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_armeb
#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_armeb
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_armeb
#define tcg_gen_ld_i32 tcg_gen_ld_i32_armeb
#define tcg_gen_ld_i64 tcg_gen_ld_i64_armeb
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_armeb
@ -2733,12 +2759,28 @@
#define tcg_gen_movi_i32 tcg_gen_movi_i32_armeb
#define tcg_gen_movi_i64 tcg_gen_movi_i64_armeb
#define tcg_gen_mul_i32 tcg_gen_mul_i32_armeb
#define tcg_gen_mul_i64 tcg_gen_mul_i64_armeb
#define tcg_gen_muli_i32 tcg_gen_muli_i32_armeb
#define tcg_gen_muli_i64 tcg_gen_muli_i64_armeb
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_armeb
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_armeb
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_armeb
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_armeb
#define tcg_gen_nand_i32 tcg_gen_nand_i32_armeb
#define tcg_gen_nand_i64 tcg_gen_nand_i64_armeb
#define tcg_gen_neg_i32 tcg_gen_neg_i32_armeb
#define tcg_gen_neg_i64 tcg_gen_neg_i64_armeb
#define tcg_gen_nor_i32 tcg_gen_nor_i32_armeb
#define tcg_gen_nor_i64 tcg_gen_nor_i64_armeb
#define tcg_gen_not_i32 tcg_gen_not_i32_armeb
#define tcg_gen_not_i64 tcg_gen_not_i64_armeb
#define tcg_gen_op0 tcg_gen_op0_armeb
#define tcg_gen_op1 tcg_gen_op1_armeb
#define tcg_gen_op2 tcg_gen_op2_armeb
#define tcg_gen_op3 tcg_gen_op3_armeb
#define tcg_gen_op4 tcg_gen_op4_armeb
#define tcg_gen_op5 tcg_gen_op5_armeb
#define tcg_gen_op6 tcg_gen_op6_armeb
#define tcg_gen_op1i tcg_gen_op1i_armeb
#define tcg_gen_op2_i32 tcg_gen_op2_i32_armeb
#define tcg_gen_op2_i64 tcg_gen_op2_i64_armeb
@ -2755,20 +2797,35 @@
#define tcg_gen_op6i_i32 tcg_gen_op6i_i32_armeb
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_armeb
#define tcg_gen_orc_i32 tcg_gen_orc_i32_armeb
#define tcg_gen_orc_i64 tcg_gen_orc_i64_armeb
#define tcg_gen_or_i32 tcg_gen_or_i32_armeb
#define tcg_gen_or_i64 tcg_gen_or_i64_armeb
#define tcg_gen_ori_i32 tcg_gen_ori_i32_armeb
#define tcg_gen_ori_i64 tcg_gen_ori_i64_armeb
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_armeb
#define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_armeb
#define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_armeb
#define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_armeb
#define tcg_gen_rem_i32 tcg_gen_rem_i32_armeb
#define tcg_gen_rem_i64 tcg_gen_rem_i64_armeb
#define tcg_gen_remu_i32 tcg_gen_remu_i32_armeb
#define tcg_gen_remu_i64 tcg_gen_remu_i64_armeb
#define tcg_gen_rotl_i32 tcg_gen_rotl_i32_armeb
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_armeb
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_armeb
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_armeb
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_armeb
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_armeb
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_armeb
#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_armeb
#define tcg_gen_sar_i32 tcg_gen_sar_i32_armeb
#define tcg_gen_sar_i64 tcg_gen_sar_i64_armeb
#define tcg_gen_sari_i32 tcg_gen_sari_i32_armeb
#define tcg_gen_sari_i64 tcg_gen_sari_i64_armeb
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_armeb
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_armeb
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_armeb
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_armeb
#define tcg_gen_shl_i32 tcg_gen_shl_i32_armeb
#define tcg_gen_shl_i64 tcg_gen_shl_i64_armeb
#define tcg_gen_shli_i32 tcg_gen_shli_i32_armeb
@ -2780,14 +2837,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_armeb
#define tcg_gen_st_i32 tcg_gen_st_i32_armeb
#define tcg_gen_st_i64 tcg_gen_st_i64_armeb
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_armeb
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_armeb
#define tcg_gen_sub_i32 tcg_gen_sub_i32_armeb
#define tcg_gen_sub_i64 tcg_gen_sub_i64_armeb
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_armeb
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_armeb
#define tcg_gen_subi_i32 tcg_gen_subi_i32_armeb
#define tcg_gen_subi_i64 tcg_gen_subi_i64_armeb
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_armeb
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_armeb
#define tcg_gen_xor_i32 tcg_gen_xor_i32_armeb
#define tcg_gen_xor_i64 tcg_gen_xor_i64_armeb
#define tcg_gen_xori_i32 tcg_gen_xori_i32_armeb
#define tcg_gen_xori_i64 tcg_gen_xori_i64_armeb
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_armeb
#define tcg_get_arg_str_i64 tcg_get_arg_str_i64_armeb
#define tcg_get_arg_str_idx tcg_get_arg_str_idx_armeb

63
qemu/header_gen.py
View file

@ -2696,11 +2696,13 @@ symbols = (
'tcg_func_start',
'tcg_gen_abs_i32',
'tcg_gen_add2_i32',
'tcg_gen_add2_i64',
'tcg_gen_add_i32',
'tcg_gen_add_i64',
'tcg_gen_addi_i32',
'tcg_gen_addi_i64',
'tcg_gen_andc_i32',
'tcg_gen_andc_i64',
'tcg_gen_and_i32',
'tcg_gen_and_i64',
'tcg_gen_andi_i32',
@ -2709,8 +2711,12 @@ symbols = (
'tcg_gen_brcond_i32',
'tcg_gen_brcond_i64',
'tcg_gen_brcondi_i32',
'tcg_gen_brcondi_i64',
'tcg_gen_bswap16_i32',
'tcg_gen_bswap16_i64',
'tcg_gen_bswap32_i32',
'tcg_gen_bswap32_i64',
'tcg_gen_bswap64_i64',
'tcg_gen_callN',
'tcg_gen_code',
'tcg_gen_code_common',
@ -2718,16 +2724,36 @@ symbols = (
'tcg_gen_concat_i32_i64',
'tcg_gen_debug_insn_start',
'tcg_gen_deposit_i32',
'tcg_gen_deposit_i64',
'tcg_gen_discard_i64',
'tcg_gen_div_i32',
'tcg_gen_div_i64',
'tcg_gen_divu_i32',
'tcg_gen_divu_i64',
'tcg_gen_eqv_i32',
'tcg_gen_eqv_i64',
'tcg_gen_exit_tb',
'tcg_gen_ext16s_i32',
'tcg_gen_ext16s_i64',
'tcg_gen_ext16u_i32',
'tcg_gen_ext16u_i64',
'tcg_gen_ext32s_i64',
'tcg_gen_ext32u_i64',
'tcg_gen_ext8s_i32',
'tcg_gen_ext8s_i64',
'tcg_gen_ext8u_i32',
'tcg_gen_ext8u_i64',
'tcg_gen_ext_i32_i64',
'tcg_gen_extr32_i64',
'tcg_gen_extr_i64_i32',
'tcg_gen_extu_i32_i64',
'tcg_gen_goto_tb',
'tcg_gen_ld16s_i64',
'tcg_gen_ld16u_i64',
'tcg_gen_ld32s_i64',
'tcg_gen_ld32u_i64',
'tcg_gen_ld8s_i64',
'tcg_gen_ld8u_i64',
'tcg_gen_ld_i32',
'tcg_gen_ld_i64',
'tcg_gen_ldst_op_i32',
@ -2739,12 +2765,28 @@ symbols = (
'tcg_gen_movi_i32',
'tcg_gen_movi_i64',
'tcg_gen_mul_i32',
'tcg_gen_mul_i64',
'tcg_gen_muli_i32',
'tcg_gen_muli_i64',
'tcg_gen_muls2_i32',
'tcg_gen_muls2_i64',
'tcg_gen_mulu2_i32',
'tcg_gen_mulu2_i64',
'tcg_gen_nand_i32',
'tcg_gen_nand_i64',
'tcg_gen_neg_i32',
'tcg_gen_neg_i64',
'tcg_gen_nor_i32',
'tcg_gen_nor_i64',
'tcg_gen_not_i32',
'tcg_gen_not_i64',
'tcg_gen_op0',
'tcg_gen_op1',
'tcg_gen_op2',
'tcg_gen_op3',
'tcg_gen_op4',
'tcg_gen_op5',
'tcg_gen_op6',
'tcg_gen_op1i',
'tcg_gen_op2_i32',
'tcg_gen_op2_i64',
@ -2761,20 +2803,35 @@ symbols = (
'tcg_gen_op6i_i32',
'tcg_gen_op6i_i64',
'tcg_gen_orc_i32',
'tcg_gen_orc_i64',
'tcg_gen_or_i32',
'tcg_gen_or_i64',
'tcg_gen_ori_i32',
'tcg_gen_ori_i64',
'tcg_gen_qemu_ld_i32',
'tcg_gen_qemu_ld_i64',
'tcg_gen_qemu_st_i32',
'tcg_gen_qemu_st_i64',
'tcg_gen_rem_i32',
'tcg_gen_rem_i64',
'tcg_gen_remu_i32',
'tcg_gen_remu_i64',
'tcg_gen_rotl_i32',
'tcg_gen_rotl_i64',
'tcg_gen_rotli_i32',
'tcg_gen_rotli_i64',
'tcg_gen_rotr_i32',
'tcg_gen_rotr_i64',
'tcg_gen_rotri_i32',
'tcg_gen_rotri_i64',
'tcg_gen_sar_i32',
'tcg_gen_sar_i64',
'tcg_gen_sari_i32',
'tcg_gen_sari_i64',
'tcg_gen_setcond_i32',
'tcg_gen_setcond_i64',
'tcg_gen_setcondi_i32',
'tcg_gen_setcondi_i64',
'tcg_gen_shl_i32',
'tcg_gen_shl_i64',
'tcg_gen_shli_i32',
@ -2786,14 +2843,20 @@ symbols = (
'tcg_gen_shri_i64',
'tcg_gen_st_i32',
'tcg_gen_st_i64',
'tcg_gen_sub2_i32',
'tcg_gen_sub2_i64',
'tcg_gen_sub_i32',
'tcg_gen_sub_i64',
'tcg_gen_subfi_i32',
'tcg_gen_subfi_i64',
'tcg_gen_subi_i32',
'tcg_gen_subi_i64',
'tcg_gen_trunc_i64_i32',
'tcg_gen_trunc_shr_i64_i32',
'tcg_gen_xor_i32',
'tcg_gen_xor_i64',
'tcg_gen_xori_i32',
'tcg_gen_xori_i64',
'tcg_get_arg_str_i32',
'tcg_get_arg_str_i64',
'tcg_get_arg_str_idx',

63
qemu/m68k.h
View file

@ -2690,11 +2690,13 @@
#define tcg_func_start tcg_func_start_m68k
#define tcg_gen_abs_i32 tcg_gen_abs_i32_m68k
#define tcg_gen_add2_i32 tcg_gen_add2_i32_m68k
#define tcg_gen_add2_i64 tcg_gen_add2_i64_m68k
#define tcg_gen_add_i32 tcg_gen_add_i32_m68k
#define tcg_gen_add_i64 tcg_gen_add_i64_m68k
#define tcg_gen_addi_i32 tcg_gen_addi_i32_m68k
#define tcg_gen_addi_i64 tcg_gen_addi_i64_m68k
#define tcg_gen_andc_i32 tcg_gen_andc_i32_m68k
#define tcg_gen_andc_i64 tcg_gen_andc_i64_m68k
#define tcg_gen_and_i32 tcg_gen_and_i32_m68k
#define tcg_gen_and_i64 tcg_gen_and_i64_m68k
#define tcg_gen_andi_i32 tcg_gen_andi_i32_m68k
@ -2703,8 +2705,12 @@
#define tcg_gen_brcond_i32 tcg_gen_brcond_i32_m68k
#define tcg_gen_brcond_i64 tcg_gen_brcond_i64_m68k
#define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_m68k
#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_m68k
#define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_m68k
#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_m68k
#define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_m68k
#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_m68k
#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_m68k
#define tcg_gen_callN tcg_gen_callN_m68k
#define tcg_gen_code tcg_gen_code_m68k
#define tcg_gen_code_common tcg_gen_code_common_m68k
@ -2712,16 +2718,36 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_m68k
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_m68k
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_m68k
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_m68k
#define tcg_gen_discard_i64 tcg_gen_discard_i64_m68k
#define tcg_gen_div_i32 tcg_gen_div_i32_m68k
#define tcg_gen_div_i64 tcg_gen_div_i64_m68k
#define tcg_gen_divu_i32 tcg_gen_divu_i32_m68k
#define tcg_gen_divu_i64 tcg_gen_divu_i64_m68k
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_m68k
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_m68k
#define tcg_gen_exit_tb tcg_gen_exit_tb_m68k
#define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_m68k
#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_m68k
#define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_m68k
#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_m68k
#define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_m68k
#define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_m68k
#define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_m68k
#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_m68k
#define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_m68k
#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_m68k
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_m68k
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_m68k
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_m68k
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_m68k
#define tcg_gen_goto_tb tcg_gen_goto_tb_m68k
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_m68k
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_m68k
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_m68k
#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_m68k
#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_m68k
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_m68k
#define tcg_gen_ld_i32 tcg_gen_ld_i32_m68k
#define tcg_gen_ld_i64 tcg_gen_ld_i64_m68k
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_m68k
@ -2733,12 +2759,28 @@
#define tcg_gen_movi_i32 tcg_gen_movi_i32_m68k
#define tcg_gen_movi_i64 tcg_gen_movi_i64_m68k
#define tcg_gen_mul_i32 tcg_gen_mul_i32_m68k
#define tcg_gen_mul_i64 tcg_gen_mul_i64_m68k
#define tcg_gen_muli_i32 tcg_gen_muli_i32_m68k
#define tcg_gen_muli_i64 tcg_gen_muli_i64_m68k
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_m68k
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_m68k
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_m68k
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_m68k
#define tcg_gen_nand_i32 tcg_gen_nand_i32_m68k
#define tcg_gen_nand_i64 tcg_gen_nand_i64_m68k
#define tcg_gen_neg_i32 tcg_gen_neg_i32_m68k
#define tcg_gen_neg_i64 tcg_gen_neg_i64_m68k
#define tcg_gen_nor_i32 tcg_gen_nor_i32_m68k
#define tcg_gen_nor_i64 tcg_gen_nor_i64_m68k
#define tcg_gen_not_i32 tcg_gen_not_i32_m68k
#define tcg_gen_not_i64 tcg_gen_not_i64_m68k
#define tcg_gen_op0 tcg_gen_op0_m68k
#define tcg_gen_op1 tcg_gen_op1_m68k
#define tcg_gen_op2 tcg_gen_op2_m68k
#define tcg_gen_op3 tcg_gen_op3_m68k
#define tcg_gen_op4 tcg_gen_op4_m68k
#define tcg_gen_op5 tcg_gen_op5_m68k
#define tcg_gen_op6 tcg_gen_op6_m68k
#define tcg_gen_op1i tcg_gen_op1i_m68k
#define tcg_gen_op2_i32 tcg_gen_op2_i32_m68k
#define tcg_gen_op2_i64 tcg_gen_op2_i64_m68k
@ -2755,20 +2797,35 @@
#define tcg_gen_op6i_i32 tcg_gen_op6i_i32_m68k
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_m68k
#define tcg_gen_orc_i32 tcg_gen_orc_i32_m68k
#define tcg_gen_orc_i64 tcg_gen_orc_i64_m68k
#define tcg_gen_or_i32 tcg_gen_or_i32_m68k
#define tcg_gen_or_i64 tcg_gen_or_i64_m68k
#define tcg_gen_ori_i32 tcg_gen_ori_i32_m68k
#define tcg_gen_ori_i64 tcg_gen_ori_i64_m68k
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_m68k
#define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_m68k
#define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_m68k
#define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_m68k
#define tcg_gen_rem_i32 tcg_gen_rem_i32_m68k
#define tcg_gen_rem_i64 tcg_gen_rem_i64_m68k
#define tcg_gen_remu_i32 tcg_gen_remu_i32_m68k
#define tcg_gen_remu_i64 tcg_gen_remu_i64_m68k
#define tcg_gen_rotl_i32 tcg_gen_rotl_i32_m68k
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_m68k
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_m68k
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_m68k
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_m68k
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_m68k
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_m68k
#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_m68k
#define tcg_gen_sar_i32 tcg_gen_sar_i32_m68k
#define tcg_gen_sar_i64 tcg_gen_sar_i64_m68k
#define tcg_gen_sari_i32 tcg_gen_sari_i32_m68k
#define tcg_gen_sari_i64 tcg_gen_sari_i64_m68k
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_m68k
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_m68k
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_m68k
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_m68k
#define tcg_gen_shl_i32 tcg_gen_shl_i32_m68k
#define tcg_gen_shl_i64 tcg_gen_shl_i64_m68k
#define tcg_gen_shli_i32 tcg_gen_shli_i32_m68k
@ -2780,14 +2837,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_m68k
#define tcg_gen_st_i32 tcg_gen_st_i32_m68k
#define tcg_gen_st_i64 tcg_gen_st_i64_m68k
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_m68k
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_m68k
#define tcg_gen_sub_i32 tcg_gen_sub_i32_m68k
#define tcg_gen_sub_i64 tcg_gen_sub_i64_m68k
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_m68k
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_m68k
#define tcg_gen_subi_i32 tcg_gen_subi_i32_m68k
#define tcg_gen_subi_i64 tcg_gen_subi_i64_m68k
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_m68k
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_m68k
#define tcg_gen_xor_i32 tcg_gen_xor_i32_m68k
#define tcg_gen_xor_i64 tcg_gen_xor_i64_m68k
#define tcg_gen_xori_i32 tcg_gen_xori_i32_m68k
#define tcg_gen_xori_i64 tcg_gen_xori_i64_m68k
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_m68k
#define tcg_get_arg_str_i64 tcg_get_arg_str_i64_m68k
#define tcg_get_arg_str_idx tcg_get_arg_str_idx_m68k

63
qemu/mips.h
View file

@ -2690,11 +2690,13 @@
#define tcg_func_start tcg_func_start_mips
#define tcg_gen_abs_i32 tcg_gen_abs_i32_mips
#define tcg_gen_add2_i32 tcg_gen_add2_i32_mips
#define tcg_gen_add2_i64 tcg_gen_add2_i64_mips
#define tcg_gen_add_i32 tcg_gen_add_i32_mips
#define tcg_gen_add_i64 tcg_gen_add_i64_mips
#define tcg_gen_addi_i32 tcg_gen_addi_i32_mips
#define tcg_gen_addi_i64 tcg_gen_addi_i64_mips
#define tcg_gen_andc_i32 tcg_gen_andc_i32_mips
#define tcg_gen_andc_i64 tcg_gen_andc_i64_mips
#define tcg_gen_and_i32 tcg_gen_and_i32_mips
#define tcg_gen_and_i64 tcg_gen_and_i64_mips
#define tcg_gen_andi_i32 tcg_gen_andi_i32_mips
@ -2703,8 +2705,12 @@
#define tcg_gen_brcond_i32 tcg_gen_brcond_i32_mips
#define tcg_gen_brcond_i64 tcg_gen_brcond_i64_mips
#define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_mips
#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_mips
#define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_mips
#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_mips
#define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_mips
#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_mips
#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_mips
#define tcg_gen_callN tcg_gen_callN_mips
#define tcg_gen_code tcg_gen_code_mips
#define tcg_gen_code_common tcg_gen_code_common_mips
@ -2712,16 +2718,36 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_mips
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_mips
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_mips
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_mips
#define tcg_gen_discard_i64 tcg_gen_discard_i64_mips
#define tcg_gen_div_i32 tcg_gen_div_i32_mips
#define tcg_gen_div_i64 tcg_gen_div_i64_mips
#define tcg_gen_divu_i32 tcg_gen_divu_i32_mips
#define tcg_gen_divu_i64 tcg_gen_divu_i64_mips
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_mips
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_mips
#define tcg_gen_exit_tb tcg_gen_exit_tb_mips
#define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_mips
#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_mips
#define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_mips
#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_mips
#define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_mips
#define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_mips
#define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_mips
#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_mips
#define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_mips
#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_mips
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_mips
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_mips
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_mips
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mips
#define tcg_gen_goto_tb tcg_gen_goto_tb_mips
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mips
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_mips
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_mips
#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_mips
#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_mips
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_mips
#define tcg_gen_ld_i32 tcg_gen_ld_i32_mips
#define tcg_gen_ld_i64 tcg_gen_ld_i64_mips
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_mips
@ -2733,12 +2759,28 @@
#define tcg_gen_movi_i32 tcg_gen_movi_i32_mips
#define tcg_gen_movi_i64 tcg_gen_movi_i64_mips
#define tcg_gen_mul_i32 tcg_gen_mul_i32_mips
#define tcg_gen_mul_i64 tcg_gen_mul_i64_mips
#define tcg_gen_muli_i32 tcg_gen_muli_i32_mips
#define tcg_gen_muli_i64 tcg_gen_muli_i64_mips
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_mips
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_mips
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_mips
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_mips
#define tcg_gen_nand_i32 tcg_gen_nand_i32_mips
#define tcg_gen_nand_i64 tcg_gen_nand_i64_mips
#define tcg_gen_neg_i32 tcg_gen_neg_i32_mips
#define tcg_gen_neg_i64 tcg_gen_neg_i64_mips
#define tcg_gen_nor_i32 tcg_gen_nor_i32_mips
#define tcg_gen_nor_i64 tcg_gen_nor_i64_mips
#define tcg_gen_not_i32 tcg_gen_not_i32_mips
#define tcg_gen_not_i64 tcg_gen_not_i64_mips
#define tcg_gen_op0 tcg_gen_op0_mips
#define tcg_gen_op1 tcg_gen_op1_mips
#define tcg_gen_op2 tcg_gen_op2_mips
#define tcg_gen_op3 tcg_gen_op3_mips
#define tcg_gen_op4 tcg_gen_op4_mips
#define tcg_gen_op5 tcg_gen_op5_mips
#define tcg_gen_op6 tcg_gen_op6_mips
#define tcg_gen_op1i tcg_gen_op1i_mips
#define tcg_gen_op2_i32 tcg_gen_op2_i32_mips
#define tcg_gen_op2_i64 tcg_gen_op2_i64_mips
@ -2755,20 +2797,35 @@
#define tcg_gen_op6i_i32 tcg_gen_op6i_i32_mips
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_mips
#define tcg_gen_orc_i32 tcg_gen_orc_i32_mips
#define tcg_gen_orc_i64 tcg_gen_orc_i64_mips
#define tcg_gen_or_i32 tcg_gen_or_i32_mips
#define tcg_gen_or_i64 tcg_gen_or_i64_mips
#define tcg_gen_ori_i32 tcg_gen_ori_i32_mips
#define tcg_gen_ori_i64 tcg_gen_ori_i64_mips
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_mips
#define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_mips
#define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_mips
#define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_mips
#define tcg_gen_rem_i32 tcg_gen_rem_i32_mips
#define tcg_gen_rem_i64 tcg_gen_rem_i64_mips
#define tcg_gen_remu_i32 tcg_gen_remu_i32_mips
#define tcg_gen_remu_i64 tcg_gen_remu_i64_mips
#define tcg_gen_rotl_i32 tcg_gen_rotl_i32_mips
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_mips
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_mips
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_mips
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_mips
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_mips
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_mips
#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_mips
#define tcg_gen_sar_i32 tcg_gen_sar_i32_mips
#define tcg_gen_sar_i64 tcg_gen_sar_i64_mips
#define tcg_gen_sari_i32 tcg_gen_sari_i32_mips
#define tcg_gen_sari_i64 tcg_gen_sari_i64_mips
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_mips
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mips
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_mips
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_mips
#define tcg_gen_shl_i32 tcg_gen_shl_i32_mips
#define tcg_gen_shl_i64 tcg_gen_shl_i64_mips
#define tcg_gen_shli_i32 tcg_gen_shli_i32_mips
@ -2780,14 +2837,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_mips
#define tcg_gen_st_i32 tcg_gen_st_i32_mips
#define tcg_gen_st_i64 tcg_gen_st_i64_mips
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_mips
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_mips
#define tcg_gen_sub_i32 tcg_gen_sub_i32_mips
#define tcg_gen_sub_i64 tcg_gen_sub_i64_mips
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_mips
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mips
#define tcg_gen_subi_i32 tcg_gen_subi_i32_mips
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mips
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_mips
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_mips
#define tcg_gen_xor_i32 tcg_gen_xor_i32_mips
#define tcg_gen_xor_i64 tcg_gen_xor_i64_mips
#define tcg_gen_xori_i32 tcg_gen_xori_i32_mips
#define tcg_gen_xori_i64 tcg_gen_xori_i64_mips
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_mips
#define tcg_get_arg_str_i64 tcg_get_arg_str_i64_mips
#define tcg_get_arg_str_idx tcg_get_arg_str_idx_mips

63
qemu/mips64.h
View file

@ -2690,11 +2690,13 @@
#define tcg_func_start tcg_func_start_mips64
#define tcg_gen_abs_i32 tcg_gen_abs_i32_mips64
#define tcg_gen_add2_i32 tcg_gen_add2_i32_mips64
#define tcg_gen_add2_i64 tcg_gen_add2_i64_mips64
#define tcg_gen_add_i32 tcg_gen_add_i32_mips64
#define tcg_gen_add_i64 tcg_gen_add_i64_mips64
#define tcg_gen_addi_i32 tcg_gen_addi_i32_mips64
#define tcg_gen_addi_i64 tcg_gen_addi_i64_mips64
#define tcg_gen_andc_i32 tcg_gen_andc_i32_mips64
#define tcg_gen_andc_i64 tcg_gen_andc_i64_mips64
#define tcg_gen_and_i32 tcg_gen_and_i32_mips64
#define tcg_gen_and_i64 tcg_gen_and_i64_mips64
#define tcg_gen_andi_i32 tcg_gen_andi_i32_mips64
@ -2703,8 +2705,12 @@
#define tcg_gen_brcond_i32 tcg_gen_brcond_i32_mips64
#define tcg_gen_brcond_i64 tcg_gen_brcond_i64_mips64
#define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_mips64
#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_mips64
#define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_mips64
#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_mips64
#define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_mips64
#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_mips64
#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_mips64
#define tcg_gen_callN tcg_gen_callN_mips64
#define tcg_gen_code tcg_gen_code_mips64
#define tcg_gen_code_common tcg_gen_code_common_mips64
@ -2712,16 +2718,36 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_mips64
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_mips64
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_mips64
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_mips64
#define tcg_gen_discard_i64 tcg_gen_discard_i64_mips64
#define tcg_gen_div_i32 tcg_gen_div_i32_mips64
#define tcg_gen_div_i64 tcg_gen_div_i64_mips64
#define tcg_gen_divu_i32 tcg_gen_divu_i32_mips64
#define tcg_gen_divu_i64 tcg_gen_divu_i64_mips64
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_mips64
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_mips64
#define tcg_gen_exit_tb tcg_gen_exit_tb_mips64
#define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_mips64
#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_mips64
#define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_mips64
#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_mips64
#define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_mips64
#define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_mips64
#define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_mips64
#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_mips64
#define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_mips64
#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_mips64
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_mips64
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_mips64
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_mips64
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mips64
#define tcg_gen_goto_tb tcg_gen_goto_tb_mips64
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mips64
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_mips64
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_mips64
#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_mips64
#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_mips64
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_mips64
#define tcg_gen_ld_i32 tcg_gen_ld_i32_mips64
#define tcg_gen_ld_i64 tcg_gen_ld_i64_mips64
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_mips64
@ -2733,12 +2759,28 @@
#define tcg_gen_movi_i32 tcg_gen_movi_i32_mips64
#define tcg_gen_movi_i64 tcg_gen_movi_i64_mips64
#define tcg_gen_mul_i32 tcg_gen_mul_i32_mips64
#define tcg_gen_mul_i64 tcg_gen_mul_i64_mips64
#define tcg_gen_muli_i32 tcg_gen_muli_i32_mips64
#define tcg_gen_muli_i64 tcg_gen_muli_i64_mips64
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_mips64
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_mips64
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_mips64
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_mips64
#define tcg_gen_nand_i32 tcg_gen_nand_i32_mips64
#define tcg_gen_nand_i64 tcg_gen_nand_i64_mips64
#define tcg_gen_neg_i32 tcg_gen_neg_i32_mips64
#define tcg_gen_neg_i64 tcg_gen_neg_i64_mips64
#define tcg_gen_nor_i32 tcg_gen_nor_i32_mips64
#define tcg_gen_nor_i64 tcg_gen_nor_i64_mips64
#define tcg_gen_not_i32 tcg_gen_not_i32_mips64
#define tcg_gen_not_i64 tcg_gen_not_i64_mips64
#define tcg_gen_op0 tcg_gen_op0_mips64
#define tcg_gen_op1 tcg_gen_op1_mips64
#define tcg_gen_op2 tcg_gen_op2_mips64
#define tcg_gen_op3 tcg_gen_op3_mips64
#define tcg_gen_op4 tcg_gen_op4_mips64
#define tcg_gen_op5 tcg_gen_op5_mips64
#define tcg_gen_op6 tcg_gen_op6_mips64
#define tcg_gen_op1i tcg_gen_op1i_mips64
#define tcg_gen_op2_i32 tcg_gen_op2_i32_mips64
#define tcg_gen_op2_i64 tcg_gen_op2_i64_mips64
@ -2755,20 +2797,35 @@
#define tcg_gen_op6i_i32 tcg_gen_op6i_i32_mips64
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_mips64
#define tcg_gen_orc_i32 tcg_gen_orc_i32_mips64
#define tcg_gen_orc_i64 tcg_gen_orc_i64_mips64
#define tcg_gen_or_i32 tcg_gen_or_i32_mips64
#define tcg_gen_or_i64 tcg_gen_or_i64_mips64
#define tcg_gen_ori_i32 tcg_gen_ori_i32_mips64
#define tcg_gen_ori_i64 tcg_gen_ori_i64_mips64
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_mips64
#define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_mips64
#define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_mips64
#define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_mips64
#define tcg_gen_rem_i32 tcg_gen_rem_i32_mips64
#define tcg_gen_rem_i64 tcg_gen_rem_i64_mips64
#define tcg_gen_remu_i32 tcg_gen_remu_i32_mips64
#define tcg_gen_remu_i64 tcg_gen_remu_i64_mips64
#define tcg_gen_rotl_i32 tcg_gen_rotl_i32_mips64
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_mips64
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_mips64
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_mips64
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_mips64
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_mips64
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_mips64
#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_mips64
#define tcg_gen_sar_i32 tcg_gen_sar_i32_mips64
#define tcg_gen_sar_i64 tcg_gen_sar_i64_mips64
#define tcg_gen_sari_i32 tcg_gen_sari_i32_mips64
#define tcg_gen_sari_i64 tcg_gen_sari_i64_mips64
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_mips64
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mips64
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_mips64
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_mips64
#define tcg_gen_shl_i32 tcg_gen_shl_i32_mips64
#define tcg_gen_shl_i64 tcg_gen_shl_i64_mips64
#define tcg_gen_shli_i32 tcg_gen_shli_i32_mips64
@ -2780,14 +2837,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_mips64
#define tcg_gen_st_i32 tcg_gen_st_i32_mips64
#define tcg_gen_st_i64 tcg_gen_st_i64_mips64
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_mips64
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_mips64
#define tcg_gen_sub_i32 tcg_gen_sub_i32_mips64
#define tcg_gen_sub_i64 tcg_gen_sub_i64_mips64
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_mips64
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mips64
#define tcg_gen_subi_i32 tcg_gen_subi_i32_mips64
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mips64
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_mips64
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_mips64
#define tcg_gen_xor_i32 tcg_gen_xor_i32_mips64
#define tcg_gen_xor_i64 tcg_gen_xor_i64_mips64
#define tcg_gen_xori_i32 tcg_gen_xori_i32_mips64
#define tcg_gen_xori_i64 tcg_gen_xori_i64_mips64
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_mips64
#define tcg_get_arg_str_i64 tcg_get_arg_str_i64_mips64
#define tcg_get_arg_str_idx tcg_get_arg_str_idx_mips64

63
qemu/mips64el.h
View file

@ -2690,11 +2690,13 @@
#define tcg_func_start tcg_func_start_mips64el
#define tcg_gen_abs_i32 tcg_gen_abs_i32_mips64el
#define tcg_gen_add2_i32 tcg_gen_add2_i32_mips64el
#define tcg_gen_add2_i64 tcg_gen_add2_i64_mips64el
#define tcg_gen_add_i32 tcg_gen_add_i32_mips64el
#define tcg_gen_add_i64 tcg_gen_add_i64_mips64el
#define tcg_gen_addi_i32 tcg_gen_addi_i32_mips64el
#define tcg_gen_addi_i64 tcg_gen_addi_i64_mips64el
#define tcg_gen_andc_i32 tcg_gen_andc_i32_mips64el
#define tcg_gen_andc_i64 tcg_gen_andc_i64_mips64el
#define tcg_gen_and_i32 tcg_gen_and_i32_mips64el
#define tcg_gen_and_i64 tcg_gen_and_i64_mips64el
#define tcg_gen_andi_i32 tcg_gen_andi_i32_mips64el
@ -2703,8 +2705,12 @@
#define tcg_gen_brcond_i32 tcg_gen_brcond_i32_mips64el
#define tcg_gen_brcond_i64 tcg_gen_brcond_i64_mips64el
#define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_mips64el
#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_mips64el
#define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_mips64el
#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_mips64el
#define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_mips64el
#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_mips64el
#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_mips64el
#define tcg_gen_callN tcg_gen_callN_mips64el
#define tcg_gen_code tcg_gen_code_mips64el
#define tcg_gen_code_common tcg_gen_code_common_mips64el
@ -2712,16 +2718,36 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_mips64el
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_mips64el
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_mips64el
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_mips64el
#define tcg_gen_discard_i64 tcg_gen_discard_i64_mips64el
#define tcg_gen_div_i32 tcg_gen_div_i32_mips64el
#define tcg_gen_div_i64 tcg_gen_div_i64_mips64el
#define tcg_gen_divu_i32 tcg_gen_divu_i32_mips64el
#define tcg_gen_divu_i64 tcg_gen_divu_i64_mips64el
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_mips64el
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_mips64el
#define tcg_gen_exit_tb tcg_gen_exit_tb_mips64el
#define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_mips64el
#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_mips64el
#define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_mips64el
#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_mips64el
#define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_mips64el
#define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_mips64el
#define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_mips64el
#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_mips64el
#define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_mips64el
#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_mips64el
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_mips64el
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_mips64el
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_mips64el
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mips64el
#define tcg_gen_goto_tb tcg_gen_goto_tb_mips64el
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mips64el
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_mips64el
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_mips64el
#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_mips64el
#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_mips64el
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_mips64el
#define tcg_gen_ld_i32 tcg_gen_ld_i32_mips64el
#define tcg_gen_ld_i64 tcg_gen_ld_i64_mips64el
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_mips64el
@ -2733,12 +2759,28 @@
#define tcg_gen_movi_i32 tcg_gen_movi_i32_mips64el
#define tcg_gen_movi_i64 tcg_gen_movi_i64_mips64el
#define tcg_gen_mul_i32 tcg_gen_mul_i32_mips64el
#define tcg_gen_mul_i64 tcg_gen_mul_i64_mips64el
#define tcg_gen_muli_i32 tcg_gen_muli_i32_mips64el
#define tcg_gen_muli_i64 tcg_gen_muli_i64_mips64el
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_mips64el
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_mips64el
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_mips64el
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_mips64el
#define tcg_gen_nand_i32 tcg_gen_nand_i32_mips64el
#define tcg_gen_nand_i64 tcg_gen_nand_i64_mips64el
#define tcg_gen_neg_i32 tcg_gen_neg_i32_mips64el
#define tcg_gen_neg_i64 tcg_gen_neg_i64_mips64el
#define tcg_gen_nor_i32 tcg_gen_nor_i32_mips64el
#define tcg_gen_nor_i64 tcg_gen_nor_i64_mips64el
#define tcg_gen_not_i32 tcg_gen_not_i32_mips64el
#define tcg_gen_not_i64 tcg_gen_not_i64_mips64el
#define tcg_gen_op0 tcg_gen_op0_mips64el
#define tcg_gen_op1 tcg_gen_op1_mips64el
#define tcg_gen_op2 tcg_gen_op2_mips64el
#define tcg_gen_op3 tcg_gen_op3_mips64el
#define tcg_gen_op4 tcg_gen_op4_mips64el
#define tcg_gen_op5 tcg_gen_op5_mips64el
#define tcg_gen_op6 tcg_gen_op6_mips64el
#define tcg_gen_op1i tcg_gen_op1i_mips64el
#define tcg_gen_op2_i32 tcg_gen_op2_i32_mips64el
#define tcg_gen_op2_i64 tcg_gen_op2_i64_mips64el
@ -2755,20 +2797,35 @@
#define tcg_gen_op6i_i32 tcg_gen_op6i_i32_mips64el
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_mips64el
#define tcg_gen_orc_i32 tcg_gen_orc_i32_mips64el
#define tcg_gen_orc_i64 tcg_gen_orc_i64_mips64el
#define tcg_gen_or_i32 tcg_gen_or_i32_mips64el
#define tcg_gen_or_i64 tcg_gen_or_i64_mips64el
#define tcg_gen_ori_i32 tcg_gen_ori_i32_mips64el
#define tcg_gen_ori_i64 tcg_gen_ori_i64_mips64el
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_mips64el
#define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_mips64el
#define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_mips64el
#define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_mips64el
#define tcg_gen_rem_i32 tcg_gen_rem_i32_mips64el
#define tcg_gen_rem_i64 tcg_gen_rem_i64_mips64el
#define tcg_gen_remu_i32 tcg_gen_remu_i32_mips64el
#define tcg_gen_remu_i64 tcg_gen_remu_i64_mips64el
#define tcg_gen_rotl_i32 tcg_gen_rotl_i32_mips64el
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_mips64el
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_mips64el
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_mips64el
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_mips64el
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_mips64el
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_mips64el
#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_mips64el
#define tcg_gen_sar_i32 tcg_gen_sar_i32_mips64el
#define tcg_gen_sar_i64 tcg_gen_sar_i64_mips64el
#define tcg_gen_sari_i32 tcg_gen_sari_i32_mips64el
#define tcg_gen_sari_i64 tcg_gen_sari_i64_mips64el
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_mips64el
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mips64el
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_mips64el
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_mips64el
#define tcg_gen_shl_i32 tcg_gen_shl_i32_mips64el
#define tcg_gen_shl_i64 tcg_gen_shl_i64_mips64el
#define tcg_gen_shli_i32 tcg_gen_shli_i32_mips64el
@ -2780,14 +2837,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_mips64el
#define tcg_gen_st_i32 tcg_gen_st_i32_mips64el
#define tcg_gen_st_i64 tcg_gen_st_i64_mips64el
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_mips64el
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_mips64el
#define tcg_gen_sub_i32 tcg_gen_sub_i32_mips64el
#define tcg_gen_sub_i64 tcg_gen_sub_i64_mips64el
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_mips64el
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mips64el
#define tcg_gen_subi_i32 tcg_gen_subi_i32_mips64el
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mips64el
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_mips64el
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_mips64el
#define tcg_gen_xor_i32 tcg_gen_xor_i32_mips64el
#define tcg_gen_xor_i64 tcg_gen_xor_i64_mips64el
#define tcg_gen_xori_i32 tcg_gen_xori_i32_mips64el
#define tcg_gen_xori_i64 tcg_gen_xori_i64_mips64el
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_mips64el
#define tcg_get_arg_str_i64 tcg_get_arg_str_i64_mips64el
#define tcg_get_arg_str_idx tcg_get_arg_str_idx_mips64el

63
qemu/mipsel.h
View file

@ -2690,11 +2690,13 @@
#define tcg_func_start tcg_func_start_mipsel
#define tcg_gen_abs_i32 tcg_gen_abs_i32_mipsel
#define tcg_gen_add2_i32 tcg_gen_add2_i32_mipsel
#define tcg_gen_add2_i64 tcg_gen_add2_i64_mipsel
#define tcg_gen_add_i32 tcg_gen_add_i32_mipsel
#define tcg_gen_add_i64 tcg_gen_add_i64_mipsel
#define tcg_gen_addi_i32 tcg_gen_addi_i32_mipsel
#define tcg_gen_addi_i64 tcg_gen_addi_i64_mipsel
#define tcg_gen_andc_i32 tcg_gen_andc_i32_mipsel
#define tcg_gen_andc_i64 tcg_gen_andc_i64_mipsel
#define tcg_gen_and_i32 tcg_gen_and_i32_mipsel
#define tcg_gen_and_i64 tcg_gen_and_i64_mipsel
#define tcg_gen_andi_i32 tcg_gen_andi_i32_mipsel
@ -2703,8 +2705,12 @@
#define tcg_gen_brcond_i32 tcg_gen_brcond_i32_mipsel
#define tcg_gen_brcond_i64 tcg_gen_brcond_i64_mipsel
#define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_mipsel
#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_mipsel
#define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_mipsel
#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_mipsel
#define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_mipsel
#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_mipsel
#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_mipsel
#define tcg_gen_callN tcg_gen_callN_mipsel
#define tcg_gen_code tcg_gen_code_mipsel
#define tcg_gen_code_common tcg_gen_code_common_mipsel
@ -2712,16 +2718,36 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_mipsel
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_mipsel
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_mipsel
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_mipsel
#define tcg_gen_discard_i64 tcg_gen_discard_i64_mipsel
#define tcg_gen_div_i32 tcg_gen_div_i32_mipsel
#define tcg_gen_div_i64 tcg_gen_div_i64_mipsel
#define tcg_gen_divu_i32 tcg_gen_divu_i32_mipsel
#define tcg_gen_divu_i64 tcg_gen_divu_i64_mipsel
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_mipsel
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_mipsel
#define tcg_gen_exit_tb tcg_gen_exit_tb_mipsel
#define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_mipsel
#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_mipsel
#define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_mipsel
#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_mipsel
#define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_mipsel
#define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_mipsel
#define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_mipsel
#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_mipsel
#define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_mipsel
#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_mipsel
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_mipsel
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_mipsel
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_mipsel
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mipsel
#define tcg_gen_goto_tb tcg_gen_goto_tb_mipsel
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mipsel
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_mipsel
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_mipsel
#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_mipsel
#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_mipsel
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_mipsel
#define tcg_gen_ld_i32 tcg_gen_ld_i32_mipsel
#define tcg_gen_ld_i64 tcg_gen_ld_i64_mipsel
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_mipsel
@ -2733,12 +2759,28 @@
#define tcg_gen_movi_i32 tcg_gen_movi_i32_mipsel
#define tcg_gen_movi_i64 tcg_gen_movi_i64_mipsel
#define tcg_gen_mul_i32 tcg_gen_mul_i32_mipsel
#define tcg_gen_mul_i64 tcg_gen_mul_i64_mipsel
#define tcg_gen_muli_i32 tcg_gen_muli_i32_mipsel
#define tcg_gen_muli_i64 tcg_gen_muli_i64_mipsel
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_mipsel
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_mipsel
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_mipsel
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_mipsel
#define tcg_gen_nand_i32 tcg_gen_nand_i32_mipsel
#define tcg_gen_nand_i64 tcg_gen_nand_i64_mipsel
#define tcg_gen_neg_i32 tcg_gen_neg_i32_mipsel
#define tcg_gen_neg_i64 tcg_gen_neg_i64_mipsel
#define tcg_gen_nor_i32 tcg_gen_nor_i32_mipsel
#define tcg_gen_nor_i64 tcg_gen_nor_i64_mipsel
#define tcg_gen_not_i32 tcg_gen_not_i32_mipsel
#define tcg_gen_not_i64 tcg_gen_not_i64_mipsel
#define tcg_gen_op0 tcg_gen_op0_mipsel
#define tcg_gen_op1 tcg_gen_op1_mipsel
#define tcg_gen_op2 tcg_gen_op2_mipsel
#define tcg_gen_op3 tcg_gen_op3_mipsel
#define tcg_gen_op4 tcg_gen_op4_mipsel
#define tcg_gen_op5 tcg_gen_op5_mipsel
#define tcg_gen_op6 tcg_gen_op6_mipsel
#define tcg_gen_op1i tcg_gen_op1i_mipsel
#define tcg_gen_op2_i32 tcg_gen_op2_i32_mipsel
#define tcg_gen_op2_i64 tcg_gen_op2_i64_mipsel
@ -2755,20 +2797,35 @@
#define tcg_gen_op6i_i32 tcg_gen_op6i_i32_mipsel
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_mipsel
#define tcg_gen_orc_i32 tcg_gen_orc_i32_mipsel
#define tcg_gen_orc_i64 tcg_gen_orc_i64_mipsel
#define tcg_gen_or_i32 tcg_gen_or_i32_mipsel
#define tcg_gen_or_i64 tcg_gen_or_i64_mipsel
#define tcg_gen_ori_i32 tcg_gen_ori_i32_mipsel
#define tcg_gen_ori_i64 tcg_gen_ori_i64_mipsel
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_mipsel
#define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_mipsel
#define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_mipsel
#define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_mipsel
#define tcg_gen_rem_i32 tcg_gen_rem_i32_mipsel
#define tcg_gen_rem_i64 tcg_gen_rem_i64_mipsel
#define tcg_gen_remu_i32 tcg_gen_remu_i32_mipsel
#define tcg_gen_remu_i64 tcg_gen_remu_i64_mipsel
#define tcg_gen_rotl_i32 tcg_gen_rotl_i32_mipsel
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_mipsel
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_mipsel
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_mipsel
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_mipsel
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_mipsel
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_mipsel
#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_mipsel
#define tcg_gen_sar_i32 tcg_gen_sar_i32_mipsel
#define tcg_gen_sar_i64 tcg_gen_sar_i64_mipsel
#define tcg_gen_sari_i32 tcg_gen_sari_i32_mipsel
#define tcg_gen_sari_i64 tcg_gen_sari_i64_mipsel
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_mipsel
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mipsel
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_mipsel
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_mipsel
#define tcg_gen_shl_i32 tcg_gen_shl_i32_mipsel
#define tcg_gen_shl_i64 tcg_gen_shl_i64_mipsel
#define tcg_gen_shli_i32 tcg_gen_shli_i32_mipsel
@ -2780,14 +2837,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_mipsel
#define tcg_gen_st_i32 tcg_gen_st_i32_mipsel
#define tcg_gen_st_i64 tcg_gen_st_i64_mipsel
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_mipsel
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_mipsel
#define tcg_gen_sub_i32 tcg_gen_sub_i32_mipsel
#define tcg_gen_sub_i64 tcg_gen_sub_i64_mipsel
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_mipsel
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_mipsel
#define tcg_gen_subi_i32 tcg_gen_subi_i32_mipsel
#define tcg_gen_subi_i64 tcg_gen_subi_i64_mipsel
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_mipsel
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_mipsel
#define tcg_gen_xor_i32 tcg_gen_xor_i32_mipsel
#define tcg_gen_xor_i64 tcg_gen_xor_i64_mipsel
#define tcg_gen_xori_i32 tcg_gen_xori_i32_mipsel
#define tcg_gen_xori_i64 tcg_gen_xori_i64_mipsel
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_mipsel
#define tcg_get_arg_str_i64 tcg_get_arg_str_i64_mipsel
#define tcg_get_arg_str_idx tcg_get_arg_str_idx_mipsel

63
qemu/powerpc.h
View file

@ -2690,11 +2690,13 @@
#define tcg_func_start tcg_func_start_powerpc
#define tcg_gen_abs_i32 tcg_gen_abs_i32_powerpc
#define tcg_gen_add2_i32 tcg_gen_add2_i32_powerpc
#define tcg_gen_add2_i64 tcg_gen_add2_i64_powerpc
#define tcg_gen_add_i32 tcg_gen_add_i32_powerpc
#define tcg_gen_add_i64 tcg_gen_add_i64_powerpc
#define tcg_gen_addi_i32 tcg_gen_addi_i32_powerpc
#define tcg_gen_addi_i64 tcg_gen_addi_i64_powerpc
#define tcg_gen_andc_i32 tcg_gen_andc_i32_powerpc
#define tcg_gen_andc_i64 tcg_gen_andc_i64_powerpc
#define tcg_gen_and_i32 tcg_gen_and_i32_powerpc
#define tcg_gen_and_i64 tcg_gen_and_i64_powerpc
#define tcg_gen_andi_i32 tcg_gen_andi_i32_powerpc
@ -2703,8 +2705,12 @@
#define tcg_gen_brcond_i32 tcg_gen_brcond_i32_powerpc
#define tcg_gen_brcond_i64 tcg_gen_brcond_i64_powerpc
#define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_powerpc
#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_powerpc
#define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_powerpc
#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_powerpc
#define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_powerpc
#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_powerpc
#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_powerpc
#define tcg_gen_callN tcg_gen_callN_powerpc
#define tcg_gen_code tcg_gen_code_powerpc
#define tcg_gen_code_common tcg_gen_code_common_powerpc
@ -2712,16 +2718,36 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_powerpc
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_powerpc
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_powerpc
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_powerpc
#define tcg_gen_discard_i64 tcg_gen_discard_i64_powerpc
#define tcg_gen_div_i32 tcg_gen_div_i32_powerpc
#define tcg_gen_div_i64 tcg_gen_div_i64_powerpc
#define tcg_gen_divu_i32 tcg_gen_divu_i32_powerpc
#define tcg_gen_divu_i64 tcg_gen_divu_i64_powerpc
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_powerpc
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_powerpc
#define tcg_gen_exit_tb tcg_gen_exit_tb_powerpc
#define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_powerpc
#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_powerpc
#define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_powerpc
#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_powerpc
#define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_powerpc
#define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_powerpc
#define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_powerpc
#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_powerpc
#define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_powerpc
#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_powerpc
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_powerpc
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_powerpc
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_powerpc
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_powerpc
#define tcg_gen_goto_tb tcg_gen_goto_tb_powerpc
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_powerpc
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_powerpc
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_powerpc
#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_powerpc
#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_powerpc
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_powerpc
#define tcg_gen_ld_i32 tcg_gen_ld_i32_powerpc
#define tcg_gen_ld_i64 tcg_gen_ld_i64_powerpc
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_powerpc
@ -2733,12 +2759,28 @@
#define tcg_gen_movi_i32 tcg_gen_movi_i32_powerpc
#define tcg_gen_movi_i64 tcg_gen_movi_i64_powerpc
#define tcg_gen_mul_i32 tcg_gen_mul_i32_powerpc
#define tcg_gen_mul_i64 tcg_gen_mul_i64_powerpc
#define tcg_gen_muli_i32 tcg_gen_muli_i32_powerpc
#define tcg_gen_muli_i64 tcg_gen_muli_i64_powerpc
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_powerpc
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_powerpc
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_powerpc
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_powerpc
#define tcg_gen_nand_i32 tcg_gen_nand_i32_powerpc
#define tcg_gen_nand_i64 tcg_gen_nand_i64_powerpc
#define tcg_gen_neg_i32 tcg_gen_neg_i32_powerpc
#define tcg_gen_neg_i64 tcg_gen_neg_i64_powerpc
#define tcg_gen_nor_i32 tcg_gen_nor_i32_powerpc
#define tcg_gen_nor_i64 tcg_gen_nor_i64_powerpc
#define tcg_gen_not_i32 tcg_gen_not_i32_powerpc
#define tcg_gen_not_i64 tcg_gen_not_i64_powerpc
#define tcg_gen_op0 tcg_gen_op0_powerpc
#define tcg_gen_op1 tcg_gen_op1_powerpc
#define tcg_gen_op2 tcg_gen_op2_powerpc
#define tcg_gen_op3 tcg_gen_op3_powerpc
#define tcg_gen_op4 tcg_gen_op4_powerpc
#define tcg_gen_op5 tcg_gen_op5_powerpc
#define tcg_gen_op6 tcg_gen_op6_powerpc
#define tcg_gen_op1i tcg_gen_op1i_powerpc
#define tcg_gen_op2_i32 tcg_gen_op2_i32_powerpc
#define tcg_gen_op2_i64 tcg_gen_op2_i64_powerpc
@ -2755,20 +2797,35 @@
#define tcg_gen_op6i_i32 tcg_gen_op6i_i32_powerpc
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_powerpc
#define tcg_gen_orc_i32 tcg_gen_orc_i32_powerpc
#define tcg_gen_orc_i64 tcg_gen_orc_i64_powerpc
#define tcg_gen_or_i32 tcg_gen_or_i32_powerpc
#define tcg_gen_or_i64 tcg_gen_or_i64_powerpc
#define tcg_gen_ori_i32 tcg_gen_ori_i32_powerpc
#define tcg_gen_ori_i64 tcg_gen_ori_i64_powerpc
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_powerpc
#define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_powerpc
#define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_powerpc
#define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_powerpc
#define tcg_gen_rem_i32 tcg_gen_rem_i32_powerpc
#define tcg_gen_rem_i64 tcg_gen_rem_i64_powerpc
#define tcg_gen_remu_i32 tcg_gen_remu_i32_powerpc
#define tcg_gen_remu_i64 tcg_gen_remu_i64_powerpc
#define tcg_gen_rotl_i32 tcg_gen_rotl_i32_powerpc
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_powerpc
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_powerpc
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_powerpc
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_powerpc
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_powerpc
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_powerpc
#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_powerpc
#define tcg_gen_sar_i32 tcg_gen_sar_i32_powerpc
#define tcg_gen_sar_i64 tcg_gen_sar_i64_powerpc
#define tcg_gen_sari_i32 tcg_gen_sari_i32_powerpc
#define tcg_gen_sari_i64 tcg_gen_sari_i64_powerpc
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_powerpc
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_powerpc
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_powerpc
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_powerpc
#define tcg_gen_shl_i32 tcg_gen_shl_i32_powerpc
#define tcg_gen_shl_i64 tcg_gen_shl_i64_powerpc
#define tcg_gen_shli_i32 tcg_gen_shli_i32_powerpc
@ -2780,14 +2837,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_powerpc
#define tcg_gen_st_i32 tcg_gen_st_i32_powerpc
#define tcg_gen_st_i64 tcg_gen_st_i64_powerpc
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_powerpc
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_powerpc
#define tcg_gen_sub_i32 tcg_gen_sub_i32_powerpc
#define tcg_gen_sub_i64 tcg_gen_sub_i64_powerpc
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_powerpc
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_powerpc
#define tcg_gen_subi_i32 tcg_gen_subi_i32_powerpc
#define tcg_gen_subi_i64 tcg_gen_subi_i64_powerpc
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_powerpc
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_powerpc
#define tcg_gen_xor_i32 tcg_gen_xor_i32_powerpc
#define tcg_gen_xor_i64 tcg_gen_xor_i64_powerpc
#define tcg_gen_xori_i32 tcg_gen_xori_i32_powerpc
#define tcg_gen_xori_i64 tcg_gen_xori_i64_powerpc
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_powerpc
#define tcg_get_arg_str_i64 tcg_get_arg_str_i64_powerpc
#define tcg_get_arg_str_idx tcg_get_arg_str_idx_powerpc

63
qemu/sparc.h
View file

@ -2690,11 +2690,13 @@
#define tcg_func_start tcg_func_start_sparc
#define tcg_gen_abs_i32 tcg_gen_abs_i32_sparc
#define tcg_gen_add2_i32 tcg_gen_add2_i32_sparc
#define tcg_gen_add2_i64 tcg_gen_add2_i64_sparc
#define tcg_gen_add_i32 tcg_gen_add_i32_sparc
#define tcg_gen_add_i64 tcg_gen_add_i64_sparc
#define tcg_gen_addi_i32 tcg_gen_addi_i32_sparc
#define tcg_gen_addi_i64 tcg_gen_addi_i64_sparc
#define tcg_gen_andc_i32 tcg_gen_andc_i32_sparc
#define tcg_gen_andc_i64 tcg_gen_andc_i64_sparc
#define tcg_gen_and_i32 tcg_gen_and_i32_sparc
#define tcg_gen_and_i64 tcg_gen_and_i64_sparc
#define tcg_gen_andi_i32 tcg_gen_andi_i32_sparc
@ -2703,8 +2705,12 @@
#define tcg_gen_brcond_i32 tcg_gen_brcond_i32_sparc
#define tcg_gen_brcond_i64 tcg_gen_brcond_i64_sparc
#define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_sparc
#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_sparc
#define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_sparc
#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_sparc
#define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_sparc
#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_sparc
#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_sparc
#define tcg_gen_callN tcg_gen_callN_sparc
#define tcg_gen_code tcg_gen_code_sparc
#define tcg_gen_code_common tcg_gen_code_common_sparc
@ -2712,16 +2718,36 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_sparc
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_sparc
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_sparc
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_sparc
#define tcg_gen_discard_i64 tcg_gen_discard_i64_sparc
#define tcg_gen_div_i32 tcg_gen_div_i32_sparc
#define tcg_gen_div_i64 tcg_gen_div_i64_sparc
#define tcg_gen_divu_i32 tcg_gen_divu_i32_sparc
#define tcg_gen_divu_i64 tcg_gen_divu_i64_sparc
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_sparc
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_sparc
#define tcg_gen_exit_tb tcg_gen_exit_tb_sparc
#define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_sparc
#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_sparc
#define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_sparc
#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_sparc
#define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_sparc
#define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_sparc
#define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_sparc
#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_sparc
#define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_sparc
#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_sparc
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_sparc
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_sparc
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_sparc
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_sparc
#define tcg_gen_goto_tb tcg_gen_goto_tb_sparc
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_sparc
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_sparc
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_sparc
#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_sparc
#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_sparc
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_sparc
#define tcg_gen_ld_i32 tcg_gen_ld_i32_sparc
#define tcg_gen_ld_i64 tcg_gen_ld_i64_sparc
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_sparc
@ -2733,12 +2759,28 @@
#define tcg_gen_movi_i32 tcg_gen_movi_i32_sparc
#define tcg_gen_movi_i64 tcg_gen_movi_i64_sparc
#define tcg_gen_mul_i32 tcg_gen_mul_i32_sparc
#define tcg_gen_mul_i64 tcg_gen_mul_i64_sparc
#define tcg_gen_muli_i32 tcg_gen_muli_i32_sparc
#define tcg_gen_muli_i64 tcg_gen_muli_i64_sparc
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_sparc
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_sparc
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_sparc
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_sparc
#define tcg_gen_nand_i32 tcg_gen_nand_i32_sparc
#define tcg_gen_nand_i64 tcg_gen_nand_i64_sparc
#define tcg_gen_neg_i32 tcg_gen_neg_i32_sparc
#define tcg_gen_neg_i64 tcg_gen_neg_i64_sparc
#define tcg_gen_nor_i32 tcg_gen_nor_i32_sparc
#define tcg_gen_nor_i64 tcg_gen_nor_i64_sparc
#define tcg_gen_not_i32 tcg_gen_not_i32_sparc
#define tcg_gen_not_i64 tcg_gen_not_i64_sparc
#define tcg_gen_op0 tcg_gen_op0_sparc
#define tcg_gen_op1 tcg_gen_op1_sparc
#define tcg_gen_op2 tcg_gen_op2_sparc
#define tcg_gen_op3 tcg_gen_op3_sparc
#define tcg_gen_op4 tcg_gen_op4_sparc
#define tcg_gen_op5 tcg_gen_op5_sparc
#define tcg_gen_op6 tcg_gen_op6_sparc
#define tcg_gen_op1i tcg_gen_op1i_sparc
#define tcg_gen_op2_i32 tcg_gen_op2_i32_sparc
#define tcg_gen_op2_i64 tcg_gen_op2_i64_sparc
@ -2755,20 +2797,35 @@
#define tcg_gen_op6i_i32 tcg_gen_op6i_i32_sparc
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_sparc
#define tcg_gen_orc_i32 tcg_gen_orc_i32_sparc
#define tcg_gen_orc_i64 tcg_gen_orc_i64_sparc
#define tcg_gen_or_i32 tcg_gen_or_i32_sparc
#define tcg_gen_or_i64 tcg_gen_or_i64_sparc
#define tcg_gen_ori_i32 tcg_gen_ori_i32_sparc
#define tcg_gen_ori_i64 tcg_gen_ori_i64_sparc
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_sparc
#define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_sparc
#define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_sparc
#define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_sparc
#define tcg_gen_rem_i32 tcg_gen_rem_i32_sparc
#define tcg_gen_rem_i64 tcg_gen_rem_i64_sparc
#define tcg_gen_remu_i32 tcg_gen_remu_i32_sparc
#define tcg_gen_remu_i64 tcg_gen_remu_i64_sparc
#define tcg_gen_rotl_i32 tcg_gen_rotl_i32_sparc
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_sparc
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_sparc
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_sparc
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_sparc
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_sparc
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_sparc
#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_sparc
#define tcg_gen_sar_i32 tcg_gen_sar_i32_sparc
#define tcg_gen_sar_i64 tcg_gen_sar_i64_sparc
#define tcg_gen_sari_i32 tcg_gen_sari_i32_sparc
#define tcg_gen_sari_i64 tcg_gen_sari_i64_sparc
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_sparc
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_sparc
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_sparc
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_sparc
#define tcg_gen_shl_i32 tcg_gen_shl_i32_sparc
#define tcg_gen_shl_i64 tcg_gen_shl_i64_sparc
#define tcg_gen_shli_i32 tcg_gen_shli_i32_sparc
@ -2780,14 +2837,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_sparc
#define tcg_gen_st_i32 tcg_gen_st_i32_sparc
#define tcg_gen_st_i64 tcg_gen_st_i64_sparc
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_sparc
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_sparc
#define tcg_gen_sub_i32 tcg_gen_sub_i32_sparc
#define tcg_gen_sub_i64 tcg_gen_sub_i64_sparc
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_sparc
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_sparc
#define tcg_gen_subi_i32 tcg_gen_subi_i32_sparc
#define tcg_gen_subi_i64 tcg_gen_subi_i64_sparc
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_sparc
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_sparc
#define tcg_gen_xor_i32 tcg_gen_xor_i32_sparc
#define tcg_gen_xor_i64 tcg_gen_xor_i64_sparc
#define tcg_gen_xori_i32 tcg_gen_xori_i32_sparc
#define tcg_gen_xori_i64 tcg_gen_xori_i64_sparc
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_sparc
#define tcg_get_arg_str_i64 tcg_get_arg_str_i64_sparc
#define tcg_get_arg_str_idx tcg_get_arg_str_idx_sparc

63
qemu/sparc64.h
View file

@ -2690,11 +2690,13 @@
#define tcg_func_start tcg_func_start_sparc64
#define tcg_gen_abs_i32 tcg_gen_abs_i32_sparc64
#define tcg_gen_add2_i32 tcg_gen_add2_i32_sparc64
#define tcg_gen_add2_i64 tcg_gen_add2_i64_sparc64
#define tcg_gen_add_i32 tcg_gen_add_i32_sparc64
#define tcg_gen_add_i64 tcg_gen_add_i64_sparc64
#define tcg_gen_addi_i32 tcg_gen_addi_i32_sparc64
#define tcg_gen_addi_i64 tcg_gen_addi_i64_sparc64
#define tcg_gen_andc_i32 tcg_gen_andc_i32_sparc64
#define tcg_gen_andc_i64 tcg_gen_andc_i64_sparc64
#define tcg_gen_and_i32 tcg_gen_and_i32_sparc64
#define tcg_gen_and_i64 tcg_gen_and_i64_sparc64
#define tcg_gen_andi_i32 tcg_gen_andi_i32_sparc64
@ -2703,8 +2705,12 @@
#define tcg_gen_brcond_i32 tcg_gen_brcond_i32_sparc64
#define tcg_gen_brcond_i64 tcg_gen_brcond_i64_sparc64
#define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_sparc64
#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_sparc64
#define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_sparc64
#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_sparc64
#define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_sparc64
#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_sparc64
#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_sparc64
#define tcg_gen_callN tcg_gen_callN_sparc64
#define tcg_gen_code tcg_gen_code_sparc64
#define tcg_gen_code_common tcg_gen_code_common_sparc64
@ -2712,16 +2718,36 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_sparc64
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_sparc64
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_sparc64
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_sparc64
#define tcg_gen_discard_i64 tcg_gen_discard_i64_sparc64
#define tcg_gen_div_i32 tcg_gen_div_i32_sparc64
#define tcg_gen_div_i64 tcg_gen_div_i64_sparc64
#define tcg_gen_divu_i32 tcg_gen_divu_i32_sparc64
#define tcg_gen_divu_i64 tcg_gen_divu_i64_sparc64
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_sparc64
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_sparc64
#define tcg_gen_exit_tb tcg_gen_exit_tb_sparc64
#define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_sparc64
#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_sparc64
#define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_sparc64
#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_sparc64
#define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_sparc64
#define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_sparc64
#define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_sparc64
#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_sparc64
#define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_sparc64
#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_sparc64
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_sparc64
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_sparc64
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_sparc64
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_sparc64
#define tcg_gen_goto_tb tcg_gen_goto_tb_sparc64
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_sparc64
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_sparc64
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_sparc64
#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_sparc64
#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_sparc64
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_sparc64
#define tcg_gen_ld_i32 tcg_gen_ld_i32_sparc64
#define tcg_gen_ld_i64 tcg_gen_ld_i64_sparc64
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_sparc64
@ -2733,12 +2759,28 @@
#define tcg_gen_movi_i32 tcg_gen_movi_i32_sparc64
#define tcg_gen_movi_i64 tcg_gen_movi_i64_sparc64
#define tcg_gen_mul_i32 tcg_gen_mul_i32_sparc64
#define tcg_gen_mul_i64 tcg_gen_mul_i64_sparc64
#define tcg_gen_muli_i32 tcg_gen_muli_i32_sparc64
#define tcg_gen_muli_i64 tcg_gen_muli_i64_sparc64
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_sparc64
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_sparc64
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_sparc64
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_sparc64
#define tcg_gen_nand_i32 tcg_gen_nand_i32_sparc64
#define tcg_gen_nand_i64 tcg_gen_nand_i64_sparc64
#define tcg_gen_neg_i32 tcg_gen_neg_i32_sparc64
#define tcg_gen_neg_i64 tcg_gen_neg_i64_sparc64
#define tcg_gen_nor_i32 tcg_gen_nor_i32_sparc64
#define tcg_gen_nor_i64 tcg_gen_nor_i64_sparc64
#define tcg_gen_not_i32 tcg_gen_not_i32_sparc64
#define tcg_gen_not_i64 tcg_gen_not_i64_sparc64
#define tcg_gen_op0 tcg_gen_op0_sparc64
#define tcg_gen_op1 tcg_gen_op1_sparc64
#define tcg_gen_op2 tcg_gen_op2_sparc64
#define tcg_gen_op3 tcg_gen_op3_sparc64
#define tcg_gen_op4 tcg_gen_op4_sparc64
#define tcg_gen_op5 tcg_gen_op5_sparc64
#define tcg_gen_op6 tcg_gen_op6_sparc64
#define tcg_gen_op1i tcg_gen_op1i_sparc64
#define tcg_gen_op2_i32 tcg_gen_op2_i32_sparc64
#define tcg_gen_op2_i64 tcg_gen_op2_i64_sparc64
@ -2755,20 +2797,35 @@
#define tcg_gen_op6i_i32 tcg_gen_op6i_i32_sparc64
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_sparc64
#define tcg_gen_orc_i32 tcg_gen_orc_i32_sparc64
#define tcg_gen_orc_i64 tcg_gen_orc_i64_sparc64
#define tcg_gen_or_i32 tcg_gen_or_i32_sparc64
#define tcg_gen_or_i64 tcg_gen_or_i64_sparc64
#define tcg_gen_ori_i32 tcg_gen_ori_i32_sparc64
#define tcg_gen_ori_i64 tcg_gen_ori_i64_sparc64
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_sparc64
#define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_sparc64
#define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_sparc64
#define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_sparc64
#define tcg_gen_rem_i32 tcg_gen_rem_i32_sparc64
#define tcg_gen_rem_i64 tcg_gen_rem_i64_sparc64
#define tcg_gen_remu_i32 tcg_gen_remu_i32_sparc64
#define tcg_gen_remu_i64 tcg_gen_remu_i64_sparc64
#define tcg_gen_rotl_i32 tcg_gen_rotl_i32_sparc64
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_sparc64
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_sparc64
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_sparc64
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_sparc64
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_sparc64
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_sparc64
#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_sparc64
#define tcg_gen_sar_i32 tcg_gen_sar_i32_sparc64
#define tcg_gen_sar_i64 tcg_gen_sar_i64_sparc64
#define tcg_gen_sari_i32 tcg_gen_sari_i32_sparc64
#define tcg_gen_sari_i64 tcg_gen_sari_i64_sparc64
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_sparc64
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_sparc64
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_sparc64
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_sparc64
#define tcg_gen_shl_i32 tcg_gen_shl_i32_sparc64
#define tcg_gen_shl_i64 tcg_gen_shl_i64_sparc64
#define tcg_gen_shli_i32 tcg_gen_shli_i32_sparc64
@ -2780,14 +2837,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_sparc64
#define tcg_gen_st_i32 tcg_gen_st_i32_sparc64
#define tcg_gen_st_i64 tcg_gen_st_i64_sparc64
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_sparc64
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_sparc64
#define tcg_gen_sub_i32 tcg_gen_sub_i32_sparc64
#define tcg_gen_sub_i64 tcg_gen_sub_i64_sparc64
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_sparc64
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_sparc64
#define tcg_gen_subi_i32 tcg_gen_subi_i32_sparc64
#define tcg_gen_subi_i64 tcg_gen_subi_i64_sparc64
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_sparc64
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_sparc64
#define tcg_gen_xor_i32 tcg_gen_xor_i32_sparc64
#define tcg_gen_xor_i64 tcg_gen_xor_i64_sparc64
#define tcg_gen_xori_i32 tcg_gen_xori_i32_sparc64
#define tcg_gen_xori_i64 tcg_gen_xori_i64_sparc64
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_sparc64
#define tcg_get_arg_str_i64 tcg_get_arg_str_i64_sparc64
#define tcg_get_arg_str_idx tcg_get_arg_str_idx_sparc64

2011
qemu/tcg/tcg-op.c Normal file
View file

File diff suppressed because it is too large Load diff

2444
qemu/tcg/tcg-op.h
View file

File diff suppressed because it is too large Load diff

170
qemu/tcg/tcg.c
View file

@ -853,176 +853,6 @@ void tcg_gen_callN(TCGContext *s, void *func, TCGArg ret,
#endif /* TCG_TARGET_EXTEND_ARGS */
}
#if TCG_TARGET_REG_BITS == 32
void tcg_gen_shifti_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1,
int c, int right, int arith)
{
if (c == 0) {
tcg_gen_mov_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1));
tcg_gen_mov_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1));
} else if (c >= 32) {
c -= 32;
if (right) {
if (arith) {
tcg_gen_sari_i32(s, TCGV_LOW(ret), TCGV_HIGH(arg1), c);
tcg_gen_sari_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), 31);
} else {
tcg_gen_shri_i32(s, TCGV_LOW(ret), TCGV_HIGH(arg1), c);
tcg_gen_movi_i32(s, TCGV_HIGH(ret), 0);
}
} else {
tcg_gen_shli_i32(s, TCGV_HIGH(ret), TCGV_LOW(arg1), c);
tcg_gen_movi_i32(s, TCGV_LOW(ret), 0);
}
} else {
TCGv_i32 t0, t1;
t0 = tcg_temp_new_i32(s);
t1 = tcg_temp_new_i32(s);
if (right) {
tcg_gen_shli_i32(s, t0, TCGV_HIGH(arg1), 32 - c);
if (arith)
tcg_gen_sari_i32(s, t1, TCGV_HIGH(arg1), c);
else
tcg_gen_shri_i32(s, t1, TCGV_HIGH(arg1), c);
tcg_gen_shri_i32(s, TCGV_LOW(ret), TCGV_LOW(arg1), c);
tcg_gen_or_i32(s, TCGV_LOW(ret), TCGV_LOW(ret), t0);
tcg_gen_mov_i32(s, TCGV_HIGH(ret), t1);
} else {
tcg_gen_shri_i32(s, t0, TCGV_LOW(arg1), 32 - c);
/* Note: ret can be the same as arg1, so we use t1 */
tcg_gen_shli_i32(s, t1, TCGV_LOW(arg1), c);
tcg_gen_shli_i32(s, TCGV_HIGH(ret), TCGV_HIGH(arg1), c);
tcg_gen_or_i32(s, TCGV_HIGH(ret), TCGV_HIGH(ret), t0);
tcg_gen_mov_i32(s, TCGV_LOW(ret), t1);
}
tcg_temp_free_i32(s, t0);
tcg_temp_free_i32(s, t1);
}
}
#endif
static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp op, bool is64, bool st)
{
switch (op & MO_SIZE) {
case MO_8:
op &= ~MO_BSWAP;
break;
case MO_16:
break;
case MO_32:
if (!is64) {
op &= ~MO_SIGN;
}
break;
case MO_64:
if (!is64) {
tcg_abort();
}
break;
}
if (st) {
op &= ~MO_SIGN;
}
return op;
}
// Unicorn engine
// check if the last memory access was invalid
// if so, we jump to the block epilogue to quit immediately.
void check_exit_request(TCGContext *tcg_ctx)
{
TCGv_i32 flag;
flag = tcg_temp_new_i32(tcg_ctx);
tcg_gen_ld_i32(tcg_ctx, flag, tcg_ctx->cpu_env,
offsetof(CPUState, tcg_exit_req) - ENV_OFFSET);
tcg_gen_brcondi_i32(tcg_ctx, TCG_COND_NE, flag, 0, tcg_ctx->exitreq_label);
tcg_temp_free_i32(tcg_ctx, flag);
}
void tcg_gen_qemu_ld_i32(struct uc_struct *uc, TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
{
TCGContext *tcg_ctx = uc->tcg_ctx;
memop = tcg_canonicalize_memop(memop, 0, 0);
*tcg_ctx->gen_opc_ptr++ = INDEX_op_qemu_ld_i32;
tcg_add_param_i32(tcg_ctx, val);
tcg_add_param_tl(tcg_ctx, addr);
*tcg_ctx->gen_opparam_ptr++ = memop;
*tcg_ctx->gen_opparam_ptr++ = idx;
check_exit_request(tcg_ctx);
}
void tcg_gen_qemu_st_i32(struct uc_struct *uc, TCGv_i32 val, TCGv addr, TCGArg idx, TCGMemOp memop)
{
TCGContext *tcg_ctx = uc->tcg_ctx;
memop = tcg_canonicalize_memop(memop, 0, 1);
*tcg_ctx->gen_opc_ptr++ = INDEX_op_qemu_st_i32;
tcg_add_param_i32(tcg_ctx, val);
tcg_add_param_tl(tcg_ctx, addr);
*tcg_ctx->gen_opparam_ptr++ = memop;
*tcg_ctx->gen_opparam_ptr++ = idx;
check_exit_request(tcg_ctx);
}
void tcg_gen_qemu_ld_i64(struct uc_struct *uc, TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)
{
TCGContext *tcg_ctx = uc->tcg_ctx;
memop = tcg_canonicalize_memop(memop, 1, 0);
#if TCG_TARGET_REG_BITS == 32
if ((memop & MO_SIZE) < MO_64) {
tcg_gen_qemu_ld_i32(uc, TCGV_LOW(val), addr, idx, memop);
if (memop & MO_SIGN) {
tcg_gen_sari_i32(tcg_ctx, TCGV_HIGH(val), TCGV_LOW(val), 31);
} else {
tcg_gen_movi_i32(tcg_ctx, TCGV_HIGH(val), 0);
}
check_exit_request(tcg_ctx);
return;
}
#endif
*tcg_ctx->gen_opc_ptr++ = INDEX_op_qemu_ld_i64;
tcg_add_param_i64(tcg_ctx, val);
tcg_add_param_tl(tcg_ctx, addr);
*tcg_ctx->gen_opparam_ptr++ = memop;
*tcg_ctx->gen_opparam_ptr++ = idx;
check_exit_request(tcg_ctx);
}
void tcg_gen_qemu_st_i64(struct uc_struct *uc, TCGv_i64 val, TCGv addr, TCGArg idx, TCGMemOp memop)
{
TCGContext *tcg_ctx = uc->tcg_ctx;
memop = tcg_canonicalize_memop(memop, 1, 1);
#if TCG_TARGET_REG_BITS == 32
if ((memop & MO_SIZE) < MO_64) {
tcg_gen_qemu_st_i32(uc, TCGV_LOW(val), addr, idx, memop);
check_exit_request(tcg_ctx);
return;
}
#endif
*tcg_ctx->gen_opc_ptr++ = INDEX_op_qemu_st_i64;
tcg_add_param_i64(tcg_ctx, val);
tcg_add_param_tl(tcg_ctx, addr);
*tcg_ctx->gen_opparam_ptr++ = memop;
*tcg_ctx->gen_opparam_ptr++ = idx;
check_exit_request(tcg_ctx);
}
static void tcg_reg_alloc_start(TCGContext *s)
{
int i;

5
qemu/tcg/tcg.h
View file

@ -830,9 +830,6 @@ void tcg_add_target_add_op_defs(TCGContext *s, const TCGTargetOpDef *tdefs);
void tcg_gen_callN(TCGContext *s, void *func,
TCGArg ret, int nargs, TCGArg *args);
void tcg_gen_shifti_i64(TCGContext *s, TCGv_i64 ret, TCGv_i64 arg1,
int c, int right, int arith);
TCGArg *tcg_optimize(TCGContext *s, uint16_t *tcg_opc_ptr, TCGArg *args,
TCGOpDef *tcg_op_def);
@ -1025,8 +1022,6 @@ void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
# define helper_ret_stq_mmu helper_le_stq_mmu
#endif
void check_exit_request(TCGContext *tcg_ctx);
#endif /* CONFIG_SOFTMMU */
#endif /* TCG_H */

63
qemu/x86_64.h
View file

@ -2690,11 +2690,13 @@
#define tcg_func_start tcg_func_start_x86_64
#define tcg_gen_abs_i32 tcg_gen_abs_i32_x86_64
#define tcg_gen_add2_i32 tcg_gen_add2_i32_x86_64
#define tcg_gen_add2_i64 tcg_gen_add2_i64_x86_64
#define tcg_gen_add_i32 tcg_gen_add_i32_x86_64
#define tcg_gen_add_i64 tcg_gen_add_i64_x86_64
#define tcg_gen_addi_i32 tcg_gen_addi_i32_x86_64
#define tcg_gen_addi_i64 tcg_gen_addi_i64_x86_64
#define tcg_gen_andc_i32 tcg_gen_andc_i32_x86_64
#define tcg_gen_andc_i64 tcg_gen_andc_i64_x86_64
#define tcg_gen_and_i32 tcg_gen_and_i32_x86_64
#define tcg_gen_and_i64 tcg_gen_and_i64_x86_64
#define tcg_gen_andi_i32 tcg_gen_andi_i32_x86_64
@ -2703,8 +2705,12 @@
#define tcg_gen_brcond_i32 tcg_gen_brcond_i32_x86_64
#define tcg_gen_brcond_i64 tcg_gen_brcond_i64_x86_64
#define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_x86_64
#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_x86_64
#define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_x86_64
#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_x86_64
#define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_x86_64
#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_x86_64
#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_x86_64
#define tcg_gen_callN tcg_gen_callN_x86_64
#define tcg_gen_code tcg_gen_code_x86_64
#define tcg_gen_code_common tcg_gen_code_common_x86_64
@ -2712,16 +2718,36 @@
#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_x86_64
#define tcg_gen_debug_insn_start tcg_gen_debug_insn_start_x86_64
#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_x86_64
#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_x86_64
#define tcg_gen_discard_i64 tcg_gen_discard_i64_x86_64
#define tcg_gen_div_i32 tcg_gen_div_i32_x86_64
#define tcg_gen_div_i64 tcg_gen_div_i64_x86_64
#define tcg_gen_divu_i32 tcg_gen_divu_i32_x86_64
#define tcg_gen_divu_i64 tcg_gen_divu_i64_x86_64
#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_x86_64
#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_x86_64
#define tcg_gen_exit_tb tcg_gen_exit_tb_x86_64
#define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_x86_64
#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_x86_64
#define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_x86_64
#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_x86_64
#define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_x86_64
#define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_x86_64
#define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_x86_64
#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_x86_64
#define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_x86_64
#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_x86_64
#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_x86_64
#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_x86_64
#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_x86_64
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_x86_64
#define tcg_gen_goto_tb tcg_gen_goto_tb_x86_64
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_x86_64
#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_x86_64
#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_x86_64
#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_x86_64
#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_x86_64
#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_x86_64
#define tcg_gen_ld_i32 tcg_gen_ld_i32_x86_64
#define tcg_gen_ld_i64 tcg_gen_ld_i64_x86_64
#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_x86_64
@ -2733,12 +2759,28 @@
#define tcg_gen_movi_i32 tcg_gen_movi_i32_x86_64
#define tcg_gen_movi_i64 tcg_gen_movi_i64_x86_64
#define tcg_gen_mul_i32 tcg_gen_mul_i32_x86_64
#define tcg_gen_mul_i64 tcg_gen_mul_i64_x86_64
#define tcg_gen_muli_i32 tcg_gen_muli_i32_x86_64
#define tcg_gen_muli_i64 tcg_gen_muli_i64_x86_64
#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_x86_64
#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_x86_64
#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_x86_64
#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_x86_64
#define tcg_gen_nand_i32 tcg_gen_nand_i32_x86_64
#define tcg_gen_nand_i64 tcg_gen_nand_i64_x86_64
#define tcg_gen_neg_i32 tcg_gen_neg_i32_x86_64
#define tcg_gen_neg_i64 tcg_gen_neg_i64_x86_64
#define tcg_gen_nor_i32 tcg_gen_nor_i32_x86_64
#define tcg_gen_nor_i64 tcg_gen_nor_i64_x86_64
#define tcg_gen_not_i32 tcg_gen_not_i32_x86_64
#define tcg_gen_not_i64 tcg_gen_not_i64_x86_64
#define tcg_gen_op0 tcg_gen_op0_x86_64
#define tcg_gen_op1 tcg_gen_op1_x86_64
#define tcg_gen_op2 tcg_gen_op2_x86_64
#define tcg_gen_op3 tcg_gen_op3_x86_64
#define tcg_gen_op4 tcg_gen_op4_x86_64
#define tcg_gen_op5 tcg_gen_op5_x86_64
#define tcg_gen_op6 tcg_gen_op6_x86_64
#define tcg_gen_op1i tcg_gen_op1i_x86_64
#define tcg_gen_op2_i32 tcg_gen_op2_i32_x86_64
#define tcg_gen_op2_i64 tcg_gen_op2_i64_x86_64
@ -2755,20 +2797,35 @@
#define tcg_gen_op6i_i32 tcg_gen_op6i_i32_x86_64
#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_x86_64
#define tcg_gen_orc_i32 tcg_gen_orc_i32_x86_64
#define tcg_gen_orc_i64 tcg_gen_orc_i64_x86_64
#define tcg_gen_or_i32 tcg_gen_or_i32_x86_64
#define tcg_gen_or_i64 tcg_gen_or_i64_x86_64
#define tcg_gen_ori_i32 tcg_gen_ori_i32_x86_64
#define tcg_gen_ori_i64 tcg_gen_ori_i64_x86_64
#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_x86_64
#define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_x86_64
#define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_x86_64
#define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_x86_64
#define tcg_gen_rem_i32 tcg_gen_rem_i32_x86_64
#define tcg_gen_rem_i64 tcg_gen_rem_i64_x86_64
#define tcg_gen_remu_i32 tcg_gen_remu_i32_x86_64
#define tcg_gen_remu_i64 tcg_gen_remu_i64_x86_64
#define tcg_gen_rotl_i32 tcg_gen_rotl_i32_x86_64
#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_x86_64
#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_x86_64
#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_x86_64
#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_x86_64
#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_x86_64
#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_x86_64
#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_x86_64
#define tcg_gen_sar_i32 tcg_gen_sar_i32_x86_64
#define tcg_gen_sar_i64 tcg_gen_sar_i64_x86_64
#define tcg_gen_sari_i32 tcg_gen_sari_i32_x86_64
#define tcg_gen_sari_i64 tcg_gen_sari_i64_x86_64
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_x86_64
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_x86_64
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_x86_64
#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_x86_64
#define tcg_gen_shl_i32 tcg_gen_shl_i32_x86_64
#define tcg_gen_shl_i64 tcg_gen_shl_i64_x86_64
#define tcg_gen_shli_i32 tcg_gen_shli_i32_x86_64
@ -2780,14 +2837,20 @@
#define tcg_gen_shri_i64 tcg_gen_shri_i64_x86_64
#define tcg_gen_st_i32 tcg_gen_st_i32_x86_64
#define tcg_gen_st_i64 tcg_gen_st_i64_x86_64
#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_x86_64
#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_x86_64
#define tcg_gen_sub_i32 tcg_gen_sub_i32_x86_64
#define tcg_gen_sub_i64 tcg_gen_sub_i64_x86_64
#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_x86_64
#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_x86_64
#define tcg_gen_subi_i32 tcg_gen_subi_i32_x86_64
#define tcg_gen_subi_i64 tcg_gen_subi_i64_x86_64
#define tcg_gen_trunc_i64_i32 tcg_gen_trunc_i64_i32_x86_64
#define tcg_gen_trunc_shr_i64_i32 tcg_gen_trunc_shr_i64_i32_x86_64
#define tcg_gen_xor_i32 tcg_gen_xor_i32_x86_64
#define tcg_gen_xor_i64 tcg_gen_xor_i64_x86_64
#define tcg_gen_xori_i32 tcg_gen_xori_i32_x86_64
#define tcg_gen_xori_i64 tcg_gen_xori_i64_x86_64
#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_x86_64
#define tcg_get_arg_str_i64 tcg_get_arg_str_i64_x86_64
#define tcg_get_arg_str_idx tcg_get_arg_str_idx_x86_64