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i386: Add new property to control cache info

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The property legacy-cache will be used to control the cache information.
If user passes "-cpu legacy-cache" then older information will
be displayed even if the hardware supports new information. Otherwise
use the statically loaded cache definitions if available.

Renamed the previous cache structures to legacy_*. If there is any change in
the cache information, then it needs to be initialized in builtin_x86_defs.

Backports commit ab8f992e3e63e91be257e4e343d386dae7be4bcb from qemu
This commit is contained in:
Babu Moger 2018-05-17 19:04:52 -04:00 committed by Lioncash
parent 1add2da704
commit 5091ebe6fb
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 70 additions and 26 deletions
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91
qemu/target/i386/cpu.c
View file

@ -323,10 +323,14 @@ static void encode_cache_cpuid80000006(CPUCacheInfo *l2,
} }
} }
/* Definitions of the hardcoded cache entries we expose: */ /*
* Definitions of the hardcoded cache entries we expose:
* These are legacy cache values. If there is a need to change any
* of these values please use builtin_x86_defs
*/
/* L1 data cache: */ /* L1 data cache: */
static CPUCacheInfo l1d_cache = { static CPUCacheInfo legacy_l1d_cache = {
DCACHE, DCACHE,
1, 1,
32 * KiB, 32 * KiB,
@ -340,7 +344,7 @@ static CPUCacheInfo l1d_cache = {
}; };
/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
static CPUCacheInfo l1d_cache_amd = { static CPUCacheInfo legacy_l1d_cache_amd = {
DCACHE, DCACHE,
1, 1,
64 * KiB, 64 * KiB,
@ -354,7 +358,7 @@ static CPUCacheInfo l1d_cache_amd = {
}; };
/* L1 instruction cache: */ /* L1 instruction cache: */
static CPUCacheInfo l1i_cache = { static CPUCacheInfo legacy_l1i_cache = {
ICACHE, ICACHE,
1, 1,
32 * KiB, 32 * KiB,
@ -366,7 +370,7 @@ static CPUCacheInfo l1i_cache = {
}; };
/*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */ /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
static CPUCacheInfo l1i_cache_amd = { static CPUCacheInfo legacy_l1i_cache_amd = {
ICACHE, ICACHE,
1, 1,
64 * KiB, 64 * KiB,
@ -380,7 +384,7 @@ static CPUCacheInfo l1i_cache_amd = {
}; };
/* Level 2 unified cache: */ /* Level 2 unified cache: */
static CPUCacheInfo l2_cache = { static CPUCacheInfo legacy_l2_cache = {
UNIFIED_CACHE, UNIFIED_CACHE,
2, 2,
4 * MiB, 4 * MiB,
@ -394,7 +398,7 @@ static CPUCacheInfo l2_cache = {
}; };
/*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */ /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
static CPUCacheInfo l2_cache_cpuid2 = { static CPUCacheInfo legacy_l2_cache_cpuid2 = {
UNIFIED_CACHE, UNIFIED_CACHE,
2, 2,
2 * MiB, 2 * MiB,
@ -403,7 +407,7 @@ static CPUCacheInfo l2_cache_cpuid2 = {
}; };
/*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */ /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
static CPUCacheInfo l2_cache_amd = { static CPUCacheInfo legacy_l2_cache_amd = {
UNIFIED_CACHE, UNIFIED_CACHE,
2, 2,
512 * KiB, 512 * KiB,
@ -415,7 +419,7 @@ static CPUCacheInfo l2_cache_amd = {
}; };
/* Level 3 unified cache: */ /* Level 3 unified cache: */
static CPUCacheInfo l3_cache = { static CPUCacheInfo legacy_l3_cache = {
UNIFIED_CACHE, UNIFIED_CACHE,
3, 3,
16 * MiB, 16 * MiB,
@ -3561,6 +3565,10 @@ static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
env->features[w] = def->features[w]; env->features[w] = def->features[w];
} }
/* Store Cache information from the X86CPUDefinition if available */
env->cache_info = def->cache_info;
cpu->legacy_cache = def->cache_info ? 0 : 1;
if (tcg_enabled(env->uc)) { if (tcg_enabled(env->uc)) {
x86_cpu_apply_props(cpu, tcg_default_props); x86_cpu_apply_props(cpu, tcg_default_props);
} }
@ -3684,11 +3692,21 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
if (!cpu->enable_l3_cache) { if (!cpu->enable_l3_cache) {
*ecx = 0; *ecx = 0;
} else { } else {
*ecx = cpuid2_cache_descriptor(&l3_cache); if (env->cache_info && !cpu->legacy_cache) {
*ecx = cpuid2_cache_descriptor(&env->cache_info->l3_cache);
} else {
*ecx = cpuid2_cache_descriptor(&legacy_l3_cache);
}
}
if (env->cache_info && !cpu->legacy_cache) {
*edx = (cpuid2_cache_descriptor(&env->cache_info->l1d_cache) << 16) |
(cpuid2_cache_descriptor(&env->cache_info->l1i_cache) << 8) |
(cpuid2_cache_descriptor(&env->cache_info->l2_cache));
} else {
*edx = (cpuid2_cache_descriptor(&legacy_l1d_cache) << 16) |
(cpuid2_cache_descriptor(&legacy_l1i_cache) << 8) |
(cpuid2_cache_descriptor(&legacy_l2_cache_cpuid2));
} }
*edx = (cpuid2_cache_descriptor(&l1d_cache) << 16) |
(cpuid2_cache_descriptor(&l1i_cache) << 8) |
(cpuid2_cache_descriptor(&l2_cache_cpuid2));
break; break;
case 4: case 4:
/* cache info: needed for Core compatibility */ /* cache info: needed for Core compatibility */
@ -3701,27 +3719,35 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
} }
} else { } else {
*eax = 0; *eax = 0;
CPUCacheInfo *l1d, *l1i, *l2, *l3;
if (env->cache_info && !cpu->legacy_cache) {
l1d = &env->cache_info->l1d_cache;
l1i = &env->cache_info->l1i_cache;
l2 = &env->cache_info->l2_cache;
l3 = &env->cache_info->l3_cache;
} else {
l1d = &legacy_l1d_cache;
l1i = &legacy_l1i_cache;
l2 = &legacy_l2_cache;
l3 = &legacy_l3_cache;
}
switch (count) { switch (count) {
case 0: /* L1 dcache info */ case 0: /* L1 dcache info */
encode_cache_cpuid4(&l1d_cache, encode_cache_cpuid4(l1d, 1, cs->nr_cores,
1, cs->nr_cores,
eax, ebx, ecx, edx); eax, ebx, ecx, edx);
break; break;
case 1: /* L1 icache info */ case 1: /* L1 icache info */
encode_cache_cpuid4(&l1i_cache, encode_cache_cpuid4(l1i, 1, cs->nr_cores,
1, cs->nr_cores,
eax, ebx, ecx, edx); eax, ebx, ecx, edx);
break; break;
case 2: /* L2 cache info */ case 2: /* L2 cache info */
encode_cache_cpuid4(&l2_cache, encode_cache_cpuid4(l2, cs->nr_threads, cs->nr_cores,
cs->nr_threads, cs->nr_cores,
eax, ebx, ecx, edx); eax, ebx, ecx, edx);
break; break;
case 3: /* L3 cache info */ case 3: /* L3 cache info */
pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads); pkg_offset = apicid_pkg_offset(cs->nr_cores, cs->nr_threads);
if (cpu->enable_l3_cache) { if (cpu->enable_l3_cache) {
encode_cache_cpuid4(&l3_cache, encode_cache_cpuid4(l3, (1 << pkg_offset), cs->nr_cores,
(1 << pkg_offset), cs->nr_cores,
eax, ebx, ecx, edx); eax, ebx, ecx, edx);
break; break;
} }
@ -3925,8 +3951,13 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
(L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES); (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
*ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \ *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
(L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES); (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
*ecx = encode_cache_cpuid80000005(&l1d_cache_amd); if (env->cache_info && !cpu->legacy_cache) {
*edx = encode_cache_cpuid80000005(&l1i_cache_amd); *ecx = encode_cache_cpuid80000005(&env->cache_info->l1d_cache);
*edx = encode_cache_cpuid80000005(&env->cache_info->l1i_cache);
} else {
*ecx = encode_cache_cpuid80000005(&legacy_l1d_cache_amd);
*edx = encode_cache_cpuid80000005(&legacy_l1i_cache_amd);
}
break; break;
case 0x80000006: case 0x80000006:
/* cache info (L2 cache) */ /* cache info (L2 cache) */
@ -3942,9 +3973,17 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
(L2_DTLB_4K_ENTRIES << 16) | \ (L2_DTLB_4K_ENTRIES << 16) | \
(AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \ (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
(L2_ITLB_4K_ENTRIES); (L2_ITLB_4K_ENTRIES);
encode_cache_cpuid80000006(&l2_cache_amd, if (env->cache_info && !cpu->legacy_cache) {
cpu->enable_l3_cache ? &l3_cache : NULL, encode_cache_cpuid80000006(&env->cache_info->l2_cache,
ecx, edx); cpu->enable_l3_cache ?
&env->cache_info->l3_cache : NULL,
ecx, edx);
} else {
encode_cache_cpuid80000006(&legacy_l2_cache_amd,
cpu->enable_l3_cache ?
&legacy_l3_cache : NULL,
ecx, edx);
}
break; break;
case 0x80000007: case 0x80000007:
*eax = 0; *eax = 0;

5
qemu/target/i386/cpu.h
View file

@ -1326,6 +1326,11 @@ typedef struct X86CPU {
*/ */
bool enable_l3_cache; bool enable_l3_cache;
/* Compatibility bits for old machine types.
* If true present the old cache topology information
*/
bool legacy_cache;
/* Compatibility bits for old machine types: */ /* Compatibility bits for old machine types: */
bool enable_cpuid_0xb; bool enable_cpuid_0xb;