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target/arm: Convert Neon 3-same-fp size field to MO_* in decode
In the Neon instructions, some instruction formats have a 2-bit size field which corresponds exactly to QEMU's MO_8/16/32/64. However the floating-point insns in the 3-same group have a 1-bit size field which is "0 for 32-bit float and 1 for 16-bit float". Currently we pass these values directly through to trans_ functions, which means that when reading a particular trans_ function you need to know if that insn uses a 2-bit size or a 1-bit size. Move the handling of the 1-bit size to the decodetree file, so that all these insns consistently pass a size to the trans_ function which is an MO_8/16/32/64 value. In this commit we switch over the insns using the 3same_fp and 3same_fp_q0 formats. Backports commit 6cf0f240e0b980a877abed12d2995f740eae6515
This commit is contained in:
parent
cd79d2a915
commit
524b54bc7b
qemu/target/arm
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@ -45,11 +45,16 @@
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@3same_q0 .... ... . . . size:2 .... .... .... . 0 . . .... \
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&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
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# For FP insns the high bit of 'size' is used as part of opcode decode
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@3same_fp .... ... . . . . size:1 .... .... .... . q:1 . . .... \
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&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp
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@3same_fp_q0 .... ... . . . . size:1 .... .... .... . 0 . . .... \
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&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0
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# For FP insns the high bit of 'size' is used as part of opcode decode,
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# and the 'size' bit is 0 for 32-bit float and 1 for 16-bit float.
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# This converts this encoding to the same MO_8/16/32/64 values that the
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# integer neon insns use.
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%3same_fp_size 20:1 !function=neon_3same_fp_size
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@3same_fp .... ... . . . . . .... .... .... . q:1 . . .... \
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&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp size=%3same_fp_size
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@3same_fp_q0 .... ... . . . . . .... .... .... . 0 . . .... \
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&3same vm=%vm_dp vn=%vn_dp vd=%vd_dp q=0 size=%3same_fp_size
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VHADD_S_3s 1111 001 0 0 . .. .... .... 0000 . . . 0 .... @3same
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VHADD_U_3s 1111 001 1 0 . .. .... .... 0000 . . . 0 .... @3same
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@ -49,6 +49,12 @@ static inline int rsub_8(DisasContext *s, int x)
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return 8 - x;
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}
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static inline int neon_3same_fp_size(DisasContext *s, int x)
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{
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/* Convert 0==fp32, 1==fp16 into a MO_* value */
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return MO_32 - x;
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}
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/* Include the generated Neon decoder */
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#include "decode-neon-dp.inc.c"
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#include "decode-neon-ls.inc.c"
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@ -1067,7 +1073,7 @@ DO_3SAME_VQDMULH(VQRDMULH, qrdmulh)
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WRAP_FP_GVEC(gen_##INSN##_fp16_3s, FPST_STD_F16, HFUNC) \
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static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \
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{ \
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if (a->size != 0) { \
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if (a->size == MO_16) { \
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if (!dc_isar_feature(aa32_fp16_arith, s)) { \
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return false; \
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} \
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@ -1106,7 +1112,7 @@ static bool trans_VMAXNM_fp_3s(DisasContext *s, arg_3same *a)
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return false;
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}
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if (a->size != 0) {
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if (a->size == MO_16) {
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if (!dc_isar_feature(aa32_fp16_arith, s)) {
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return false;
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}
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@ -1122,7 +1128,7 @@ static bool trans_VMINNM_fp_3s(DisasContext *s, arg_3same *a)
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return false;
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}
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if (a->size != 0) {
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if (a->size == MO_16) {
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if (!dc_isar_feature(aa32_fp16_arith, s)) {
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return false;
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}
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@ -1155,7 +1161,7 @@ static bool do_3same_fp_pair(DisasContext *s, arg_3same *a,
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assert(a->q == 0); /* enforced by decode patterns */
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fpstatus = fpstatus_ptr(tcg_ctx, a->size != 0 ? FPST_STD_F16 : FPST_STD);
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fpstatus = fpstatus_ptr(tcg_ctx, a->size == MO_16 ? FPST_STD_F16 : FPST_STD);
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tcg_gen_gvec_3_ptr(tcg_ctx, vfp_reg_offset(1, a->vd),
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vfp_reg_offset(1, a->vn),
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vfp_reg_offset(1, a->vm),
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@ -1172,7 +1178,7 @@ static bool do_3same_fp_pair(DisasContext *s, arg_3same *a,
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#define DO_3S_FP_PAIR(INSN,FUNC) \
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static bool trans_##INSN##_fp_3s(DisasContext *s, arg_3same *a) \
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{ \
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if (a->size != 0) { \
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if (a->size == MO_16) { \
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if (!dc_isar_feature(aa32_fp16_arith, s)) { \
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return false; \
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} \
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