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target/mips: Refactor and fix COPY_S.<B|H|W|D> instructions

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The old version of the helper for the COPY_S.<B|H|W|D> MSA instructions
has been replaced with four helpers that don't use switch, and change
the endianness of the given index, when executed on a big endian host.

Backports commit 631c467461496dcf6d6a3e4c3d27a1433e96868e from qemu
This commit is contained in:
Mateja Marjanovic 2019-05-28 19:35:52 -04:00 committed by Lioncash
parent 6dd651af3a
commit 54a33d1db3
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
8 changed files with 89 additions and 28 deletions
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5
qemu/header_gen.py
View file

@ -4972,7 +4972,10 @@ mips_symbols = (
'helper_msa_clt_u_df',
'helper_msa_clti_s_df',
'helper_msa_clti_u_df',
'helper_msa_copy_s_df',
'helper_msa_copy_s_b',
'helper_msa_copy_s_d',
'helper_msa_copy_s_h',
'helper_msa_copy_s_w',
'helper_msa_copy_u_df',
'helper_msa_ctcmsa',
'helper_msa_div_s_df',

5
qemu/mips.h
View file

@ -3860,7 +3860,10 @@
#define helper_msa_clt_u_df helper_msa_clt_u_df_mips
#define helper_msa_clti_s_df helper_msa_clti_s_df_mips
#define helper_msa_clti_u_df helper_msa_clti_u_df_mips
#define helper_msa_copy_s_df helper_msa_copy_s_df_mips
#define helper_msa_copy_s_b helper_msa_copy_s_b_mips
#define helper_msa_copy_s_d helper_msa_copy_s_d_mips
#define helper_msa_copy_s_h helper_msa_copy_s_h_mips
#define helper_msa_copy_s_w helper_msa_copy_s_w_mips
#define helper_msa_copy_u_df helper_msa_copy_u_df_mips
#define helper_msa_ctcmsa helper_msa_ctcmsa_mips
#define helper_msa_div_s_df helper_msa_div_s_df_mips

5
qemu/mips64.h
View file

@ -3860,7 +3860,10 @@
#define helper_msa_clt_u_df helper_msa_clt_u_df_mips64
#define helper_msa_clti_s_df helper_msa_clti_s_df_mips64
#define helper_msa_clti_u_df helper_msa_clti_u_df_mips64
#define helper_msa_copy_s_df helper_msa_copy_s_df_mips64
#define helper_msa_copy_s_b helper_msa_copy_s_b_mips64
#define helper_msa_copy_s_d helper_msa_copy_s_d_mips64
#define helper_msa_copy_s_h helper_msa_copy_s_h_mips64
#define helper_msa_copy_s_w helper_msa_copy_s_w_mips64
#define helper_msa_copy_u_df helper_msa_copy_u_df_mips64
#define helper_msa_ctcmsa helper_msa_ctcmsa_mips64
#define helper_msa_div_s_df helper_msa_div_s_df_mips64

5
qemu/mips64el.h
View file

@ -3860,7 +3860,10 @@
#define helper_msa_clt_u_df helper_msa_clt_u_df_mips64el
#define helper_msa_clti_s_df helper_msa_clti_s_df_mips64el
#define helper_msa_clti_u_df helper_msa_clti_u_df_mips64el
#define helper_msa_copy_s_df helper_msa_copy_s_df_mips64el
#define helper_msa_copy_s_b helper_msa_copy_s_b_mips64el
#define helper_msa_copy_s_d helper_msa_copy_s_d_mips64el
#define helper_msa_copy_s_h helper_msa_copy_s_h_mips64el
#define helper_msa_copy_s_w helper_msa_copy_s_w_mips64el
#define helper_msa_copy_u_df helper_msa_copy_u_df_mips64el
#define helper_msa_ctcmsa helper_msa_ctcmsa_mips64el
#define helper_msa_div_s_df helper_msa_div_s_df_mips64el

5
qemu/mipsel.h
View file

@ -3860,7 +3860,10 @@
#define helper_msa_clt_u_df helper_msa_clt_u_df_mipsel
#define helper_msa_clti_s_df helper_msa_clti_s_df_mipsel
#define helper_msa_clti_u_df helper_msa_clti_u_df_mipsel
#define helper_msa_copy_s_df helper_msa_copy_s_df_mipsel
#define helper_msa_copy_s_b helper_msa_copy_s_b_mipsel
#define helper_msa_copy_s_d helper_msa_copy_s_d_mipsel
#define helper_msa_copy_s_h helper_msa_copy_s_h_mipsel
#define helper_msa_copy_s_w helper_msa_copy_s_w_mipsel
#define helper_msa_copy_u_df helper_msa_copy_u_df_mipsel
#define helper_msa_ctcmsa helper_msa_ctcmsa_mipsel
#define helper_msa_div_s_df helper_msa_div_s_df_mipsel

7
qemu/target/mips/helper.h
View file

@ -876,7 +876,7 @@ DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_copy_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_copy_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_insert_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_insve_df, void, env, i32, i32, i32, i32)
@ -938,6 +938,11 @@ DEF_HELPER_4(msa_pcnt_df, void, env, i32, i32, i32)
DEF_HELPER_4(msa_nloc_df, void, env, i32, i32, i32)
DEF_HELPER_4(msa_nlzc_df, void, env, i32, i32, i32)
DEF_HELPER_4(msa_copy_s_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_copy_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_copy_s_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_copy_s_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_fclass_df, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ftrunc_s_df, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ftrunc_u_df, void, env, i32, i32, i32)

66
qemu/target/mips/msa_helper.c
View file

@ -1249,29 +1249,53 @@ void helper_msa_splati_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
msa_splat_df(df, pwd, pws, n);
}
void helper_msa_copy_s_df(CPUMIPSState *env, uint32_t df, uint32_t rd,
uint32_t ws, uint32_t n)
void helper_msa_copy_s_b(CPUMIPSState *env, uint32_t rd,
uint32_t ws, uint32_t n)
{
n %= DF_ELEMENTS(df);
switch (df) {
case DF_BYTE:
env->active_tc.gpr[rd] = (int8_t)env->active_fpu.fpr[ws].wr.b[n];
break;
case DF_HALF:
env->active_tc.gpr[rd] = (int16_t)env->active_fpu.fpr[ws].wr.h[n];
break;
case DF_WORD:
env->active_tc.gpr[rd] = (int32_t)env->active_fpu.fpr[ws].wr.w[n];
break;
#ifdef TARGET_MIPS64
case DF_DOUBLE:
env->active_tc.gpr[rd] = (int64_t)env->active_fpu.fpr[ws].wr.d[n];
break;
#endif
default:
assert(0);
n %= 16;
#if defined(HOST_WORDS_BIGENDIAN)
if (n < 8) {
n = 8 - n - 1;
} else {
n = 24 - n - 1;
}
#endif
env->active_tc.gpr[rd] = (int8_t)env->active_fpu.fpr[ws].wr.b[n];
}
void helper_msa_copy_s_h(CPUMIPSState *env, uint32_t rd,
uint32_t ws, uint32_t n)
{
n %= 8;
#if defined(HOST_WORDS_BIGENDIAN)
if (n < 4) {
n = 4 - n - 1;
} else {
n = 12 - n - 1;
}
#endif
env->active_tc.gpr[rd] = (int16_t)env->active_fpu.fpr[ws].wr.h[n];
}
void helper_msa_copy_s_w(CPUMIPSState *env, uint32_t rd,
uint32_t ws, uint32_t n)
{
n %= 4;
#if defined(HOST_WORDS_BIGENDIAN)
if (n < 2) {
n = 2 - n - 1;
} else {
n = 6 - n - 1;
}
#endif
env->active_tc.gpr[rd] = (int32_t)env->active_fpu.fpr[ws].wr.w[n];
}
void helper_msa_copy_s_d(CPUMIPSState *env, uint32_t rd,
uint32_t ws, uint32_t n)
{
n %= 2;
env->active_tc.gpr[rd] = (int64_t)env->active_fpu.fpr[ws].wr.d[n];
}
void helper_msa_copy_u_df(CPUMIPSState *env, uint32_t df, uint32_t rd,

19
qemu/target/mips/translate.c
View file

@ -28462,7 +28462,24 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df,
switch (MASK_MSA_ELM(ctx->opcode)) {
case OPC_COPY_S_df:
if (likely(wd != 0)) {
gen_helper_msa_copy_s_df(tcg_ctx, tcg_ctx->cpu_env, tdf, twd, tws, tn);
switch (df) {
case DF_BYTE:
gen_helper_msa_copy_s_b(tcg_ctx, tcg_ctx->cpu_env, twd, tws, tn);
break;
case DF_HALF:
gen_helper_msa_copy_s_h(tcg_ctx, tcg_ctx->cpu_env, twd, tws, tn);
break;
case DF_WORD:
gen_helper_msa_copy_s_w(tcg_ctx, tcg_ctx->cpu_env, twd, tws, tn);
break;
#if defined(TARGET_MIPS64)
case DF_DOUBLE:
gen_helper_msa_copy_s_d(tcg_ctx, tcg_ctx->cpu_env, twd, tws, tn);
break;
#endif
default:
assert(0);
}
}
break;
case OPC_COPY_U_df: