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armv7m: Raise correct kind of UsageFault for attempts to execute ARM code

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M profile doesn't implement ARM, and the architecturally required
behaviour for attempts to execute with the Thumb bit clear is to
generate a UsageFault with the CFSR INVSTATE bit set. We were
incorrectly implementing this as generating an UNDEFINSTR UsageFault;
fix this.

Backports commit e13886e3a790b52f0b2e93cb5e84fdc2ada5471a from qemu
This commit is contained in:
Peter Maydell 2018-03-02 20:00:56 -05:00 committed by Lioncash
parent fbfeca93b3
commit 565626ca63
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 10 additions and 2 deletions
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4
qemu/target/arm/helper.c
View file

@ -5598,6 +5598,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs)
//armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE); //armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
env->v7m.cfsr |= R_V7M_CFSR_NOCP_MASK; env->v7m.cfsr |= R_V7M_CFSR_NOCP_MASK;
break; break;
case EXCP_INVSTATE:
//armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
env->v7m.cfsr |= R_V7M_CFSR_INVSTATE_MASK;
break;
case EXCP_SWI: case EXCP_SWI:
/* The PC already points to the next instruction. */ /* The PC already points to the next instruction. */
//armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC); //armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);

8
qemu/target/arm/translate.c
View file

@ -8218,9 +8218,13 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) // qq
TCGv_i32 addr; TCGv_i32 addr;
TCGv_i64 tmp64; TCGv_i64 tmp64;
/* M variants do not implement ARM mode. */ /* M variants do not implement ARM mode; this must raise the INVSTATE
* UsageFault exception.
*/
if (arm_dc_feature(s, ARM_FEATURE_M)) { if (arm_dc_feature(s, ARM_FEATURE_M)) {
goto illegal_op; gen_exception_insn(s, 4, EXCP_INVSTATE, syn_uncategorized(),
default_exception_el(s));
return;
} }
// Unicorn: trace this instruction on request // Unicorn: trace this instruction on request