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tcg/s390: Make direct jump patching thread-safe
Ensure direct jump patching in s390 is atomic by: * naturally aligning a location of direct jump address; * using atomic_read()/atomic_set() for code patching. Backports commit ed3d51ecd7fe248d3959e469d53890ac9ffe0cd2 from qemu
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@ -315,7 +315,7 @@ static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr)
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{
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{
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/* patch the branch destination */
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/* patch the branch destination */
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intptr_t disp = addr - (jmp_addr - 2);
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intptr_t disp = addr - (jmp_addr - 2);
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stl_be_p((void*)jmp_addr, disp / 2);
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atomic_set((int32_t *)jmp_addr, disp / 2);
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/* no need to flush icache explicitly */
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/* no need to flush icache explicitly */
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}
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}
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#elif defined(__aarch64__)
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#elif defined(__aarch64__)
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@ -224,6 +224,8 @@ typedef enum S390Opcode {
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RX_ST = 0x50,
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RX_ST = 0x50,
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RX_STC = 0x42,
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RX_STC = 0x42,
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RX_STH = 0x40,
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RX_STH = 0x40,
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NOP = 0x0707,
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} S390Opcode;
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} S390Opcode;
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#ifdef CONFIG_DEBUG_TCG
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#ifdef CONFIG_DEBUG_TCG
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@ -1721,6 +1723,12 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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case INDEX_op_goto_tb:
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case INDEX_op_goto_tb:
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if (s->tb_jmp_offset) {
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if (s->tb_jmp_offset) {
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/* branch displacement must be aligned for atomic patching;
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* see if we need to add extra nop before branch
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*/
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if (!(void*)QEMU_PTR_IS_ALIGNED(s->code_ptr + 1, 4)) {
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tcg_out16(s, NOP);
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}
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tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4));
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tcg_out16(s, RIL_BRCL | (S390_CC_ALWAYS << 4));
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s->tb_jmp_offset[args[0]] = tcg_current_code_size(s);
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s->tb_jmp_offset[args[0]] = tcg_current_code_size(s);
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s->code_ptr += 2;
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s->code_ptr += 2;
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