mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2024-12-23 00:35:34 +00:00
tcg: Add generic vector ops for constant shifts
Opcodes are added for scalar and vector shifts, but considering the varied semantics of these do not expose them to the front ends. Do go ahead and provide them in case they are needed for backend expansion. Backports commit d0ec97967f940bbc11dced83422b39c224127f1e from qemu
This commit is contained in:
Richard Henderson
Lioncash
parent
64365612bf
commit
577ee114c3
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@ -1627,6 +1627,18 @@
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#define helper_gvec_not helper_gvec_not_aarch64
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#define helper_gvec_or helper_gvec_or_aarch64
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#define helper_gvec_orc helper_gvec_orc_aarch64
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#define helper_gvec_sar8i helper_gvec_sar8i_aarch64
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#define helper_gvec_sar16i helper_gvec_sar16i_aarch64
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#define helper_gvec_sar32i helper_gvec_sar32i_aarch64
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#define helper_gvec_sar64i helper_gvec_sar64i_aarch64
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#define helper_gvec_shl8i helper_gvec_shl8i_aarch64
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#define helper_gvec_shl16i helper_gvec_shl16i_aarch64
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#define helper_gvec_shl32i helper_gvec_shl32i_aarch64
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#define helper_gvec_shl64i helper_gvec_shl64i_aarch64
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#define helper_gvec_shr8i helper_gvec_shr8i_aarch64
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#define helper_gvec_shr16i helper_gvec_shr16i_aarch64
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#define helper_gvec_shr32i helper_gvec_shr32i_aarch64
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#define helper_gvec_shr64i helper_gvec_shr64i_aarch64
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#define helper_gvec_sub8 helper_gvec_sub8_aarch64
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#define helper_gvec_sub16 helper_gvec_sub16_aarch64
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#define helper_gvec_sub32 helper_gvec_sub32_aarch64
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@ -3114,6 +3126,7 @@
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#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_aarch64
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#define tcg_gen_goto_tb tcg_gen_goto_tb_aarch64
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#define tcg_gen_gvec_2 tcg_gen_gvec_2_aarch64
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#define tcg_gen_gvec_2i tcg_gen_gvec_2i_aarch64
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#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_aarch64
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#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_aarch64
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#define tcg_gen_gvec_3 tcg_gen_gvec_3_aarch64
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@ -3138,6 +3151,9 @@
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#define tcg_gen_gvec_not tcg_gen_gvec_not_aarch64
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#define tcg_gen_gvec_or tcg_gen_gvec_or_aarch64
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#define tcg_gen_gvec_orc tcg_gen_gvec_orc_aarch64
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#define tcg_gen_gvec_sari tcg_gen_gvec_sari_aarch64
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#define tcg_gen_gvec_shli tcg_gen_gvec_shli_aarch64
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#define tcg_gen_gvec_shri tcg_gen_gvec_shri_aarch64
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#define tcg_gen_gvec_sub tcg_gen_gvec_sub_aarch64
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#define tcg_gen_gvec_xor tcg_gen_gvec_xor_aarch64
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#define tcg_gen_insn_start tcg_gen_insn_start_aarch64
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@ -3231,6 +3247,7 @@
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#define tcg_gen_sar_i64 tcg_gen_sar_i64_aarch64
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#define tcg_gen_sari_i32 tcg_gen_sari_i32_aarch64
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#define tcg_gen_sari_i64 tcg_gen_sari_i64_aarch64
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#define tcg_gen_sari_vec tcg_gen_sari_vec_aarch64
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#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_aarch64
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#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_aarch64
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#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_aarch64
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@ -3242,10 +3259,12 @@
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#define tcg_gen_shl_i64 tcg_gen_shl_i64_aarch64
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#define tcg_gen_shli_i32 tcg_gen_shli_i32_aarch64
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#define tcg_gen_shli_i64 tcg_gen_shli_i64_aarch64
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#define tcg_gen_shli_vec tcg_gen_shli_vec_aarch64
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#define tcg_gen_shr_i32 tcg_gen_shr_i32_aarch64
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#define tcg_gen_shr_i64 tcg_gen_shr_i64_aarch64
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#define tcg_gen_shri_i32 tcg_gen_shri_i32_aarch64
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#define tcg_gen_shri_i64 tcg_gen_shri_i64_aarch64
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#define tcg_gen_shri_vec tcg_gen_shri_vec_aarch64
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#define tcg_gen_st_i32 tcg_gen_st_i32_aarch64
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#define tcg_gen_st_i64 tcg_gen_st_i64_aarch64
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#define tcg_gen_st_vec tcg_gen_st_vec_aarch64
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@ -3265,6 +3284,12 @@
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#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_aarch64
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#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_aarch64
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#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_aarch64
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#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_aarch64
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#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_aarch64
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#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_aarch64
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#define tcg_gen_vec_shl16i_i64 tcg_gen_vec_shl16i_i64_aarch64
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#define tcg_gen_vec_shr8i_i64 tcg_gen_vec_shr8i_i64_aarch64
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#define tcg_gen_vec_shr16i_i64 tcg_gen_vec_shr16i_i64_aarch64
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#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_aarch64
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#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_aarch64
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#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_aarch64
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@ -1627,6 +1627,18 @@
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#define helper_gvec_not helper_gvec_not_aarch64eb
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#define helper_gvec_or helper_gvec_or_aarch64eb
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#define helper_gvec_orc helper_gvec_orc_aarch64eb
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#define helper_gvec_sar8i helper_gvec_sar8i_aarch64eb
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#define helper_gvec_sar16i helper_gvec_sar16i_aarch64eb
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#define helper_gvec_sar32i helper_gvec_sar32i_aarch64eb
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#define helper_gvec_sar64i helper_gvec_sar64i_aarch64eb
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#define helper_gvec_shl8i helper_gvec_shl8i_aarch64eb
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#define helper_gvec_shl16i helper_gvec_shl16i_aarch64eb
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#define helper_gvec_shl32i helper_gvec_shl32i_aarch64eb
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#define helper_gvec_shl64i helper_gvec_shl64i_aarch64eb
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#define helper_gvec_shr8i helper_gvec_shr8i_aarch64eb
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#define helper_gvec_shr16i helper_gvec_shr16i_aarch64eb
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#define helper_gvec_shr32i helper_gvec_shr32i_aarch64eb
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#define helper_gvec_shr64i helper_gvec_shr64i_aarch64eb
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#define helper_gvec_sub8 helper_gvec_sub8_aarch64eb
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#define helper_gvec_sub16 helper_gvec_sub16_aarch64eb
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#define helper_gvec_sub32 helper_gvec_sub32_aarch64eb
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@ -3114,6 +3126,7 @@
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#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_aarch64eb
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#define tcg_gen_goto_tb tcg_gen_goto_tb_aarch64eb
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#define tcg_gen_gvec_2 tcg_gen_gvec_2_aarch64eb
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#define tcg_gen_gvec_2i tcg_gen_gvec_2i_aarch64eb
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#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_aarch64eb
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#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_aarch64eb
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#define tcg_gen_gvec_3 tcg_gen_gvec_3_aarch64eb
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@ -3138,6 +3151,9 @@
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#define tcg_gen_gvec_not tcg_gen_gvec_not_aarch64eb
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#define tcg_gen_gvec_or tcg_gen_gvec_or_aarch64eb
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#define tcg_gen_gvec_orc tcg_gen_gvec_orc_aarch64eb
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#define tcg_gen_gvec_sari tcg_gen_gvec_sari_aarch64eb
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#define tcg_gen_gvec_shli tcg_gen_gvec_shli_aarch64eb
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#define tcg_gen_gvec_shri tcg_gen_gvec_shri_aarch64eb
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#define tcg_gen_gvec_sub tcg_gen_gvec_sub_aarch64eb
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#define tcg_gen_gvec_xor tcg_gen_gvec_xor_aarch64eb
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#define tcg_gen_insn_start tcg_gen_insn_start_aarch64eb
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@ -3231,6 +3247,7 @@
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#define tcg_gen_sar_i64 tcg_gen_sar_i64_aarch64eb
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#define tcg_gen_sari_i32 tcg_gen_sari_i32_aarch64eb
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#define tcg_gen_sari_i64 tcg_gen_sari_i64_aarch64eb
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#define tcg_gen_sari_vec tcg_gen_sari_vec_aarch64eb
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#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_aarch64eb
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#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_aarch64eb
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#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_aarch64eb
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@ -3242,10 +3259,12 @@
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#define tcg_gen_shl_i64 tcg_gen_shl_i64_aarch64eb
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#define tcg_gen_shli_i32 tcg_gen_shli_i32_aarch64eb
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#define tcg_gen_shli_i64 tcg_gen_shli_i64_aarch64eb
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#define tcg_gen_shli_vec tcg_gen_shli_vec_aarch64eb
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#define tcg_gen_shr_i32 tcg_gen_shr_i32_aarch64eb
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#define tcg_gen_shr_i64 tcg_gen_shr_i64_aarch64eb
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#define tcg_gen_shri_i32 tcg_gen_shri_i32_aarch64eb
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#define tcg_gen_shri_i64 tcg_gen_shri_i64_aarch64eb
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#define tcg_gen_shri_vec tcg_gen_shri_vec_aarch64eb
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#define tcg_gen_st_i32 tcg_gen_st_i32_aarch64eb
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#define tcg_gen_st_i64 tcg_gen_st_i64_aarch64eb
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#define tcg_gen_st_vec tcg_gen_st_vec_aarch64eb
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#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_aarch64eb
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#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_aarch64eb
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#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_aarch64eb
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#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_aarch64eb
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#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_aarch64eb
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#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_aarch64eb
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#define tcg_gen_vec_shl16i_i64 tcg_gen_vec_shl16i_i64_aarch64eb
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#define tcg_gen_vec_shr8i_i64 tcg_gen_vec_shr8i_i64_aarch64eb
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#define tcg_gen_vec_shr16i_i64 tcg_gen_vec_shr16i_i64_aarch64eb
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#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_aarch64eb
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#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_aarch64eb
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#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_aarch64eb
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25
qemu/arm.h
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qemu/arm.h
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@ -1627,6 +1627,18 @@
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#define helper_gvec_not helper_gvec_not_arm
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#define helper_gvec_or helper_gvec_or_arm
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#define helper_gvec_orc helper_gvec_orc_arm
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#define helper_gvec_sar8i helper_gvec_sar8i_arm
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#define helper_gvec_sar16i helper_gvec_sar16i_arm
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#define helper_gvec_sar32i helper_gvec_sar32i_arm
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#define helper_gvec_sar64i helper_gvec_sar64i_arm
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#define helper_gvec_shl8i helper_gvec_shl8i_arm
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#define helper_gvec_shl16i helper_gvec_shl16i_arm
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#define helper_gvec_shl32i helper_gvec_shl32i_arm
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#define helper_gvec_shl64i helper_gvec_shl64i_arm
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#define helper_gvec_shr8i helper_gvec_shr8i_arm
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#define helper_gvec_shr16i helper_gvec_shr16i_arm
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#define helper_gvec_shr32i helper_gvec_shr32i_arm
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#define helper_gvec_shr64i helper_gvec_shr64i_arm
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#define helper_gvec_sub8 helper_gvec_sub8_arm
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#define helper_gvec_sub16 helper_gvec_sub16_arm
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#define helper_gvec_sub32 helper_gvec_sub32_arm
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#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_arm
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#define tcg_gen_goto_tb tcg_gen_goto_tb_arm
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#define tcg_gen_gvec_2 tcg_gen_gvec_2_arm
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#define tcg_gen_gvec_2i tcg_gen_gvec_2i_arm
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#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_arm
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#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_arm
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#define tcg_gen_gvec_3 tcg_gen_gvec_3_arm
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#define tcg_gen_gvec_not tcg_gen_gvec_not_arm
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#define tcg_gen_gvec_or tcg_gen_gvec_or_arm
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#define tcg_gen_gvec_orc tcg_gen_gvec_orc_arm
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#define tcg_gen_gvec_sari tcg_gen_gvec_sari_arm
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#define tcg_gen_gvec_shli tcg_gen_gvec_shli_arm
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#define tcg_gen_gvec_shri tcg_gen_gvec_shri_arm
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#define tcg_gen_gvec_sub tcg_gen_gvec_sub_arm
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#define tcg_gen_gvec_xor tcg_gen_gvec_xor_arm
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#define tcg_gen_insn_start tcg_gen_insn_start_arm
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#define tcg_gen_sar_i64 tcg_gen_sar_i64_arm
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#define tcg_gen_sari_i32 tcg_gen_sari_i32_arm
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#define tcg_gen_sari_i64 tcg_gen_sari_i64_arm
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#define tcg_gen_sari_vec tcg_gen_sari_vec_arm
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#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_arm
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#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_arm
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#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_arm
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#define tcg_gen_shl_i64 tcg_gen_shl_i64_arm
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#define tcg_gen_shli_i32 tcg_gen_shli_i32_arm
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#define tcg_gen_shli_i64 tcg_gen_shli_i64_arm
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#define tcg_gen_shli_vec tcg_gen_shli_vec_arm
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#define tcg_gen_shr_i32 tcg_gen_shr_i32_arm
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#define tcg_gen_shr_i64 tcg_gen_shr_i64_arm
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#define tcg_gen_shri_i32 tcg_gen_shri_i32_arm
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#define tcg_gen_shri_i64 tcg_gen_shri_i64_arm
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#define tcg_gen_shri_vec tcg_gen_shri_vec_arm
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#define tcg_gen_st_i32 tcg_gen_st_i32_arm
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#define tcg_gen_st_i64 tcg_gen_st_i64_arm
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#define tcg_gen_st_vec tcg_gen_st_vec_arm
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#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_arm
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#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_arm
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#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_arm
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#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_arm
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#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_arm
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#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_arm
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#define tcg_gen_vec_shl16i_i64 tcg_gen_vec_shl16i_i64_arm
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#define tcg_gen_vec_shr8i_i64 tcg_gen_vec_shr8i_i64_arm
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#define tcg_gen_vec_shr16i_i64 tcg_gen_vec_shr16i_i64_arm
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#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_arm
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#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_arm
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#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_arm
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25
qemu/armeb.h
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qemu/armeb.h
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#define helper_gvec_not helper_gvec_not_armeb
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#define helper_gvec_or helper_gvec_or_armeb
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#define helper_gvec_orc helper_gvec_orc_armeb
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#define helper_gvec_sar8i helper_gvec_sar8i_armeb
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#define helper_gvec_sar16i helper_gvec_sar16i_armeb
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#define helper_gvec_sar32i helper_gvec_sar32i_armeb
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#define helper_gvec_sar64i helper_gvec_sar64i_armeb
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#define helper_gvec_shl8i helper_gvec_shl8i_armeb
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#define helper_gvec_shl16i helper_gvec_shl16i_armeb
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#define helper_gvec_shl32i helper_gvec_shl32i_armeb
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#define helper_gvec_shl64i helper_gvec_shl64i_armeb
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#define helper_gvec_shr8i helper_gvec_shr8i_armeb
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#define helper_gvec_shr16i helper_gvec_shr16i_armeb
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#define helper_gvec_shr32i helper_gvec_shr32i_armeb
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#define helper_gvec_shr64i helper_gvec_shr64i_armeb
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#define helper_gvec_sub8 helper_gvec_sub8_armeb
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#define helper_gvec_sub16 helper_gvec_sub16_armeb
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#define helper_gvec_sub32 helper_gvec_sub32_armeb
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#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_armeb
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#define tcg_gen_goto_tb tcg_gen_goto_tb_armeb
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#define tcg_gen_gvec_2 tcg_gen_gvec_2_armeb
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#define tcg_gen_gvec_2i tcg_gen_gvec_2i_armeb
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#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_armeb
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#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_armeb
|
||||
#define tcg_gen_gvec_3 tcg_gen_gvec_3_armeb
|
||||
|
|
@ -3138,6 +3151,9 @@
|
|||
#define tcg_gen_gvec_not tcg_gen_gvec_not_armeb
|
||||
#define tcg_gen_gvec_or tcg_gen_gvec_or_armeb
|
||||
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_armeb
|
||||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_armeb
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_armeb
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_armeb
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_armeb
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_armeb
|
||||
#define tcg_gen_insn_start tcg_gen_insn_start_armeb
|
||||
|
|
@ -3231,6 +3247,7 @@
|
|||
#define tcg_gen_sar_i64 tcg_gen_sar_i64_armeb
|
||||
#define tcg_gen_sari_i32 tcg_gen_sari_i32_armeb
|
||||
#define tcg_gen_sari_i64 tcg_gen_sari_i64_armeb
|
||||
#define tcg_gen_sari_vec tcg_gen_sari_vec_armeb
|
||||
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_armeb
|
||||
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_armeb
|
||||
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_armeb
|
||||
|
|
@ -3242,10 +3259,12 @@
|
|||
#define tcg_gen_shl_i64 tcg_gen_shl_i64_armeb
|
||||
#define tcg_gen_shli_i32 tcg_gen_shli_i32_armeb
|
||||
#define tcg_gen_shli_i64 tcg_gen_shli_i64_armeb
|
||||
#define tcg_gen_shli_vec tcg_gen_shli_vec_armeb
|
||||
#define tcg_gen_shr_i32 tcg_gen_shr_i32_armeb
|
||||
#define tcg_gen_shr_i64 tcg_gen_shr_i64_armeb
|
||||
#define tcg_gen_shri_i32 tcg_gen_shri_i32_armeb
|
||||
#define tcg_gen_shri_i64 tcg_gen_shri_i64_armeb
|
||||
#define tcg_gen_shri_vec tcg_gen_shri_vec_armeb
|
||||
#define tcg_gen_st_i32 tcg_gen_st_i32_armeb
|
||||
#define tcg_gen_st_i64 tcg_gen_st_i64_armeb
|
||||
#define tcg_gen_st_vec tcg_gen_st_vec_armeb
|
||||
|
|
@ -3265,6 +3284,12 @@
|
|||
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_armeb
|
||||
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_armeb
|
||||
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_armeb
|
||||
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_armeb
|
||||
#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_armeb
|
||||
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_armeb
|
||||
#define tcg_gen_vec_shl16i_i64 tcg_gen_vec_shl16i_i64_armeb
|
||||
#define tcg_gen_vec_shr8i_i64 tcg_gen_vec_shr8i_i64_armeb
|
||||
#define tcg_gen_vec_shr16i_i64 tcg_gen_vec_shr16i_i64_armeb
|
||||
#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_armeb
|
||||
#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_armeb
|
||||
#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_armeb
|
||||
|
|
|
|||
|
|
@ -1633,6 +1633,18 @@ symbols = (
|
|||
'helper_gvec_not',
|
||||
'helper_gvec_or',
|
||||
'helper_gvec_orc',
|
||||
'helper_gvec_sar8i',
|
||||
'helper_gvec_sar16i',
|
||||
'helper_gvec_sar32i',
|
||||
'helper_gvec_sar64i',
|
||||
'helper_gvec_shl8i',
|
||||
'helper_gvec_shl16i',
|
||||
'helper_gvec_shl32i',
|
||||
'helper_gvec_shl64i',
|
||||
'helper_gvec_shr8i',
|
||||
'helper_gvec_shr16i',
|
||||
'helper_gvec_shr32i',
|
||||
'helper_gvec_shr64i',
|
||||
'helper_gvec_sub8',
|
||||
'helper_gvec_sub16',
|
||||
'helper_gvec_sub32',
|
||||
|
|
@ -3120,6 +3132,7 @@ symbols = (
|
|||
'tcg_gen_extu_i32_i64',
|
||||
'tcg_gen_goto_tb',
|
||||
'tcg_gen_gvec_2',
|
||||
'tcg_gen_gvec_2i',
|
||||
'tcg_gen_gvec_2_ool',
|
||||
'tcg_gen_gvec_2_ptr',
|
||||
'tcg_gen_gvec_3',
|
||||
|
|
@ -3144,6 +3157,9 @@ symbols = (
|
|||
'tcg_gen_gvec_not',
|
||||
'tcg_gen_gvec_or',
|
||||
'tcg_gen_gvec_orc',
|
||||
'tcg_gen_gvec_sari',
|
||||
'tcg_gen_gvec_shli',
|
||||
'tcg_gen_gvec_shri',
|
||||
'tcg_gen_gvec_sub',
|
||||
'tcg_gen_gvec_xor',
|
||||
'tcg_gen_insn_start',
|
||||
|
|
@ -3237,6 +3253,7 @@ symbols = (
|
|||
'tcg_gen_sar_i64',
|
||||
'tcg_gen_sari_i32',
|
||||
'tcg_gen_sari_i64',
|
||||
'tcg_gen_sari_vec',
|
||||
'tcg_gen_setcond_i32',
|
||||
'tcg_gen_setcond_i64',
|
||||
'tcg_gen_setcondi_i32',
|
||||
|
|
@ -3248,10 +3265,12 @@ symbols = (
|
|||
'tcg_gen_shl_i64',
|
||||
'tcg_gen_shli_i32',
|
||||
'tcg_gen_shli_i64',
|
||||
'tcg_gen_shli_vec',
|
||||
'tcg_gen_shr_i32',
|
||||
'tcg_gen_shr_i64',
|
||||
'tcg_gen_shri_i32',
|
||||
'tcg_gen_shri_i64',
|
||||
'tcg_gen_shri_vec',
|
||||
'tcg_gen_st_i32',
|
||||
'tcg_gen_st_i64',
|
||||
'tcg_gen_st_vec',
|
||||
|
|
@ -3271,6 +3290,12 @@ symbols = (
|
|||
'tcg_gen_vec_neg8_i64',
|
||||
'tcg_gen_vec_neg16_i64',
|
||||
'tcg_gen_vec_neg32_i64',
|
||||
'tcg_gen_vec_sar8i_i64',
|
||||
'tcg_gen_vec_sar16i_i64',
|
||||
'tcg_gen_vec_shl8i_i64',
|
||||
'tcg_gen_vec_shl16i_i64',
|
||||
'tcg_gen_vec_shr8i_i64',
|
||||
'tcg_gen_vec_shr16i_i64',
|
||||
'tcg_gen_vec_sub8_i64',
|
||||
'tcg_gen_vec_sub16_i64',
|
||||
'tcg_gen_vec_sub32_i64',
|
||||
|
|
|
|||
25
qemu/m68k.h
25
qemu/m68k.h
|
|
@ -1627,6 +1627,18 @@
|
|||
#define helper_gvec_not helper_gvec_not_m68k
|
||||
#define helper_gvec_or helper_gvec_or_m68k
|
||||
#define helper_gvec_orc helper_gvec_orc_m68k
|
||||
#define helper_gvec_sar8i helper_gvec_sar8i_m68k
|
||||
#define helper_gvec_sar16i helper_gvec_sar16i_m68k
|
||||
#define helper_gvec_sar32i helper_gvec_sar32i_m68k
|
||||
#define helper_gvec_sar64i helper_gvec_sar64i_m68k
|
||||
#define helper_gvec_shl8i helper_gvec_shl8i_m68k
|
||||
#define helper_gvec_shl16i helper_gvec_shl16i_m68k
|
||||
#define helper_gvec_shl32i helper_gvec_shl32i_m68k
|
||||
#define helper_gvec_shl64i helper_gvec_shl64i_m68k
|
||||
#define helper_gvec_shr8i helper_gvec_shr8i_m68k
|
||||
#define helper_gvec_shr16i helper_gvec_shr16i_m68k
|
||||
#define helper_gvec_shr32i helper_gvec_shr32i_m68k
|
||||
#define helper_gvec_shr64i helper_gvec_shr64i_m68k
|
||||
#define helper_gvec_sub8 helper_gvec_sub8_m68k
|
||||
#define helper_gvec_sub16 helper_gvec_sub16_m68k
|
||||
#define helper_gvec_sub32 helper_gvec_sub32_m68k
|
||||
|
|
@ -3114,6 +3126,7 @@
|
|||
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_m68k
|
||||
#define tcg_gen_goto_tb tcg_gen_goto_tb_m68k
|
||||
#define tcg_gen_gvec_2 tcg_gen_gvec_2_m68k
|
||||
#define tcg_gen_gvec_2i tcg_gen_gvec_2i_m68k
|
||||
#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_m68k
|
||||
#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_m68k
|
||||
#define tcg_gen_gvec_3 tcg_gen_gvec_3_m68k
|
||||
|
|
@ -3138,6 +3151,9 @@
|
|||
#define tcg_gen_gvec_not tcg_gen_gvec_not_m68k
|
||||
#define tcg_gen_gvec_or tcg_gen_gvec_or_m68k
|
||||
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_m68k
|
||||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_m68k
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_m68k
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_m68k
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_m68k
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_m68k
|
||||
#define tcg_gen_insn_start tcg_gen_insn_start_m68k
|
||||
|
|
@ -3231,6 +3247,7 @@
|
|||
#define tcg_gen_sar_i64 tcg_gen_sar_i64_m68k
|
||||
#define tcg_gen_sari_i32 tcg_gen_sari_i32_m68k
|
||||
#define tcg_gen_sari_i64 tcg_gen_sari_i64_m68k
|
||||
#define tcg_gen_sari_vec tcg_gen_sari_vec_m68k
|
||||
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_m68k
|
||||
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_m68k
|
||||
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_m68k
|
||||
|
|
@ -3242,10 +3259,12 @@
|
|||
#define tcg_gen_shl_i64 tcg_gen_shl_i64_m68k
|
||||
#define tcg_gen_shli_i32 tcg_gen_shli_i32_m68k
|
||||
#define tcg_gen_shli_i64 tcg_gen_shli_i64_m68k
|
||||
#define tcg_gen_shli_vec tcg_gen_shli_vec_m68k
|
||||
#define tcg_gen_shr_i32 tcg_gen_shr_i32_m68k
|
||||
#define tcg_gen_shr_i64 tcg_gen_shr_i64_m68k
|
||||
#define tcg_gen_shri_i32 tcg_gen_shri_i32_m68k
|
||||
#define tcg_gen_shri_i64 tcg_gen_shri_i64_m68k
|
||||
#define tcg_gen_shri_vec tcg_gen_shri_vec_m68k
|
||||
#define tcg_gen_st_i32 tcg_gen_st_i32_m68k
|
||||
#define tcg_gen_st_i64 tcg_gen_st_i64_m68k
|
||||
#define tcg_gen_st_vec tcg_gen_st_vec_m68k
|
||||
|
|
@ -3265,6 +3284,12 @@
|
|||
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_m68k
|
||||
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_m68k
|
||||
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_m68k
|
||||
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_m68k
|
||||
#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_m68k
|
||||
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_m68k
|
||||
#define tcg_gen_vec_shl16i_i64 tcg_gen_vec_shl16i_i64_m68k
|
||||
#define tcg_gen_vec_shr8i_i64 tcg_gen_vec_shr8i_i64_m68k
|
||||
#define tcg_gen_vec_shr16i_i64 tcg_gen_vec_shr16i_i64_m68k
|
||||
#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_m68k
|
||||
#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_m68k
|
||||
#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_m68k
|
||||
|
|
|
|||
25
qemu/mips.h
25
qemu/mips.h
|
|
@ -1627,6 +1627,18 @@
|
|||
#define helper_gvec_not helper_gvec_not_mips
|
||||
#define helper_gvec_or helper_gvec_or_mips
|
||||
#define helper_gvec_orc helper_gvec_orc_mips
|
||||
#define helper_gvec_sar8i helper_gvec_sar8i_mips
|
||||
#define helper_gvec_sar16i helper_gvec_sar16i_mips
|
||||
#define helper_gvec_sar32i helper_gvec_sar32i_mips
|
||||
#define helper_gvec_sar64i helper_gvec_sar64i_mips
|
||||
#define helper_gvec_shl8i helper_gvec_shl8i_mips
|
||||
#define helper_gvec_shl16i helper_gvec_shl16i_mips
|
||||
#define helper_gvec_shl32i helper_gvec_shl32i_mips
|
||||
#define helper_gvec_shl64i helper_gvec_shl64i_mips
|
||||
#define helper_gvec_shr8i helper_gvec_shr8i_mips
|
||||
#define helper_gvec_shr16i helper_gvec_shr16i_mips
|
||||
#define helper_gvec_shr32i helper_gvec_shr32i_mips
|
||||
#define helper_gvec_shr64i helper_gvec_shr64i_mips
|
||||
#define helper_gvec_sub8 helper_gvec_sub8_mips
|
||||
#define helper_gvec_sub16 helper_gvec_sub16_mips
|
||||
#define helper_gvec_sub32 helper_gvec_sub32_mips
|
||||
|
|
@ -3114,6 +3126,7 @@
|
|||
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mips
|
||||
#define tcg_gen_goto_tb tcg_gen_goto_tb_mips
|
||||
#define tcg_gen_gvec_2 tcg_gen_gvec_2_mips
|
||||
#define tcg_gen_gvec_2i tcg_gen_gvec_2i_mips
|
||||
#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_mips
|
||||
#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_mips
|
||||
#define tcg_gen_gvec_3 tcg_gen_gvec_3_mips
|
||||
|
|
@ -3138,6 +3151,9 @@
|
|||
#define tcg_gen_gvec_not tcg_gen_gvec_not_mips
|
||||
#define tcg_gen_gvec_or tcg_gen_gvec_or_mips
|
||||
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_mips
|
||||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_mips
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_mips
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_mips
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_mips
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_mips
|
||||
#define tcg_gen_insn_start tcg_gen_insn_start_mips
|
||||
|
|
@ -3231,6 +3247,7 @@
|
|||
#define tcg_gen_sar_i64 tcg_gen_sar_i64_mips
|
||||
#define tcg_gen_sari_i32 tcg_gen_sari_i32_mips
|
||||
#define tcg_gen_sari_i64 tcg_gen_sari_i64_mips
|
||||
#define tcg_gen_sari_vec tcg_gen_sari_vec_mips
|
||||
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_mips
|
||||
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mips
|
||||
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_mips
|
||||
|
|
@ -3242,10 +3259,12 @@
|
|||
#define tcg_gen_shl_i64 tcg_gen_shl_i64_mips
|
||||
#define tcg_gen_shli_i32 tcg_gen_shli_i32_mips
|
||||
#define tcg_gen_shli_i64 tcg_gen_shli_i64_mips
|
||||
#define tcg_gen_shli_vec tcg_gen_shli_vec_mips
|
||||
#define tcg_gen_shr_i32 tcg_gen_shr_i32_mips
|
||||
#define tcg_gen_shr_i64 tcg_gen_shr_i64_mips
|
||||
#define tcg_gen_shri_i32 tcg_gen_shri_i32_mips
|
||||
#define tcg_gen_shri_i64 tcg_gen_shri_i64_mips
|
||||
#define tcg_gen_shri_vec tcg_gen_shri_vec_mips
|
||||
#define tcg_gen_st_i32 tcg_gen_st_i32_mips
|
||||
#define tcg_gen_st_i64 tcg_gen_st_i64_mips
|
||||
#define tcg_gen_st_vec tcg_gen_st_vec_mips
|
||||
|
|
@ -3265,6 +3284,12 @@
|
|||
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_mips
|
||||
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_mips
|
||||
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_mips
|
||||
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_mips
|
||||
#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_mips
|
||||
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_mips
|
||||
#define tcg_gen_vec_shl16i_i64 tcg_gen_vec_shl16i_i64_mips
|
||||
#define tcg_gen_vec_shr8i_i64 tcg_gen_vec_shr8i_i64_mips
|
||||
#define tcg_gen_vec_shr16i_i64 tcg_gen_vec_shr16i_i64_mips
|
||||
#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_mips
|
||||
#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_mips
|
||||
#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_mips
|
||||
|
|
|
|||
|
|
@ -1627,6 +1627,18 @@
|
|||
#define helper_gvec_not helper_gvec_not_mips64
|
||||
#define helper_gvec_or helper_gvec_or_mips64
|
||||
#define helper_gvec_orc helper_gvec_orc_mips64
|
||||
#define helper_gvec_sar8i helper_gvec_sar8i_mips64
|
||||
#define helper_gvec_sar16i helper_gvec_sar16i_mips64
|
||||
#define helper_gvec_sar32i helper_gvec_sar32i_mips64
|
||||
#define helper_gvec_sar64i helper_gvec_sar64i_mips64
|
||||
#define helper_gvec_shl8i helper_gvec_shl8i_mips64
|
||||
#define helper_gvec_shl16i helper_gvec_shl16i_mips64
|
||||
#define helper_gvec_shl32i helper_gvec_shl32i_mips64
|
||||
#define helper_gvec_shl64i helper_gvec_shl64i_mips64
|
||||
#define helper_gvec_shr8i helper_gvec_shr8i_mips64
|
||||
#define helper_gvec_shr16i helper_gvec_shr16i_mips64
|
||||
#define helper_gvec_shr32i helper_gvec_shr32i_mips64
|
||||
#define helper_gvec_shr64i helper_gvec_shr64i_mips64
|
||||
#define helper_gvec_sub8 helper_gvec_sub8_mips64
|
||||
#define helper_gvec_sub16 helper_gvec_sub16_mips64
|
||||
#define helper_gvec_sub32 helper_gvec_sub32_mips64
|
||||
|
|
@ -3114,6 +3126,7 @@
|
|||
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mips64
|
||||
#define tcg_gen_goto_tb tcg_gen_goto_tb_mips64
|
||||
#define tcg_gen_gvec_2 tcg_gen_gvec_2_mips64
|
||||
#define tcg_gen_gvec_2i tcg_gen_gvec_2i_mips64
|
||||
#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_mips64
|
||||
#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_mips64
|
||||
#define tcg_gen_gvec_3 tcg_gen_gvec_3_mips64
|
||||
|
|
@ -3138,6 +3151,9 @@
|
|||
#define tcg_gen_gvec_not tcg_gen_gvec_not_mips64
|
||||
#define tcg_gen_gvec_or tcg_gen_gvec_or_mips64
|
||||
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_mips64
|
||||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_mips64
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_mips64
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_mips64
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_mips64
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_mips64
|
||||
#define tcg_gen_insn_start tcg_gen_insn_start_mips64
|
||||
|
|
@ -3231,6 +3247,7 @@
|
|||
#define tcg_gen_sar_i64 tcg_gen_sar_i64_mips64
|
||||
#define tcg_gen_sari_i32 tcg_gen_sari_i32_mips64
|
||||
#define tcg_gen_sari_i64 tcg_gen_sari_i64_mips64
|
||||
#define tcg_gen_sari_vec tcg_gen_sari_vec_mips64
|
||||
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_mips64
|
||||
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mips64
|
||||
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_mips64
|
||||
|
|
@ -3242,10 +3259,12 @@
|
|||
#define tcg_gen_shl_i64 tcg_gen_shl_i64_mips64
|
||||
#define tcg_gen_shli_i32 tcg_gen_shli_i32_mips64
|
||||
#define tcg_gen_shli_i64 tcg_gen_shli_i64_mips64
|
||||
#define tcg_gen_shli_vec tcg_gen_shli_vec_mips64
|
||||
#define tcg_gen_shr_i32 tcg_gen_shr_i32_mips64
|
||||
#define tcg_gen_shr_i64 tcg_gen_shr_i64_mips64
|
||||
#define tcg_gen_shri_i32 tcg_gen_shri_i32_mips64
|
||||
#define tcg_gen_shri_i64 tcg_gen_shri_i64_mips64
|
||||
#define tcg_gen_shri_vec tcg_gen_shri_vec_mips64
|
||||
#define tcg_gen_st_i32 tcg_gen_st_i32_mips64
|
||||
#define tcg_gen_st_i64 tcg_gen_st_i64_mips64
|
||||
#define tcg_gen_st_vec tcg_gen_st_vec_mips64
|
||||
|
|
@ -3265,6 +3284,12 @@
|
|||
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_mips64
|
||||
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_mips64
|
||||
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_mips64
|
||||
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_mips64
|
||||
#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_mips64
|
||||
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_mips64
|
||||
#define tcg_gen_vec_shl16i_i64 tcg_gen_vec_shl16i_i64_mips64
|
||||
#define tcg_gen_vec_shr8i_i64 tcg_gen_vec_shr8i_i64_mips64
|
||||
#define tcg_gen_vec_shr16i_i64 tcg_gen_vec_shr16i_i64_mips64
|
||||
#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_mips64
|
||||
#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_mips64
|
||||
#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_mips64
|
||||
|
|
|
|||
|
|
@ -1627,6 +1627,18 @@
|
|||
#define helper_gvec_not helper_gvec_not_mips64el
|
||||
#define helper_gvec_or helper_gvec_or_mips64el
|
||||
#define helper_gvec_orc helper_gvec_orc_mips64el
|
||||
#define helper_gvec_sar8i helper_gvec_sar8i_mips64el
|
||||
#define helper_gvec_sar16i helper_gvec_sar16i_mips64el
|
||||
#define helper_gvec_sar32i helper_gvec_sar32i_mips64el
|
||||
#define helper_gvec_sar64i helper_gvec_sar64i_mips64el
|
||||
#define helper_gvec_shl8i helper_gvec_shl8i_mips64el
|
||||
#define helper_gvec_shl16i helper_gvec_shl16i_mips64el
|
||||
#define helper_gvec_shl32i helper_gvec_shl32i_mips64el
|
||||
#define helper_gvec_shl64i helper_gvec_shl64i_mips64el
|
||||
#define helper_gvec_shr8i helper_gvec_shr8i_mips64el
|
||||
#define helper_gvec_shr16i helper_gvec_shr16i_mips64el
|
||||
#define helper_gvec_shr32i helper_gvec_shr32i_mips64el
|
||||
#define helper_gvec_shr64i helper_gvec_shr64i_mips64el
|
||||
#define helper_gvec_sub8 helper_gvec_sub8_mips64el
|
||||
#define helper_gvec_sub16 helper_gvec_sub16_mips64el
|
||||
#define helper_gvec_sub32 helper_gvec_sub32_mips64el
|
||||
|
|
@ -3114,6 +3126,7 @@
|
|||
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mips64el
|
||||
#define tcg_gen_goto_tb tcg_gen_goto_tb_mips64el
|
||||
#define tcg_gen_gvec_2 tcg_gen_gvec_2_mips64el
|
||||
#define tcg_gen_gvec_2i tcg_gen_gvec_2i_mips64el
|
||||
#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_mips64el
|
||||
#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_mips64el
|
||||
#define tcg_gen_gvec_3 tcg_gen_gvec_3_mips64el
|
||||
|
|
@ -3138,6 +3151,9 @@
|
|||
#define tcg_gen_gvec_not tcg_gen_gvec_not_mips64el
|
||||
#define tcg_gen_gvec_or tcg_gen_gvec_or_mips64el
|
||||
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_mips64el
|
||||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_mips64el
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_mips64el
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_mips64el
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_mips64el
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_mips64el
|
||||
#define tcg_gen_insn_start tcg_gen_insn_start_mips64el
|
||||
|
|
@ -3231,6 +3247,7 @@
|
|||
#define tcg_gen_sar_i64 tcg_gen_sar_i64_mips64el
|
||||
#define tcg_gen_sari_i32 tcg_gen_sari_i32_mips64el
|
||||
#define tcg_gen_sari_i64 tcg_gen_sari_i64_mips64el
|
||||
#define tcg_gen_sari_vec tcg_gen_sari_vec_mips64el
|
||||
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_mips64el
|
||||
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mips64el
|
||||
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_mips64el
|
||||
|
|
@ -3242,10 +3259,12 @@
|
|||
#define tcg_gen_shl_i64 tcg_gen_shl_i64_mips64el
|
||||
#define tcg_gen_shli_i32 tcg_gen_shli_i32_mips64el
|
||||
#define tcg_gen_shli_i64 tcg_gen_shli_i64_mips64el
|
||||
#define tcg_gen_shli_vec tcg_gen_shli_vec_mips64el
|
||||
#define tcg_gen_shr_i32 tcg_gen_shr_i32_mips64el
|
||||
#define tcg_gen_shr_i64 tcg_gen_shr_i64_mips64el
|
||||
#define tcg_gen_shri_i32 tcg_gen_shri_i32_mips64el
|
||||
#define tcg_gen_shri_i64 tcg_gen_shri_i64_mips64el
|
||||
#define tcg_gen_shri_vec tcg_gen_shri_vec_mips64el
|
||||
#define tcg_gen_st_i32 tcg_gen_st_i32_mips64el
|
||||
#define tcg_gen_st_i64 tcg_gen_st_i64_mips64el
|
||||
#define tcg_gen_st_vec tcg_gen_st_vec_mips64el
|
||||
|
|
@ -3265,6 +3284,12 @@
|
|||
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_mips64el
|
||||
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_mips64el
|
||||
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_mips64el
|
||||
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_mips64el
|
||||
#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_mips64el
|
||||
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_mips64el
|
||||
#define tcg_gen_vec_shl16i_i64 tcg_gen_vec_shl16i_i64_mips64el
|
||||
#define tcg_gen_vec_shr8i_i64 tcg_gen_vec_shr8i_i64_mips64el
|
||||
#define tcg_gen_vec_shr16i_i64 tcg_gen_vec_shr16i_i64_mips64el
|
||||
#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_mips64el
|
||||
#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_mips64el
|
||||
#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_mips64el
|
||||
|
|
|
|||
|
|
@ -1627,6 +1627,18 @@
|
|||
#define helper_gvec_not helper_gvec_not_mipsel
|
||||
#define helper_gvec_or helper_gvec_or_mipsel
|
||||
#define helper_gvec_orc helper_gvec_orc_mipsel
|
||||
#define helper_gvec_sar8i helper_gvec_sar8i_mipsel
|
||||
#define helper_gvec_sar16i helper_gvec_sar16i_mipsel
|
||||
#define helper_gvec_sar32i helper_gvec_sar32i_mipsel
|
||||
#define helper_gvec_sar64i helper_gvec_sar64i_mipsel
|
||||
#define helper_gvec_shl8i helper_gvec_shl8i_mipsel
|
||||
#define helper_gvec_shl16i helper_gvec_shl16i_mipsel
|
||||
#define helper_gvec_shl32i helper_gvec_shl32i_mipsel
|
||||
#define helper_gvec_shl64i helper_gvec_shl64i_mipsel
|
||||
#define helper_gvec_shr8i helper_gvec_shr8i_mipsel
|
||||
#define helper_gvec_shr16i helper_gvec_shr16i_mipsel
|
||||
#define helper_gvec_shr32i helper_gvec_shr32i_mipsel
|
||||
#define helper_gvec_shr64i helper_gvec_shr64i_mipsel
|
||||
#define helper_gvec_sub8 helper_gvec_sub8_mipsel
|
||||
#define helper_gvec_sub16 helper_gvec_sub16_mipsel
|
||||
#define helper_gvec_sub32 helper_gvec_sub32_mipsel
|
||||
|
|
@ -3114,6 +3126,7 @@
|
|||
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_mipsel
|
||||
#define tcg_gen_goto_tb tcg_gen_goto_tb_mipsel
|
||||
#define tcg_gen_gvec_2 tcg_gen_gvec_2_mipsel
|
||||
#define tcg_gen_gvec_2i tcg_gen_gvec_2i_mipsel
|
||||
#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_mipsel
|
||||
#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_mipsel
|
||||
#define tcg_gen_gvec_3 tcg_gen_gvec_3_mipsel
|
||||
|
|
@ -3138,6 +3151,9 @@
|
|||
#define tcg_gen_gvec_not tcg_gen_gvec_not_mipsel
|
||||
#define tcg_gen_gvec_or tcg_gen_gvec_or_mipsel
|
||||
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_mipsel
|
||||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_mipsel
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_mipsel
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_mipsel
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_mipsel
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_mipsel
|
||||
#define tcg_gen_insn_start tcg_gen_insn_start_mipsel
|
||||
|
|
@ -3231,6 +3247,7 @@
|
|||
#define tcg_gen_sar_i64 tcg_gen_sar_i64_mipsel
|
||||
#define tcg_gen_sari_i32 tcg_gen_sari_i32_mipsel
|
||||
#define tcg_gen_sari_i64 tcg_gen_sari_i64_mipsel
|
||||
#define tcg_gen_sari_vec tcg_gen_sari_vec_mipsel
|
||||
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_mipsel
|
||||
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mipsel
|
||||
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_mipsel
|
||||
|
|
@ -3242,10 +3259,12 @@
|
|||
#define tcg_gen_shl_i64 tcg_gen_shl_i64_mipsel
|
||||
#define tcg_gen_shli_i32 tcg_gen_shli_i32_mipsel
|
||||
#define tcg_gen_shli_i64 tcg_gen_shli_i64_mipsel
|
||||
#define tcg_gen_shli_vec tcg_gen_shli_vec_mipsel
|
||||
#define tcg_gen_shr_i32 tcg_gen_shr_i32_mipsel
|
||||
#define tcg_gen_shr_i64 tcg_gen_shr_i64_mipsel
|
||||
#define tcg_gen_shri_i32 tcg_gen_shri_i32_mipsel
|
||||
#define tcg_gen_shri_i64 tcg_gen_shri_i64_mipsel
|
||||
#define tcg_gen_shri_vec tcg_gen_shri_vec_mipsel
|
||||
#define tcg_gen_st_i32 tcg_gen_st_i32_mipsel
|
||||
#define tcg_gen_st_i64 tcg_gen_st_i64_mipsel
|
||||
#define tcg_gen_st_vec tcg_gen_st_vec_mipsel
|
||||
|
|
@ -3265,6 +3284,12 @@
|
|||
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_mipsel
|
||||
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_mipsel
|
||||
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_mipsel
|
||||
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_mipsel
|
||||
#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_mipsel
|
||||
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_mipsel
|
||||
#define tcg_gen_vec_shl16i_i64 tcg_gen_vec_shl16i_i64_mipsel
|
||||
#define tcg_gen_vec_shr8i_i64 tcg_gen_vec_shr8i_i64_mipsel
|
||||
#define tcg_gen_vec_shr16i_i64 tcg_gen_vec_shr16i_i64_mipsel
|
||||
#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_mipsel
|
||||
#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_mipsel
|
||||
#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_mipsel
|
||||
|
|
|
|||
|
|
@ -1627,6 +1627,18 @@
|
|||
#define helper_gvec_not helper_gvec_not_powerpc
|
||||
#define helper_gvec_or helper_gvec_or_powerpc
|
||||
#define helper_gvec_orc helper_gvec_orc_powerpc
|
||||
#define helper_gvec_sar8i helper_gvec_sar8i_powerpc
|
||||
#define helper_gvec_sar16i helper_gvec_sar16i_powerpc
|
||||
#define helper_gvec_sar32i helper_gvec_sar32i_powerpc
|
||||
#define helper_gvec_sar64i helper_gvec_sar64i_powerpc
|
||||
#define helper_gvec_shl8i helper_gvec_shl8i_powerpc
|
||||
#define helper_gvec_shl16i helper_gvec_shl16i_powerpc
|
||||
#define helper_gvec_shl32i helper_gvec_shl32i_powerpc
|
||||
#define helper_gvec_shl64i helper_gvec_shl64i_powerpc
|
||||
#define helper_gvec_shr8i helper_gvec_shr8i_powerpc
|
||||
#define helper_gvec_shr16i helper_gvec_shr16i_powerpc
|
||||
#define helper_gvec_shr32i helper_gvec_shr32i_powerpc
|
||||
#define helper_gvec_shr64i helper_gvec_shr64i_powerpc
|
||||
#define helper_gvec_sub8 helper_gvec_sub8_powerpc
|
||||
#define helper_gvec_sub16 helper_gvec_sub16_powerpc
|
||||
#define helper_gvec_sub32 helper_gvec_sub32_powerpc
|
||||
|
|
@ -3114,6 +3126,7 @@
|
|||
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_powerpc
|
||||
#define tcg_gen_goto_tb tcg_gen_goto_tb_powerpc
|
||||
#define tcg_gen_gvec_2 tcg_gen_gvec_2_powerpc
|
||||
#define tcg_gen_gvec_2i tcg_gen_gvec_2i_powerpc
|
||||
#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_powerpc
|
||||
#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_powerpc
|
||||
#define tcg_gen_gvec_3 tcg_gen_gvec_3_powerpc
|
||||
|
|
@ -3138,6 +3151,9 @@
|
|||
#define tcg_gen_gvec_not tcg_gen_gvec_not_powerpc
|
||||
#define tcg_gen_gvec_or tcg_gen_gvec_or_powerpc
|
||||
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_powerpc
|
||||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_powerpc
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_powerpc
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_powerpc
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_powerpc
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_powerpc
|
||||
#define tcg_gen_insn_start tcg_gen_insn_start_powerpc
|
||||
|
|
@ -3231,6 +3247,7 @@
|
|||
#define tcg_gen_sar_i64 tcg_gen_sar_i64_powerpc
|
||||
#define tcg_gen_sari_i32 tcg_gen_sari_i32_powerpc
|
||||
#define tcg_gen_sari_i64 tcg_gen_sari_i64_powerpc
|
||||
#define tcg_gen_sari_vec tcg_gen_sari_vec_powerpc
|
||||
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_powerpc
|
||||
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_powerpc
|
||||
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_powerpc
|
||||
|
|
@ -3242,10 +3259,12 @@
|
|||
#define tcg_gen_shl_i64 tcg_gen_shl_i64_powerpc
|
||||
#define tcg_gen_shli_i32 tcg_gen_shli_i32_powerpc
|
||||
#define tcg_gen_shli_i64 tcg_gen_shli_i64_powerpc
|
||||
#define tcg_gen_shli_vec tcg_gen_shli_vec_powerpc
|
||||
#define tcg_gen_shr_i32 tcg_gen_shr_i32_powerpc
|
||||
#define tcg_gen_shr_i64 tcg_gen_shr_i64_powerpc
|
||||
#define tcg_gen_shri_i32 tcg_gen_shri_i32_powerpc
|
||||
#define tcg_gen_shri_i64 tcg_gen_shri_i64_powerpc
|
||||
#define tcg_gen_shri_vec tcg_gen_shri_vec_powerpc
|
||||
#define tcg_gen_st_i32 tcg_gen_st_i32_powerpc
|
||||
#define tcg_gen_st_i64 tcg_gen_st_i64_powerpc
|
||||
#define tcg_gen_st_vec tcg_gen_st_vec_powerpc
|
||||
|
|
@ -3265,6 +3284,12 @@
|
|||
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_powerpc
|
||||
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_powerpc
|
||||
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_powerpc
|
||||
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_powerpc
|
||||
#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_powerpc
|
||||
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_powerpc
|
||||
#define tcg_gen_vec_shl16i_i64 tcg_gen_vec_shl16i_i64_powerpc
|
||||
#define tcg_gen_vec_shr8i_i64 tcg_gen_vec_shr8i_i64_powerpc
|
||||
#define tcg_gen_vec_shr16i_i64 tcg_gen_vec_shr16i_i64_powerpc
|
||||
#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_powerpc
|
||||
#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_powerpc
|
||||
#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_powerpc
|
||||
|
|
|
|||
25
qemu/sparc.h
25
qemu/sparc.h
|
|
@ -1627,6 +1627,18 @@
|
|||
#define helper_gvec_not helper_gvec_not_sparc
|
||||
#define helper_gvec_or helper_gvec_or_sparc
|
||||
#define helper_gvec_orc helper_gvec_orc_sparc
|
||||
#define helper_gvec_sar8i helper_gvec_sar8i_sparc
|
||||
#define helper_gvec_sar16i helper_gvec_sar16i_sparc
|
||||
#define helper_gvec_sar32i helper_gvec_sar32i_sparc
|
||||
#define helper_gvec_sar64i helper_gvec_sar64i_sparc
|
||||
#define helper_gvec_shl8i helper_gvec_shl8i_sparc
|
||||
#define helper_gvec_shl16i helper_gvec_shl16i_sparc
|
||||
#define helper_gvec_shl32i helper_gvec_shl32i_sparc
|
||||
#define helper_gvec_shl64i helper_gvec_shl64i_sparc
|
||||
#define helper_gvec_shr8i helper_gvec_shr8i_sparc
|
||||
#define helper_gvec_shr16i helper_gvec_shr16i_sparc
|
||||
#define helper_gvec_shr32i helper_gvec_shr32i_sparc
|
||||
#define helper_gvec_shr64i helper_gvec_shr64i_sparc
|
||||
#define helper_gvec_sub8 helper_gvec_sub8_sparc
|
||||
#define helper_gvec_sub16 helper_gvec_sub16_sparc
|
||||
#define helper_gvec_sub32 helper_gvec_sub32_sparc
|
||||
|
|
@ -3114,6 +3126,7 @@
|
|||
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_sparc
|
||||
#define tcg_gen_goto_tb tcg_gen_goto_tb_sparc
|
||||
#define tcg_gen_gvec_2 tcg_gen_gvec_2_sparc
|
||||
#define tcg_gen_gvec_2i tcg_gen_gvec_2i_sparc
|
||||
#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_sparc
|
||||
#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_sparc
|
||||
#define tcg_gen_gvec_3 tcg_gen_gvec_3_sparc
|
||||
|
|
@ -3138,6 +3151,9 @@
|
|||
#define tcg_gen_gvec_not tcg_gen_gvec_not_sparc
|
||||
#define tcg_gen_gvec_or tcg_gen_gvec_or_sparc
|
||||
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_sparc
|
||||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_sparc
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_sparc
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_sparc
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_sparc
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_sparc
|
||||
#define tcg_gen_insn_start tcg_gen_insn_start_sparc
|
||||
|
|
@ -3231,6 +3247,7 @@
|
|||
#define tcg_gen_sar_i64 tcg_gen_sar_i64_sparc
|
||||
#define tcg_gen_sari_i32 tcg_gen_sari_i32_sparc
|
||||
#define tcg_gen_sari_i64 tcg_gen_sari_i64_sparc
|
||||
#define tcg_gen_sari_vec tcg_gen_sari_vec_sparc
|
||||
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_sparc
|
||||
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_sparc
|
||||
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_sparc
|
||||
|
|
@ -3242,10 +3259,12 @@
|
|||
#define tcg_gen_shl_i64 tcg_gen_shl_i64_sparc
|
||||
#define tcg_gen_shli_i32 tcg_gen_shli_i32_sparc
|
||||
#define tcg_gen_shli_i64 tcg_gen_shli_i64_sparc
|
||||
#define tcg_gen_shli_vec tcg_gen_shli_vec_sparc
|
||||
#define tcg_gen_shr_i32 tcg_gen_shr_i32_sparc
|
||||
#define tcg_gen_shr_i64 tcg_gen_shr_i64_sparc
|
||||
#define tcg_gen_shri_i32 tcg_gen_shri_i32_sparc
|
||||
#define tcg_gen_shri_i64 tcg_gen_shri_i64_sparc
|
||||
#define tcg_gen_shri_vec tcg_gen_shri_vec_sparc
|
||||
#define tcg_gen_st_i32 tcg_gen_st_i32_sparc
|
||||
#define tcg_gen_st_i64 tcg_gen_st_i64_sparc
|
||||
#define tcg_gen_st_vec tcg_gen_st_vec_sparc
|
||||
|
|
@ -3265,6 +3284,12 @@
|
|||
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_sparc
|
||||
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_sparc
|
||||
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_sparc
|
||||
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_sparc
|
||||
#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_sparc
|
||||
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_sparc
|
||||
#define tcg_gen_vec_shl16i_i64 tcg_gen_vec_shl16i_i64_sparc
|
||||
#define tcg_gen_vec_shr8i_i64 tcg_gen_vec_shr8i_i64_sparc
|
||||
#define tcg_gen_vec_shr16i_i64 tcg_gen_vec_shr16i_i64_sparc
|
||||
#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_sparc
|
||||
#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_sparc
|
||||
#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_sparc
|
||||
|
|
|
|||
|
|
@ -1627,6 +1627,18 @@
|
|||
#define helper_gvec_not helper_gvec_not_sparc64
|
||||
#define helper_gvec_or helper_gvec_or_sparc64
|
||||
#define helper_gvec_orc helper_gvec_orc_sparc64
|
||||
#define helper_gvec_sar8i helper_gvec_sar8i_sparc64
|
||||
#define helper_gvec_sar16i helper_gvec_sar16i_sparc64
|
||||
#define helper_gvec_sar32i helper_gvec_sar32i_sparc64
|
||||
#define helper_gvec_sar64i helper_gvec_sar64i_sparc64
|
||||
#define helper_gvec_shl8i helper_gvec_shl8i_sparc64
|
||||
#define helper_gvec_shl16i helper_gvec_shl16i_sparc64
|
||||
#define helper_gvec_shl32i helper_gvec_shl32i_sparc64
|
||||
#define helper_gvec_shl64i helper_gvec_shl64i_sparc64
|
||||
#define helper_gvec_shr8i helper_gvec_shr8i_sparc64
|
||||
#define helper_gvec_shr16i helper_gvec_shr16i_sparc64
|
||||
#define helper_gvec_shr32i helper_gvec_shr32i_sparc64
|
||||
#define helper_gvec_shr64i helper_gvec_shr64i_sparc64
|
||||
#define helper_gvec_sub8 helper_gvec_sub8_sparc64
|
||||
#define helper_gvec_sub16 helper_gvec_sub16_sparc64
|
||||
#define helper_gvec_sub32 helper_gvec_sub32_sparc64
|
||||
|
|
@ -3114,6 +3126,7 @@
|
|||
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_sparc64
|
||||
#define tcg_gen_goto_tb tcg_gen_goto_tb_sparc64
|
||||
#define tcg_gen_gvec_2 tcg_gen_gvec_2_sparc64
|
||||
#define tcg_gen_gvec_2i tcg_gen_gvec_2i_sparc64
|
||||
#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_sparc64
|
||||
#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_sparc64
|
||||
#define tcg_gen_gvec_3 tcg_gen_gvec_3_sparc64
|
||||
|
|
@ -3138,6 +3151,9 @@
|
|||
#define tcg_gen_gvec_not tcg_gen_gvec_not_sparc64
|
||||
#define tcg_gen_gvec_or tcg_gen_gvec_or_sparc64
|
||||
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_sparc64
|
||||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_sparc64
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_sparc64
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_sparc64
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_sparc64
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_sparc64
|
||||
#define tcg_gen_insn_start tcg_gen_insn_start_sparc64
|
||||
|
|
@ -3231,6 +3247,7 @@
|
|||
#define tcg_gen_sar_i64 tcg_gen_sar_i64_sparc64
|
||||
#define tcg_gen_sari_i32 tcg_gen_sari_i32_sparc64
|
||||
#define tcg_gen_sari_i64 tcg_gen_sari_i64_sparc64
|
||||
#define tcg_gen_sari_vec tcg_gen_sari_vec_sparc64
|
||||
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_sparc64
|
||||
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_sparc64
|
||||
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_sparc64
|
||||
|
|
@ -3242,10 +3259,12 @@
|
|||
#define tcg_gen_shl_i64 tcg_gen_shl_i64_sparc64
|
||||
#define tcg_gen_shli_i32 tcg_gen_shli_i32_sparc64
|
||||
#define tcg_gen_shli_i64 tcg_gen_shli_i64_sparc64
|
||||
#define tcg_gen_shli_vec tcg_gen_shli_vec_sparc64
|
||||
#define tcg_gen_shr_i32 tcg_gen_shr_i32_sparc64
|
||||
#define tcg_gen_shr_i64 tcg_gen_shr_i64_sparc64
|
||||
#define tcg_gen_shri_i32 tcg_gen_shri_i32_sparc64
|
||||
#define tcg_gen_shri_i64 tcg_gen_shri_i64_sparc64
|
||||
#define tcg_gen_shri_vec tcg_gen_shri_vec_sparc64
|
||||
#define tcg_gen_st_i32 tcg_gen_st_i32_sparc64
|
||||
#define tcg_gen_st_i64 tcg_gen_st_i64_sparc64
|
||||
#define tcg_gen_st_vec tcg_gen_st_vec_sparc64
|
||||
|
|
@ -3265,6 +3284,12 @@
|
|||
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_sparc64
|
||||
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_sparc64
|
||||
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_sparc64
|
||||
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_sparc64
|
||||
#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_sparc64
|
||||
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_sparc64
|
||||
#define tcg_gen_vec_shl16i_i64 tcg_gen_vec_shl16i_i64_sparc64
|
||||
#define tcg_gen_vec_shr8i_i64 tcg_gen_vec_shr8i_i64_sparc64
|
||||
#define tcg_gen_vec_shr16i_i64 tcg_gen_vec_shr16i_i64_sparc64
|
||||
#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_sparc64
|
||||
#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_sparc64
|
||||
#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_sparc64
|
||||
|
|
|
|||
|
|
@ -323,3 +323,147 @@ void HELPER(gvec_orc)(void *d, void *a, void *b, uint32_t desc)
|
|||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_shl8i)(void *d, void *a, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
int shift = simd_data(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(vec8)) {
|
||||
*(vec8 *)(d + i) = *(vec8 *)(a + i) << shift;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_shl16i)(void *d, void *a, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
int shift = simd_data(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(vec16)) {
|
||||
*(vec16 *)(d + i) = *(vec16 *)(a + i) << shift;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_shl32i)(void *d, void *a, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
int shift = simd_data(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(vec32)) {
|
||||
*(vec32 *)(d + i) = *(vec32 *)(a + i) << shift;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_shl64i)(void *d, void *a, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
int shift = simd_data(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(vec64)) {
|
||||
*(vec64 *)(d + i) = *(vec64 *)(a + i) << shift;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_shr8i)(void *d, void *a, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
int shift = simd_data(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(vec8)) {
|
||||
*(vec8 *)(d + i) = *(vec8 *)(a + i) >> shift;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_shr16i)(void *d, void *a, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
int shift = simd_data(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(vec16)) {
|
||||
*(vec16 *)(d + i) = *(vec16 *)(a + i) >> shift;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_shr32i)(void *d, void *a, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
int shift = simd_data(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(vec32)) {
|
||||
*(vec32 *)(d + i) = *(vec32 *)(a + i) >> shift;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_shr64i)(void *d, void *a, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
int shift = simd_data(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(vec64)) {
|
||||
*(vec64 *)(d + i) = *(vec64 *)(a + i) >> shift;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_sar8i)(void *d, void *a, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
int shift = simd_data(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(vec8)) {
|
||||
*(svec8 *)(d + i) = *(svec8 *)(a + i) >> shift;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_sar16i)(void *d, void *a, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
int shift = simd_data(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(vec16)) {
|
||||
*(svec16 *)(d + i) = *(svec16 *)(a + i) >> shift;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_sar32i)(void *d, void *a, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
int shift = simd_data(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(vec32)) {
|
||||
*(svec32 *)(d + i) = *(svec32 *)(a + i) >> shift;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_sar64i)(void *d, void *a, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
int shift = simd_data(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(vec64)) {
|
||||
*(svec64 *)(d + i) = *(svec64 *)(a + i) >> shift;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -547,6 +547,35 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
|
|||
Similarly, logical operations with and without compliment.
|
||||
Note that VECE is unused.
|
||||
|
||||
* shli_vec v0, v1, i2
|
||||
* shls_vec v0, v1, s2
|
||||
|
||||
Shift all elements from v1 by a scalar i2/s2. I.e.
|
||||
|
||||
for (i = 0; i < VECL/VECE; ++i) {
|
||||
v0[i] = v1[i] << s2;
|
||||
}
|
||||
|
||||
* shri_vec v0, v1, i2
|
||||
* sari_vec v0, v1, i2
|
||||
* shrs_vec v0, v1, s2
|
||||
* sars_vec v0, v1, s2
|
||||
|
||||
Similarly for logical and arithmetic right shift.
|
||||
|
||||
* shlv_vec v0, v1, v2
|
||||
|
||||
Shift elements from v1 by elements from v2. I.e.
|
||||
|
||||
for (i = 0; i < VECL/VECE; ++i) {
|
||||
v0[i] = v1[i] << v2[i];
|
||||
}
|
||||
|
||||
* shrv_vec v0, v1, v2
|
||||
* sarv_vec v0, v1, v2
|
||||
|
||||
Similarly for logical and arithmetic right shift.
|
||||
|
||||
*********
|
||||
|
||||
Note 1: Some shortcuts are defined when the last operand is known to be
|
||||
|
|
|
|||
|
|
@ -535,6 +535,26 @@ static void expand_2_i32(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t o
|
|||
tcg_temp_free_i32(s, t0);
|
||||
}
|
||||
|
||||
static void expand_2i_i32(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t oprsz,
|
||||
int32_t c, bool load_dest,
|
||||
void (*fni)(TCGContext *, TCGv_i32, TCGv_i32, int32_t))
|
||||
{
|
||||
TCGv_i32 t0 = tcg_temp_new_i32(s);
|
||||
TCGv_i32 t1 = tcg_temp_new_i32(s);
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += 4) {
|
||||
tcg_gen_ld_i32(s, t0, s->cpu_env, aofs + i);
|
||||
if (load_dest) {
|
||||
tcg_gen_ld_i32(s, t1, s->cpu_env, dofs + i);
|
||||
}
|
||||
fni(s, t1, t0, c);
|
||||
tcg_gen_st_i32(s, t1, s->cpu_env, dofs + i);
|
||||
}
|
||||
tcg_temp_free_i32(s, t0);
|
||||
tcg_temp_free_i32(s, t1);
|
||||
}
|
||||
|
||||
/* Expand OPSZ bytes worth of three-operand operations using i32 elements. */
|
||||
static void expand_3_i32(TCGContext *s, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t bofs, uint32_t oprsz, bool load_dest,
|
||||
|
|
@ -598,6 +618,26 @@ static void expand_2_i64(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t o
|
|||
tcg_temp_free_i64(s, t0);
|
||||
}
|
||||
|
||||
static void expand_2i_i64(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t oprsz,
|
||||
int64_t c, bool load_dest,
|
||||
void (*fni)(TCGContext *s, TCGv_i64, TCGv_i64, int64_t))
|
||||
{
|
||||
TCGv_i64 t0 = tcg_temp_new_i64(s);
|
||||
TCGv_i64 t1 = tcg_temp_new_i64(s);
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += 8) {
|
||||
tcg_gen_ld_i64(s, t0, s->cpu_env, aofs + i);
|
||||
if (load_dest) {
|
||||
tcg_gen_ld_i64(s, t1, s->cpu_env, dofs + i);
|
||||
}
|
||||
fni(s, t1, t0, c);
|
||||
tcg_gen_st_i64(s, t1, s->cpu_env, dofs + i);
|
||||
}
|
||||
tcg_temp_free_i64(s, t0);
|
||||
tcg_temp_free_i64(s, t1);
|
||||
}
|
||||
|
||||
/* Expand OPSZ bytes worth of three-operand operations using i64 elements. */
|
||||
static void expand_3_i64(TCGContext *s, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t bofs, uint32_t oprsz, bool load_dest,
|
||||
|
|
@ -662,6 +702,30 @@ static void expand_2_vec(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t a
|
|||
tcg_temp_free_vec(s, t0);
|
||||
}
|
||||
|
||||
/* Expand OPSZ bytes worth of two-vector operands and an immediate operand
|
||||
using host vectors. */
|
||||
static void expand_2i_vec(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t oprsz, uint32_t tysz, TCGType type,
|
||||
int64_t c, bool load_dest,
|
||||
void (*fni)(TCGContext *s, unsigned, TCGv_vec, TCGv_vec, int64_t))
|
||||
{
|
||||
TCGv_vec t0 = tcg_temp_new_vec(s, type);
|
||||
TCGv_vec t1 = tcg_temp_new_vec(s, type);
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += tysz) {
|
||||
tcg_gen_ld_vec(s, t0, s->cpu_env, aofs + i);
|
||||
if (load_dest) {
|
||||
tcg_gen_ld_vec(s, t1, s->cpu_env, dofs + i);
|
||||
}
|
||||
fni(s, vece, t1, t0, c);
|
||||
tcg_gen_st_vec(s, t1, s->cpu_env, dofs + i);
|
||||
}
|
||||
tcg_temp_free_vec(s, t0);
|
||||
tcg_temp_free_vec(s, t1);
|
||||
}
|
||||
|
||||
|
||||
/* Expand OPSZ bytes worth of three-operand operations using host vectors. */
|
||||
static void expand_3_vec(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t bofs, uint32_t oprsz,
|
||||
|
|
@ -765,6 +829,55 @@ void tcg_gen_gvec_2(TCGContext *s, uint32_t dofs, uint32_t aofs,
|
|||
}
|
||||
}
|
||||
|
||||
void tcg_gen_gvec_2i(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t oprsz,
|
||||
uint32_t maxsz, int64_t c, const GVecGen2i *g)
|
||||
{
|
||||
check_size_align(oprsz, maxsz, dofs | aofs);
|
||||
check_overlap_2(dofs, aofs, maxsz);
|
||||
|
||||
/* Recall that ARM SVE allows vector sizes that are not a power of 2.
|
||||
Expand with successively smaller host vector sizes. The intent is
|
||||
that e.g. oprsz == 80 would be expanded with 2x32 + 1x16. */
|
||||
|
||||
if (TCG_TARGET_HAS_v256 && g->fniv && check_size_impl(oprsz, 32)
|
||||
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V256, g->vece))) {
|
||||
uint32_t some = QEMU_ALIGN_DOWN(oprsz, 32);
|
||||
expand_2i_vec(s, g->vece, dofs, aofs, some, 32, TCG_TYPE_V256,
|
||||
c, g->load_dest, g->fniv);
|
||||
if (some == oprsz) {
|
||||
goto done;
|
||||
}
|
||||
dofs += some;
|
||||
aofs += some;
|
||||
oprsz -= some;
|
||||
maxsz -= some;
|
||||
}
|
||||
|
||||
if (TCG_TARGET_HAS_v128 && g->fniv && check_size_impl(oprsz, 16)
|
||||
&& (!g->opc || tcg_can_emit_vec_op(g->opc, TCG_TYPE_V128, g->vece))) {
|
||||
expand_2i_vec(s, g->vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128,
|
||||
c, g->load_dest, g->fniv);
|
||||
} else if (TCG_TARGET_HAS_v64 && !g->prefer_i64
|
||||
&& g->fniv && check_size_impl(oprsz, 8)
|
||||
&& (!g->opc
|
||||
|| tcg_can_emit_vec_op(g->opc, TCG_TYPE_V64, g->vece))) {
|
||||
expand_2i_vec(s, g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64,
|
||||
c, g->load_dest, g->fniv);
|
||||
} else if (g->fni8 && check_size_impl(oprsz, 8)) {
|
||||
expand_2i_i64(s, dofs, aofs, oprsz, c, g->load_dest, g->fni8);
|
||||
} else if (g->fni4 && check_size_impl(oprsz, 4)) {
|
||||
expand_2i_i32(s, dofs, aofs, oprsz, c, g->load_dest, g->fni4);
|
||||
} else {
|
||||
tcg_gen_gvec_2_ool(s, dofs, aofs, oprsz, maxsz, c, g->fno);
|
||||
return;
|
||||
}
|
||||
|
||||
done:
|
||||
if (oprsz < maxsz) {
|
||||
expand_clr(s, dofs + oprsz, maxsz - oprsz);
|
||||
}
|
||||
}
|
||||
|
||||
/* Expand a vector three-operand operation. */
|
||||
void tcg_gen_gvec_3(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs,
|
||||
uint32_t oprsz, uint32_t maxsz, const GVecGen3 *g)
|
||||
|
|
@ -1307,3 +1420,167 @@ void tcg_gen_gvec_orc(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs
|
|||
};
|
||||
tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g);
|
||||
}
|
||||
|
||||
void tcg_gen_vec_shl8i_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, int64_t c)
|
||||
{
|
||||
uint64_t mask = dup_const(MO_8, 0xff << c);
|
||||
tcg_gen_shli_i64(s, d, a, c);
|
||||
tcg_gen_andi_i64(s, d, d, mask);
|
||||
}
|
||||
|
||||
void tcg_gen_vec_shl16i_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, int64_t c)
|
||||
{
|
||||
uint64_t mask = dup_const(MO_16, 0xffff << c);
|
||||
tcg_gen_shli_i64(s, d, a, c);
|
||||
tcg_gen_andi_i64(s, d, d, mask);
|
||||
}
|
||||
|
||||
void tcg_gen_gvec_shli(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
int64_t shift, uint32_t oprsz, uint32_t maxsz)
|
||||
{
|
||||
static const GVecGen2i g[4] = {
|
||||
{ .fni8 = tcg_gen_vec_shl8i_i64,
|
||||
.fniv = tcg_gen_shli_vec,
|
||||
.fno = gen_helper_gvec_shl8i,
|
||||
.opc = INDEX_op_shli_vec,
|
||||
.vece = MO_8 },
|
||||
{ .fni8 = tcg_gen_vec_shl16i_i64,
|
||||
.fniv = tcg_gen_shli_vec,
|
||||
.fno = gen_helper_gvec_shl16i,
|
||||
.opc = INDEX_op_shli_vec,
|
||||
.vece = MO_16 },
|
||||
{ .fni4 = tcg_gen_shli_i32,
|
||||
.fniv = tcg_gen_shli_vec,
|
||||
.fno = gen_helper_gvec_shl32i,
|
||||
.opc = INDEX_op_shli_vec,
|
||||
.vece = MO_32 },
|
||||
{ .fni8 = tcg_gen_shli_i64,
|
||||
.fniv = tcg_gen_shli_vec,
|
||||
.fno = gen_helper_gvec_shl64i,
|
||||
.opc = INDEX_op_shli_vec,
|
||||
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
|
||||
.vece = MO_64 },
|
||||
};
|
||||
|
||||
tcg_debug_assert(vece <= MO_64);
|
||||
tcg_debug_assert(shift >= 0 && shift < (8 << vece));
|
||||
if (shift == 0) {
|
||||
tcg_gen_gvec_mov(s, vece, dofs, aofs, oprsz, maxsz);
|
||||
} else {
|
||||
tcg_gen_gvec_2i(s, dofs, aofs, oprsz, maxsz, shift, &g[vece]);
|
||||
}
|
||||
}
|
||||
|
||||
void tcg_gen_vec_shr8i_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, int64_t c)
|
||||
{
|
||||
uint64_t mask = dup_const(MO_8, 0xff >> c);
|
||||
tcg_gen_shri_i64(s, d, a, c);
|
||||
tcg_gen_andi_i64(s, d, d, mask);
|
||||
}
|
||||
|
||||
void tcg_gen_vec_shr16i_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, int64_t c)
|
||||
{
|
||||
uint64_t mask = dup_const(MO_16, 0xffff >> c);
|
||||
tcg_gen_shri_i64(s, d, a, c);
|
||||
tcg_gen_andi_i64(s, d, d, mask);
|
||||
}
|
||||
|
||||
void tcg_gen_gvec_shri(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
int64_t shift, uint32_t oprsz, uint32_t maxsz)
|
||||
{
|
||||
static const GVecGen2i g[4] = {
|
||||
{ .fni8 = tcg_gen_vec_shr8i_i64,
|
||||
.fniv = tcg_gen_shri_vec,
|
||||
.fno = gen_helper_gvec_shr8i,
|
||||
.opc = INDEX_op_shri_vec,
|
||||
.vece = MO_8 },
|
||||
{ .fni8 = tcg_gen_vec_shr16i_i64,
|
||||
.fniv = tcg_gen_shri_vec,
|
||||
.fno = gen_helper_gvec_shr16i,
|
||||
.opc = INDEX_op_shri_vec,
|
||||
.vece = MO_16 },
|
||||
{ .fni4 = tcg_gen_shri_i32,
|
||||
.fniv = tcg_gen_shri_vec,
|
||||
.fno = gen_helper_gvec_shr32i,
|
||||
.opc = INDEX_op_shri_vec,
|
||||
.vece = MO_32 },
|
||||
{ .fni8 = tcg_gen_shri_i64,
|
||||
.fniv = tcg_gen_shri_vec,
|
||||
.fno = gen_helper_gvec_shr64i,
|
||||
.opc = INDEX_op_shri_vec,
|
||||
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
|
||||
.vece = MO_64 },
|
||||
};
|
||||
|
||||
tcg_debug_assert(vece <= MO_64);
|
||||
tcg_debug_assert(shift >= 0 && shift < (8 << vece));
|
||||
if (shift == 0) {
|
||||
tcg_gen_gvec_mov(s, vece, dofs, aofs, oprsz, maxsz);
|
||||
} else {
|
||||
tcg_gen_gvec_2i(s, dofs, aofs, oprsz, maxsz, shift, &g[vece]);
|
||||
}
|
||||
}
|
||||
|
||||
void tcg_gen_vec_sar8i_i64(TCGContext *ctx, TCGv_i64 d, TCGv_i64 a, int64_t c)
|
||||
{
|
||||
uint64_t s_mask = dup_const(MO_8, 0x80 >> c);
|
||||
uint64_t c_mask = dup_const(MO_8, 0xff >> c);
|
||||
TCGv_i64 s = tcg_temp_new_i64(ctx);
|
||||
|
||||
tcg_gen_shri_i64(ctx, d, a, c);
|
||||
tcg_gen_andi_i64(ctx, s, d, s_mask); /* isolate (shifted) sign bit */
|
||||
tcg_gen_muli_i64(ctx, s, s, (2 << c) - 2); /* replicate isolated signs */
|
||||
tcg_gen_andi_i64(ctx, d, d, c_mask); /* clear out bits above sign */
|
||||
tcg_gen_or_i64(ctx, d, d, s); /* include sign extension */
|
||||
tcg_temp_free_i64(ctx, s);
|
||||
}
|
||||
|
||||
void tcg_gen_vec_sar16i_i64(TCGContext *ctx, TCGv_i64 d, TCGv_i64 a, int64_t c)
|
||||
{
|
||||
uint64_t s_mask = dup_const(MO_16, 0x8000 >> c);
|
||||
uint64_t c_mask = dup_const(MO_16, 0xffff >> c);
|
||||
TCGv_i64 s = tcg_temp_new_i64(ctx);
|
||||
|
||||
tcg_gen_shri_i64(ctx, d, a, c);
|
||||
tcg_gen_andi_i64(ctx, s, d, s_mask); /* isolate (shifted) sign bit */
|
||||
tcg_gen_andi_i64(ctx, d, d, c_mask); /* clear out bits above sign */
|
||||
tcg_gen_muli_i64(ctx, s, s, (2 << c) - 2); /* replicate isolated signs */
|
||||
tcg_gen_or_i64(ctx, d, d, s); /* include sign extension */
|
||||
tcg_temp_free_i64(ctx, s);
|
||||
}
|
||||
|
||||
void tcg_gen_gvec_sari(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
int64_t shift, uint32_t oprsz, uint32_t maxsz)
|
||||
{
|
||||
static const GVecGen2i g[4] = {
|
||||
{ .fni8 = tcg_gen_vec_sar8i_i64,
|
||||
.fniv = tcg_gen_sari_vec,
|
||||
.fno = gen_helper_gvec_sar8i,
|
||||
.opc = INDEX_op_sari_vec,
|
||||
.vece = MO_8 },
|
||||
{ .fni8 = tcg_gen_vec_sar16i_i64,
|
||||
.fniv = tcg_gen_sari_vec,
|
||||
.fno = gen_helper_gvec_sar16i,
|
||||
.opc = INDEX_op_sari_vec,
|
||||
.vece = MO_16 },
|
||||
{ .fni4 = tcg_gen_sari_i32,
|
||||
.fniv = tcg_gen_sari_vec,
|
||||
.fno = gen_helper_gvec_sar32i,
|
||||
.opc = INDEX_op_sari_vec,
|
||||
.vece = MO_32 },
|
||||
{ .fni8 = tcg_gen_sari_i64,
|
||||
.fniv = tcg_gen_sari_vec,
|
||||
.fno = gen_helper_gvec_sar64i,
|
||||
.opc = INDEX_op_sari_vec,
|
||||
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
|
||||
.vece = MO_64 },
|
||||
};
|
||||
|
||||
tcg_debug_assert(vece <= MO_64);
|
||||
tcg_debug_assert(shift >= 0 && shift < (8 << vece));
|
||||
if (shift == 0) {
|
||||
tcg_gen_gvec_mov(s, vece, dofs, aofs, oprsz, maxsz);
|
||||
} else {
|
||||
tcg_gen_gvec_2i(s, dofs, aofs, oprsz, maxsz, shift, &g[vece]);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -76,13 +76,32 @@ void tcg_gen_gvec_4_ptr(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bo
|
|||
|
||||
/* Expand a gvec operation. Either inline or out-of-line depending on
|
||||
the actual vector size and the operations supported by the host. */
|
||||
typedef struct {
|
||||
/* Expand inline as a 64-bit or 32-bit integer.
|
||||
Only one of these will be non-NULL. */
|
||||
void (*fni8)(TCGContext *, TCGv_i64, TCGv_i64, int64_t);
|
||||
void (*fni4)(TCGContext *, TCGv_i32, TCGv_i32, int32_t);
|
||||
/* Expand inline with a host vector type. */
|
||||
void (*fniv)(TCGContext *, unsigned, TCGv_vec, TCGv_vec, int64_t);
|
||||
/* Expand out-of-line helper w/descriptor. */
|
||||
gen_helper_gvec_2 *fno;
|
||||
/* The opcode, if any, to which this corresponds. */
|
||||
TCGOpcode opc;
|
||||
/* The vector element size, if applicable. */
|
||||
uint8_t vece;
|
||||
/* Prefer i64 to v64. */
|
||||
bool prefer_i64;
|
||||
/* Load dest as a 3rd source operand. */
|
||||
bool load_dest;
|
||||
} GVecGen2i;
|
||||
|
||||
typedef struct {
|
||||
/* Expand inline as a 64-bit or 32-bit integer.
|
||||
Only one of these will be non-NULL. */
|
||||
void (*fni8)(TCGContext *, TCGv_i64, TCGv_i64);
|
||||
void (*fni4)(TCGContext *, TCGv_i32, TCGv_i32);
|
||||
/* Expand inline with a host vector type. */
|
||||
void (*fniv)(TCGContext *s, unsigned, TCGv_vec, TCGv_vec);
|
||||
void (*fniv)(TCGContext *, unsigned, TCGv_vec, TCGv_vec);
|
||||
/* Expand out-of-line helper w/descriptor. */
|
||||
gen_helper_gvec_2 *fno;
|
||||
/* The opcode, if any, to which this corresponds. */
|
||||
|
|
@ -98,10 +117,10 @@ typedef struct {
|
|||
typedef struct {
|
||||
/* Expand inline as a 64-bit or 32-bit integer.
|
||||
Only one of these will be non-NULL. */
|
||||
void (*fni8)(TCGContext *s, TCGv_i64, TCGv_i64, TCGv_i64);
|
||||
void (*fni4)(TCGContext *s, TCGv_i32, TCGv_i32, TCGv_i32);
|
||||
void (*fni8)(TCGContext *, TCGv_i64, TCGv_i64, TCGv_i64);
|
||||
void (*fni4)(TCGContext *, TCGv_i32, TCGv_i32, TCGv_i32);
|
||||
/* Expand inline with a host vector type. */
|
||||
void (*fniv)(TCGContext *s, unsigned, TCGv_vec, TCGv_vec, TCGv_vec);
|
||||
void (*fniv)(TCGContext *, unsigned, TCGv_vec, TCGv_vec, TCGv_vec);
|
||||
/* Expand out-of-line helper w/descriptor. */
|
||||
gen_helper_gvec_3 *fno;
|
||||
/* The opcode, if any, to which this corresponds. */
|
||||
|
|
@ -137,6 +156,8 @@ typedef struct {
|
|||
|
||||
void tcg_gen_gvec_2(TCGContext *, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t oprsz, uint32_t maxsz, const GVecGen2 *);
|
||||
void tcg_gen_gvec_2i(TCGContext *, uint32_t dofs, uint32_t aofs, uint32_t oprsz,
|
||||
uint32_t maxsz, int64_t c, const GVecGen2i *);
|
||||
void tcg_gen_gvec_3(TCGContext *, uint32_t dofs, uint32_t aofs, uint32_t bofs,
|
||||
uint32_t oprsz, uint32_t maxsz, const GVecGen3 *);
|
||||
void tcg_gen_gvec_4(TCGContext *, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs,
|
||||
|
|
@ -174,6 +195,13 @@ void tcg_gen_gvec_dup_i32(TCGContext *, unsigned vece, uint32_t dofs, uint32_t s
|
|||
void tcg_gen_gvec_dup_i64(TCGContext *, unsigned vece, uint32_t dofs, uint32_t s,
|
||||
uint32_t m, TCGv_i64);
|
||||
|
||||
void tcg_gen_gvec_shli(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
int64_t shift, uint32_t oprsz, uint32_t maxsz);
|
||||
void tcg_gen_gvec_shri(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
int64_t shift, uint32_t oprsz, uint32_t maxsz);
|
||||
void tcg_gen_gvec_sari(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
int64_t shift, uint32_t oprsz, uint32_t maxsz);
|
||||
|
||||
void tcg_gen_gvec_dup8i(TCGContext *, uint32_t dofs, uint32_t s, uint32_t m, uint8_t x);
|
||||
void tcg_gen_gvec_dup16i(TCGContext *, uint32_t dofs, uint32_t s, uint32_t m, uint16_t x);
|
||||
void tcg_gen_gvec_dup32i(TCGContext *, uint32_t dofs, uint32_t s, uint32_t m, uint32_t x);
|
||||
|
|
@ -196,3 +224,10 @@ void tcg_gen_vec_add32_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
|
|||
void tcg_gen_vec_sub8_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
|
||||
void tcg_gen_vec_sub16_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
|
||||
void tcg_gen_vec_sub32_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b);
|
||||
|
||||
void tcg_gen_vec_shl8i_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, int64_t);
|
||||
void tcg_gen_vec_shl16i_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, int64_t);
|
||||
void tcg_gen_vec_shr8i_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, int64_t);
|
||||
void tcg_gen_vec_shr16i_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, int64_t);
|
||||
void tcg_gen_vec_sar8i_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, int64_t);
|
||||
void tcg_gen_vec_sar16i_i64(TCGContext *, TCGv_i64 d, TCGv_i64 a, int64_t);
|
||||
|
|
|
|||
|
|
@ -297,3 +297,48 @@ void tcg_gen_neg_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a)
|
|||
tcg_temp_free_vec(s, t);
|
||||
}
|
||||
}
|
||||
|
||||
static void do_shifti(TCGContext *s, TCGOpcode opc, unsigned vece,
|
||||
TCGv_vec r, TCGv_vec a, int64_t i)
|
||||
{
|
||||
TCGTemp *rt = tcgv_vec_temp(s, r);
|
||||
TCGTemp *at = tcgv_vec_temp(s, a);
|
||||
TCGArg ri = temp_arg(rt);
|
||||
TCGArg ai = temp_arg(at);
|
||||
TCGType type = rt->base_type;
|
||||
int can;
|
||||
|
||||
tcg_debug_assert(at->base_type == type);
|
||||
tcg_debug_assert(i >= 0 && i < (8 << vece));
|
||||
|
||||
if (i == 0) {
|
||||
tcg_gen_mov_vec(s, r, a);
|
||||
return;
|
||||
}
|
||||
|
||||
can = tcg_can_emit_vec_op(opc, type, vece);
|
||||
if (can > 0) {
|
||||
vec_gen_3(s, opc, type, vece, ri, ai, i);
|
||||
} else {
|
||||
/* We leave the choice of expansion via scalar or vector shift
|
||||
to the target. Often, but not always, dupi can feed a vector
|
||||
shift easier than a scalar. */
|
||||
tcg_debug_assert(can < 0);
|
||||
tcg_expand_vec_op(s, opc, type, vece, ri, ai, i);
|
||||
}
|
||||
}
|
||||
|
||||
void tcg_gen_shli_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i)
|
||||
{
|
||||
do_shifti(s, INDEX_op_shli_vec, vece, r, a, i);
|
||||
}
|
||||
|
||||
void tcg_gen_shri_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i)
|
||||
{
|
||||
do_shifti(s, INDEX_op_shri_vec, vece, r, a, i);
|
||||
}
|
||||
|
||||
void tcg_gen_sari_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i)
|
||||
{
|
||||
do_shifti(s, INDEX_op_sari_vec, vece, r, a, i);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -933,6 +933,10 @@ void tcg_gen_orc_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_v
|
|||
void tcg_gen_not_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a);
|
||||
void tcg_gen_neg_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a);
|
||||
|
||||
void tcg_gen_shli_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
|
||||
void tcg_gen_shri_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
|
||||
void tcg_gen_sari_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i);
|
||||
|
||||
void tcg_gen_ld_vec(TCGContext *, TCGv_vec r, TCGv_ptr base, TCGArg offset);
|
||||
void tcg_gen_st_vec(TCGContext *, TCGv_vec r, TCGv_ptr base, TCGArg offset);
|
||||
void tcg_gen_stl_vec(TCGContext *, TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
|
||||
|
|
|
|||
|
|
@ -232,6 +232,18 @@ DEF(andc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_andc_vec))
|
|||
DEF(orc_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_orc_vec))
|
||||
DEF(not_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_not_vec))
|
||||
|
||||
DEF(shli_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
|
||||
DEF(shri_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
|
||||
DEF(sari_vec, 1, 1, 1, IMPLVEC | IMPL(TCG_TARGET_HAS_shi_vec))
|
||||
|
||||
DEF(shls_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
|
||||
DEF(shrs_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
|
||||
DEF(sars_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shs_vec))
|
||||
|
||||
DEF(shlv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
|
||||
DEF(shrv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
|
||||
DEF(sarv_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_shv_vec))
|
||||
|
||||
DEF(last_generic, 0, 0, 0, TCG_OPF_NOT_PRESENT)
|
||||
|
||||
#if TCG_TARGET_MAYBE_vec
|
||||
|
|
|
|||
|
|
@ -165,3 +165,17 @@ DEF_HELPER_FLAGS_4(gvec_xor, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
|||
DEF_HELPER_FLAGS_4(gvec_andc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_orc, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(gvec_shl8i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(gvec_shl16i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(gvec_shl32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(gvec_shl64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(gvec_shr8i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(gvec_shr16i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(gvec_shr32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(gvec_shr64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(gvec_sar8i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(gvec_sar16i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(gvec_sar32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(gvec_sar64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
|
||||
|
|
|
|||
|
|
@ -1059,6 +1059,18 @@ bool tcg_op_supported(TCGOpcode op)
|
|||
return have_vec && TCG_TARGET_HAS_andc_vec;
|
||||
case INDEX_op_orc_vec:
|
||||
return have_vec && TCG_TARGET_HAS_orc_vec;
|
||||
case INDEX_op_shli_vec:
|
||||
case INDEX_op_shri_vec:
|
||||
case INDEX_op_sari_vec:
|
||||
return have_vec && TCG_TARGET_HAS_shi_vec;
|
||||
case INDEX_op_shls_vec:
|
||||
case INDEX_op_shrs_vec:
|
||||
case INDEX_op_sars_vec:
|
||||
return have_vec && TCG_TARGET_HAS_shs_vec;
|
||||
case INDEX_op_shlv_vec:
|
||||
case INDEX_op_shrv_vec:
|
||||
case INDEX_op_sarv_vec:
|
||||
return have_vec && TCG_TARGET_HAS_shv_vec;
|
||||
|
||||
default:
|
||||
tcg_debug_assert(op > INDEX_op_last_generic && op < NB_OPS);
|
||||
|
|
@ -3131,7 +3143,7 @@ void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf)
|
|||
#endif
|
||||
|
||||
#if !TCG_TARGET_MAYBE_vec
|
||||
void tcg_expand_vec_op(TCGOpcode o, TCGType t, unsigned e, TCGArg a0, ...)
|
||||
void tcg_expand_vec_op(TCGContext *s, TCGOpcode o, TCGType t, unsigned e, TCGArg a0, ...)
|
||||
{
|
||||
g_assert_not_reached();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -181,6 +181,9 @@ typedef uint64_t TCGRegSet;
|
|||
#define TCG_TARGET_HAS_not_vec 0
|
||||
#define TCG_TARGET_HAS_andc_vec 0
|
||||
#define TCG_TARGET_HAS_orc_vec 0
|
||||
#define TCG_TARGET_HAS_shi_vec 0
|
||||
#define TCG_TARGET_HAS_shs_vec 0
|
||||
#define TCG_TARGET_HAS_shv_vec 0
|
||||
#else
|
||||
#define TCG_TARGET_MAYBE_vec 1
|
||||
#endif
|
||||
|
|
@ -1094,7 +1097,7 @@ static inline TCGv_i64 tcg_temp_local_new_i64(TCGContext *s)
|
|||
}
|
||||
|
||||
// UNICORN: Added
|
||||
#define TCG_OP_DEFS_TABLE_SIZE 152
|
||||
#define TCG_OP_DEFS_TABLE_SIZE 161
|
||||
extern const TCGOpDef tcg_op_defs_org[TCG_OP_DEFS_TABLE_SIZE];
|
||||
|
||||
typedef struct TCGTargetOpDef {
|
||||
|
|
@ -1352,7 +1355,7 @@ static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve)
|
|||
#endif
|
||||
|
||||
/* Expand the tuple (opc, type, vece) on the given arguments. */
|
||||
void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...);
|
||||
void tcg_expand_vec_op(TCGContext *s, TCGOpcode, TCGType, unsigned, TCGArg, ...);
|
||||
|
||||
/* Replicate a constant C accoring to the log2 of the element size. */
|
||||
// Unicorn: renamed to avoid symbol clashing
|
||||
|
|
|
|||
|
|
@ -1627,6 +1627,18 @@
|
|||
#define helper_gvec_not helper_gvec_not_x86_64
|
||||
#define helper_gvec_or helper_gvec_or_x86_64
|
||||
#define helper_gvec_orc helper_gvec_orc_x86_64
|
||||
#define helper_gvec_sar8i helper_gvec_sar8i_x86_64
|
||||
#define helper_gvec_sar16i helper_gvec_sar16i_x86_64
|
||||
#define helper_gvec_sar32i helper_gvec_sar32i_x86_64
|
||||
#define helper_gvec_sar64i helper_gvec_sar64i_x86_64
|
||||
#define helper_gvec_shl8i helper_gvec_shl8i_x86_64
|
||||
#define helper_gvec_shl16i helper_gvec_shl16i_x86_64
|
||||
#define helper_gvec_shl32i helper_gvec_shl32i_x86_64
|
||||
#define helper_gvec_shl64i helper_gvec_shl64i_x86_64
|
||||
#define helper_gvec_shr8i helper_gvec_shr8i_x86_64
|
||||
#define helper_gvec_shr16i helper_gvec_shr16i_x86_64
|
||||
#define helper_gvec_shr32i helper_gvec_shr32i_x86_64
|
||||
#define helper_gvec_shr64i helper_gvec_shr64i_x86_64
|
||||
#define helper_gvec_sub8 helper_gvec_sub8_x86_64
|
||||
#define helper_gvec_sub16 helper_gvec_sub16_x86_64
|
||||
#define helper_gvec_sub32 helper_gvec_sub32_x86_64
|
||||
|
|
@ -3114,6 +3126,7 @@
|
|||
#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_x86_64
|
||||
#define tcg_gen_goto_tb tcg_gen_goto_tb_x86_64
|
||||
#define tcg_gen_gvec_2 tcg_gen_gvec_2_x86_64
|
||||
#define tcg_gen_gvec_2i tcg_gen_gvec_2i_x86_64
|
||||
#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_x86_64
|
||||
#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_x86_64
|
||||
#define tcg_gen_gvec_3 tcg_gen_gvec_3_x86_64
|
||||
|
|
@ -3138,6 +3151,9 @@
|
|||
#define tcg_gen_gvec_not tcg_gen_gvec_not_x86_64
|
||||
#define tcg_gen_gvec_or tcg_gen_gvec_or_x86_64
|
||||
#define tcg_gen_gvec_orc tcg_gen_gvec_orc_x86_64
|
||||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_x86_64
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_x86_64
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_x86_64
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_x86_64
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_x86_64
|
||||
#define tcg_gen_insn_start tcg_gen_insn_start_x86_64
|
||||
|
|
@ -3231,6 +3247,7 @@
|
|||
#define tcg_gen_sar_i64 tcg_gen_sar_i64_x86_64
|
||||
#define tcg_gen_sari_i32 tcg_gen_sari_i32_x86_64
|
||||
#define tcg_gen_sari_i64 tcg_gen_sari_i64_x86_64
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||||
#define tcg_gen_sari_vec tcg_gen_sari_vec_x86_64
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||||
#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_x86_64
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||||
#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_x86_64
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||||
#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_x86_64
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||||
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@ -3242,10 +3259,12 @@
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#define tcg_gen_shl_i64 tcg_gen_shl_i64_x86_64
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||||
#define tcg_gen_shli_i32 tcg_gen_shli_i32_x86_64
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||||
#define tcg_gen_shli_i64 tcg_gen_shli_i64_x86_64
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||||
#define tcg_gen_shli_vec tcg_gen_shli_vec_x86_64
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||||
#define tcg_gen_shr_i32 tcg_gen_shr_i32_x86_64
|
||||
#define tcg_gen_shr_i64 tcg_gen_shr_i64_x86_64
|
||||
#define tcg_gen_shri_i32 tcg_gen_shri_i32_x86_64
|
||||
#define tcg_gen_shri_i64 tcg_gen_shri_i64_x86_64
|
||||
#define tcg_gen_shri_vec tcg_gen_shri_vec_x86_64
|
||||
#define tcg_gen_st_i32 tcg_gen_st_i32_x86_64
|
||||
#define tcg_gen_st_i64 tcg_gen_st_i64_x86_64
|
||||
#define tcg_gen_st_vec tcg_gen_st_vec_x86_64
|
||||
|
|
@ -3265,6 +3284,12 @@
|
|||
#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_x86_64
|
||||
#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_x86_64
|
||||
#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_x86_64
|
||||
#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_x86_64
|
||||
#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_x86_64
|
||||
#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_x86_64
|
||||
#define tcg_gen_vec_shl16i_i64 tcg_gen_vec_shl16i_i64_x86_64
|
||||
#define tcg_gen_vec_shr8i_i64 tcg_gen_vec_shr8i_i64_x86_64
|
||||
#define tcg_gen_vec_shr16i_i64 tcg_gen_vec_shr16i_i64_x86_64
|
||||
#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_x86_64
|
||||
#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_x86_64
|
||||
#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_x86_64
|
||||
|
|
|
|||
Loading…
Reference in a new issue