mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2025-01-08 22:35:35 +00:00
tcg: Add generic helpers for saturating arithmetic
No vector ops as yet. SSE only has direct support for 8- and 16-bit saturation; handling 32- and 64-bit saturation is much more expensive. Backports commit f49b12c6e6a75a5bd109bcbbda072b24e5fb8dfd from qemu
This commit is contained in:
Richard Henderson
Lioncash
parent
ab8579123e
commit
57bdf0faa2
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@ -1671,6 +1671,22 @@
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#define helper_gvec_sub16 helper_gvec_sub16_aarch64
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#define helper_gvec_sub32 helper_gvec_sub32_aarch64
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#define helper_gvec_sub64 helper_gvec_sub64_aarch64
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#define helper_gvec_ssadd8 helper_gvec_ssadd8_aarch64
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#define helper_gvec_ssadd16 helper_gvec_ssadd16_aarch64
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#define helper_gvec_ssadd32 helper_gvec_ssadd32_aarch64
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#define helper_gvec_ssadd64 helper_gvec_ssadd64_aarch64
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#define helper_gvec_sssub8 helper_gvec_sssub8_aarch64
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#define helper_gvec_sssub16 helper_gvec_sssub16_aarch64
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#define helper_gvec_sssub32 helper_gvec_sssub32_aarch64
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#define helper_gvec_sssub64 helper_gvec_sssub64_aarch64
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#define helper_gvec_usadd8 helper_gvec_usadd8_aarch64
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#define helper_gvec_usadd16 helper_gvec_usadd16_aarch64
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#define helper_gvec_usadd32 helper_gvec_usadd32_aarch64
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#define helper_gvec_usadd64 helper_gvec_usadd64_aarch64
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#define helper_gvec_ussub8 helper_gvec_ussub8_aarch64
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#define helper_gvec_ussub16 helper_gvec_ussub16_aarch64
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#define helper_gvec_ussub32 helper_gvec_ussub32_aarch64
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#define helper_gvec_ussub64 helper_gvec_ussub64_aarch64
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#define helper_gvec_xor helper_gvec_xor_aarch64
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#define helper_iwmmxt_addcb helper_iwmmxt_addcb_aarch64
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#define helper_iwmmxt_addcl helper_iwmmxt_addcl_aarch64
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@ -3185,7 +3201,11 @@
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#define tcg_gen_gvec_sari tcg_gen_gvec_sari_aarch64
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#define tcg_gen_gvec_shli tcg_gen_gvec_shli_aarch64
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#define tcg_gen_gvec_shri tcg_gen_gvec_shri_aarch64
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#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_aarch64
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#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_aarch64
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#define tcg_gen_gvec_sub tcg_gen_gvec_sub_aarch64
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#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_aarch64
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#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_aarch64
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#define tcg_gen_gvec_xor tcg_gen_gvec_xor_aarch64
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#define tcg_gen_insn_start tcg_gen_insn_start_aarch64
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#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_aarch64
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@ -1671,6 +1671,22 @@
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#define helper_gvec_sub16 helper_gvec_sub16_aarch64eb
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#define helper_gvec_sub32 helper_gvec_sub32_aarch64eb
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#define helper_gvec_sub64 helper_gvec_sub64_aarch64eb
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#define helper_gvec_ssadd8 helper_gvec_ssadd8_aarch64eb
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#define helper_gvec_ssadd16 helper_gvec_ssadd16_aarch64eb
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#define helper_gvec_ssadd32 helper_gvec_ssadd32_aarch64eb
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#define helper_gvec_ssadd64 helper_gvec_ssadd64_aarch64eb
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#define helper_gvec_sssub8 helper_gvec_sssub8_aarch64eb
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#define helper_gvec_sssub16 helper_gvec_sssub16_aarch64eb
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#define helper_gvec_sssub32 helper_gvec_sssub32_aarch64eb
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#define helper_gvec_sssub64 helper_gvec_sssub64_aarch64eb
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#define helper_gvec_usadd8 helper_gvec_usadd8_aarch64eb
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#define helper_gvec_usadd16 helper_gvec_usadd16_aarch64eb
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#define helper_gvec_usadd32 helper_gvec_usadd32_aarch64eb
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#define helper_gvec_usadd64 helper_gvec_usadd64_aarch64eb
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#define helper_gvec_ussub8 helper_gvec_ussub8_aarch64eb
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#define helper_gvec_ussub16 helper_gvec_ussub16_aarch64eb
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#define helper_gvec_ussub32 helper_gvec_ussub32_aarch64eb
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#define helper_gvec_ussub64 helper_gvec_ussub64_aarch64eb
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#define helper_gvec_xor helper_gvec_xor_aarch64eb
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#define helper_iwmmxt_addcb helper_iwmmxt_addcb_aarch64eb
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#define helper_iwmmxt_addcl helper_iwmmxt_addcl_aarch64eb
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@ -3185,7 +3201,11 @@
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#define tcg_gen_gvec_sari tcg_gen_gvec_sari_aarch64eb
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#define tcg_gen_gvec_shli tcg_gen_gvec_shli_aarch64eb
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#define tcg_gen_gvec_shri tcg_gen_gvec_shri_aarch64eb
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#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_aarch64eb
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#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_aarch64eb
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#define tcg_gen_gvec_sub tcg_gen_gvec_sub_aarch64eb
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#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_aarch64eb
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#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_aarch64eb
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#define tcg_gen_gvec_xor tcg_gen_gvec_xor_aarch64eb
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#define tcg_gen_insn_start tcg_gen_insn_start_aarch64eb
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#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_aarch64eb
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20
qemu/arm.h
20
qemu/arm.h
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@ -1671,6 +1671,22 @@
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#define helper_gvec_sub16 helper_gvec_sub16_arm
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#define helper_gvec_sub32 helper_gvec_sub32_arm
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#define helper_gvec_sub64 helper_gvec_sub64_arm
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#define helper_gvec_ssadd8 helper_gvec_ssadd8_arm
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#define helper_gvec_ssadd16 helper_gvec_ssadd16_arm
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#define helper_gvec_ssadd32 helper_gvec_ssadd32_arm
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#define helper_gvec_ssadd64 helper_gvec_ssadd64_arm
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#define helper_gvec_sssub8 helper_gvec_sssub8_arm
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#define helper_gvec_sssub16 helper_gvec_sssub16_arm
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#define helper_gvec_sssub32 helper_gvec_sssub32_arm
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#define helper_gvec_sssub64 helper_gvec_sssub64_arm
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#define helper_gvec_usadd8 helper_gvec_usadd8_arm
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#define helper_gvec_usadd16 helper_gvec_usadd16_arm
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#define helper_gvec_usadd32 helper_gvec_usadd32_arm
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#define helper_gvec_usadd64 helper_gvec_usadd64_arm
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#define helper_gvec_ussub8 helper_gvec_ussub8_arm
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#define helper_gvec_ussub16 helper_gvec_ussub16_arm
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#define helper_gvec_ussub32 helper_gvec_ussub32_arm
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#define helper_gvec_ussub64 helper_gvec_ussub64_arm
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#define helper_gvec_xor helper_gvec_xor_arm
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#define helper_iwmmxt_addcb helper_iwmmxt_addcb_arm
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#define helper_iwmmxt_addcl helper_iwmmxt_addcl_arm
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@ -3185,7 +3201,11 @@
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#define tcg_gen_gvec_sari tcg_gen_gvec_sari_arm
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#define tcg_gen_gvec_shli tcg_gen_gvec_shli_arm
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#define tcg_gen_gvec_shri tcg_gen_gvec_shri_arm
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#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_arm
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#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_arm
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#define tcg_gen_gvec_sub tcg_gen_gvec_sub_arm
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#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_arm
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#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_arm
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#define tcg_gen_gvec_xor tcg_gen_gvec_xor_arm
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#define tcg_gen_insn_start tcg_gen_insn_start_arm
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#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_arm
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20
qemu/armeb.h
20
qemu/armeb.h
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@ -1671,6 +1671,22 @@
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#define helper_gvec_sub16 helper_gvec_sub16_armeb
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#define helper_gvec_sub32 helper_gvec_sub32_armeb
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#define helper_gvec_sub64 helper_gvec_sub64_armeb
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#define helper_gvec_ssadd8 helper_gvec_ssadd8_armeb
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#define helper_gvec_ssadd16 helper_gvec_ssadd16_armeb
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#define helper_gvec_ssadd32 helper_gvec_ssadd32_armeb
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#define helper_gvec_ssadd64 helper_gvec_ssadd64_armeb
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#define helper_gvec_sssub8 helper_gvec_sssub8_armeb
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#define helper_gvec_sssub16 helper_gvec_sssub16_armeb
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#define helper_gvec_sssub32 helper_gvec_sssub32_armeb
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#define helper_gvec_sssub64 helper_gvec_sssub64_armeb
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#define helper_gvec_usadd8 helper_gvec_usadd8_armeb
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#define helper_gvec_usadd16 helper_gvec_usadd16_armeb
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#define helper_gvec_usadd32 helper_gvec_usadd32_armeb
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#define helper_gvec_usadd64 helper_gvec_usadd64_armeb
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#define helper_gvec_ussub8 helper_gvec_ussub8_armeb
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#define helper_gvec_ussub16 helper_gvec_ussub16_armeb
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#define helper_gvec_ussub32 helper_gvec_ussub32_armeb
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#define helper_gvec_ussub64 helper_gvec_ussub64_armeb
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#define helper_gvec_xor helper_gvec_xor_armeb
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#define helper_iwmmxt_addcb helper_iwmmxt_addcb_armeb
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#define helper_iwmmxt_addcl helper_iwmmxt_addcl_armeb
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@ -3185,7 +3201,11 @@
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#define tcg_gen_gvec_sari tcg_gen_gvec_sari_armeb
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#define tcg_gen_gvec_shli tcg_gen_gvec_shli_armeb
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#define tcg_gen_gvec_shri tcg_gen_gvec_shri_armeb
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#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_armeb
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#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_armeb
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#define tcg_gen_gvec_sub tcg_gen_gvec_sub_armeb
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#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_armeb
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#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_armeb
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#define tcg_gen_gvec_xor tcg_gen_gvec_xor_armeb
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#define tcg_gen_insn_start tcg_gen_insn_start_armeb
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#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_armeb
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@ -1677,6 +1677,22 @@ symbols = (
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'helper_gvec_sub16',
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'helper_gvec_sub32',
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'helper_gvec_sub64',
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'helper_gvec_ssadd8',
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'helper_gvec_ssadd16',
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'helper_gvec_ssadd32',
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'helper_gvec_ssadd64',
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'helper_gvec_sssub8',
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'helper_gvec_sssub16',
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'helper_gvec_sssub32',
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'helper_gvec_sssub64',
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'helper_gvec_usadd8',
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'helper_gvec_usadd16',
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'helper_gvec_usadd32',
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'helper_gvec_usadd64',
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'helper_gvec_ussub8',
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'helper_gvec_ussub16',
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'helper_gvec_ussub32',
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'helper_gvec_ussub64',
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'helper_gvec_xor',
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'helper_iwmmxt_addcb',
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'helper_iwmmxt_addcl',
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@ -3191,7 +3207,11 @@ symbols = (
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'tcg_gen_gvec_sari',
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'tcg_gen_gvec_shli',
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'tcg_gen_gvec_shri',
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'tcg_gen_gvec_ssadd',
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'tcg_gen_gvec_sssub',
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'tcg_gen_gvec_sub',
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'tcg_gen_gvec_usadd',
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'tcg_gen_gvec_ussub',
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'tcg_gen_gvec_xor',
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'tcg_gen_insn_start',
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'tcg_gen_ld16s_i64',
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20
qemu/m68k.h
20
qemu/m68k.h
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@ -1671,6 +1671,22 @@
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#define helper_gvec_sub16 helper_gvec_sub16_m68k
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#define helper_gvec_sub32 helper_gvec_sub32_m68k
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#define helper_gvec_sub64 helper_gvec_sub64_m68k
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#define helper_gvec_ssadd8 helper_gvec_ssadd8_m68k
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#define helper_gvec_ssadd16 helper_gvec_ssadd16_m68k
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#define helper_gvec_ssadd32 helper_gvec_ssadd32_m68k
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#define helper_gvec_ssadd64 helper_gvec_ssadd64_m68k
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#define helper_gvec_sssub8 helper_gvec_sssub8_m68k
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#define helper_gvec_sssub16 helper_gvec_sssub16_m68k
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#define helper_gvec_sssub32 helper_gvec_sssub32_m68k
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#define helper_gvec_sssub64 helper_gvec_sssub64_m68k
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#define helper_gvec_usadd8 helper_gvec_usadd8_m68k
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#define helper_gvec_usadd16 helper_gvec_usadd16_m68k
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#define helper_gvec_usadd32 helper_gvec_usadd32_m68k
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#define helper_gvec_usadd64 helper_gvec_usadd64_m68k
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#define helper_gvec_ussub8 helper_gvec_ussub8_m68k
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#define helper_gvec_ussub16 helper_gvec_ussub16_m68k
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#define helper_gvec_ussub32 helper_gvec_ussub32_m68k
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#define helper_gvec_ussub64 helper_gvec_ussub64_m68k
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#define helper_gvec_xor helper_gvec_xor_m68k
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#define helper_iwmmxt_addcb helper_iwmmxt_addcb_m68k
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#define helper_iwmmxt_addcl helper_iwmmxt_addcl_m68k
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@ -3185,7 +3201,11 @@
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#define tcg_gen_gvec_sari tcg_gen_gvec_sari_m68k
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#define tcg_gen_gvec_shli tcg_gen_gvec_shli_m68k
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#define tcg_gen_gvec_shri tcg_gen_gvec_shri_m68k
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#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_m68k
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#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_m68k
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#define tcg_gen_gvec_sub tcg_gen_gvec_sub_m68k
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#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_m68k
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#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_m68k
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#define tcg_gen_gvec_xor tcg_gen_gvec_xor_m68k
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#define tcg_gen_insn_start tcg_gen_insn_start_m68k
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#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_m68k
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20
qemu/mips.h
20
qemu/mips.h
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@ -1671,6 +1671,22 @@
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#define helper_gvec_sub16 helper_gvec_sub16_mips
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#define helper_gvec_sub32 helper_gvec_sub32_mips
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#define helper_gvec_sub64 helper_gvec_sub64_mips
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#define helper_gvec_ssadd8 helper_gvec_ssadd8_mips
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#define helper_gvec_ssadd16 helper_gvec_ssadd16_mips
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#define helper_gvec_ssadd32 helper_gvec_ssadd32_mips
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#define helper_gvec_ssadd64 helper_gvec_ssadd64_mips
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#define helper_gvec_sssub8 helper_gvec_sssub8_mips
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#define helper_gvec_sssub16 helper_gvec_sssub16_mips
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#define helper_gvec_sssub32 helper_gvec_sssub32_mips
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#define helper_gvec_sssub64 helper_gvec_sssub64_mips
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#define helper_gvec_usadd8 helper_gvec_usadd8_mips
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#define helper_gvec_usadd16 helper_gvec_usadd16_mips
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#define helper_gvec_usadd32 helper_gvec_usadd32_mips
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#define helper_gvec_usadd64 helper_gvec_usadd64_mips
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#define helper_gvec_ussub8 helper_gvec_ussub8_mips
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#define helper_gvec_ussub16 helper_gvec_ussub16_mips
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#define helper_gvec_ussub32 helper_gvec_ussub32_mips
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#define helper_gvec_ussub64 helper_gvec_ussub64_mips
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#define helper_gvec_xor helper_gvec_xor_mips
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#define helper_iwmmxt_addcb helper_iwmmxt_addcb_mips
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#define helper_iwmmxt_addcl helper_iwmmxt_addcl_mips
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@ -3185,7 +3201,11 @@
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#define tcg_gen_gvec_sari tcg_gen_gvec_sari_mips
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#define tcg_gen_gvec_shli tcg_gen_gvec_shli_mips
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#define tcg_gen_gvec_shri tcg_gen_gvec_shri_mips
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#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_mips
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#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_mips
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#define tcg_gen_gvec_sub tcg_gen_gvec_sub_mips
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#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_mips
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#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_mips
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#define tcg_gen_gvec_xor tcg_gen_gvec_xor_mips
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#define tcg_gen_insn_start tcg_gen_insn_start_mips
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#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mips
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@ -1671,6 +1671,22 @@
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#define helper_gvec_sub16 helper_gvec_sub16_mips64
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#define helper_gvec_sub32 helper_gvec_sub32_mips64
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#define helper_gvec_sub64 helper_gvec_sub64_mips64
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#define helper_gvec_ssadd8 helper_gvec_ssadd8_mips64
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#define helper_gvec_ssadd16 helper_gvec_ssadd16_mips64
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#define helper_gvec_ssadd32 helper_gvec_ssadd32_mips64
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#define helper_gvec_ssadd64 helper_gvec_ssadd64_mips64
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#define helper_gvec_sssub8 helper_gvec_sssub8_mips64
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#define helper_gvec_sssub16 helper_gvec_sssub16_mips64
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#define helper_gvec_sssub32 helper_gvec_sssub32_mips64
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#define helper_gvec_sssub64 helper_gvec_sssub64_mips64
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#define helper_gvec_usadd8 helper_gvec_usadd8_mips64
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#define helper_gvec_usadd16 helper_gvec_usadd16_mips64
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#define helper_gvec_usadd32 helper_gvec_usadd32_mips64
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#define helper_gvec_usadd64 helper_gvec_usadd64_mips64
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#define helper_gvec_ussub8 helper_gvec_ussub8_mips64
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#define helper_gvec_ussub16 helper_gvec_ussub16_mips64
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||||
#define helper_gvec_ussub32 helper_gvec_ussub32_mips64
|
||||
#define helper_gvec_ussub64 helper_gvec_ussub64_mips64
|
||||
#define helper_gvec_xor helper_gvec_xor_mips64
|
||||
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_mips64
|
||||
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_mips64
|
||||
|
|
@ -3185,7 +3201,11 @@
|
|||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_mips64
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_mips64
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_mips64
|
||||
#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_mips64
|
||||
#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_mips64
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_mips64
|
||||
#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_mips64
|
||||
#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_mips64
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_mips64
|
||||
#define tcg_gen_insn_start tcg_gen_insn_start_mips64
|
||||
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mips64
|
||||
|
|
|
|||
|
|
@ -1671,6 +1671,22 @@
|
|||
#define helper_gvec_sub16 helper_gvec_sub16_mips64el
|
||||
#define helper_gvec_sub32 helper_gvec_sub32_mips64el
|
||||
#define helper_gvec_sub64 helper_gvec_sub64_mips64el
|
||||
#define helper_gvec_ssadd8 helper_gvec_ssadd8_mips64el
|
||||
#define helper_gvec_ssadd16 helper_gvec_ssadd16_mips64el
|
||||
#define helper_gvec_ssadd32 helper_gvec_ssadd32_mips64el
|
||||
#define helper_gvec_ssadd64 helper_gvec_ssadd64_mips64el
|
||||
#define helper_gvec_sssub8 helper_gvec_sssub8_mips64el
|
||||
#define helper_gvec_sssub16 helper_gvec_sssub16_mips64el
|
||||
#define helper_gvec_sssub32 helper_gvec_sssub32_mips64el
|
||||
#define helper_gvec_sssub64 helper_gvec_sssub64_mips64el
|
||||
#define helper_gvec_usadd8 helper_gvec_usadd8_mips64el
|
||||
#define helper_gvec_usadd16 helper_gvec_usadd16_mips64el
|
||||
#define helper_gvec_usadd32 helper_gvec_usadd32_mips64el
|
||||
#define helper_gvec_usadd64 helper_gvec_usadd64_mips64el
|
||||
#define helper_gvec_ussub8 helper_gvec_ussub8_mips64el
|
||||
#define helper_gvec_ussub16 helper_gvec_ussub16_mips64el
|
||||
#define helper_gvec_ussub32 helper_gvec_ussub32_mips64el
|
||||
#define helper_gvec_ussub64 helper_gvec_ussub64_mips64el
|
||||
#define helper_gvec_xor helper_gvec_xor_mips64el
|
||||
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_mips64el
|
||||
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_mips64el
|
||||
|
|
@ -3185,7 +3201,11 @@
|
|||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_mips64el
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_mips64el
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_mips64el
|
||||
#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_mips64el
|
||||
#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_mips64el
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_mips64el
|
||||
#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_mips64el
|
||||
#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_mips64el
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_mips64el
|
||||
#define tcg_gen_insn_start tcg_gen_insn_start_mips64el
|
||||
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mips64el
|
||||
|
|
|
|||
|
|
@ -1671,6 +1671,22 @@
|
|||
#define helper_gvec_sub16 helper_gvec_sub16_mipsel
|
||||
#define helper_gvec_sub32 helper_gvec_sub32_mipsel
|
||||
#define helper_gvec_sub64 helper_gvec_sub64_mipsel
|
||||
#define helper_gvec_ssadd8 helper_gvec_ssadd8_mipsel
|
||||
#define helper_gvec_ssadd16 helper_gvec_ssadd16_mipsel
|
||||
#define helper_gvec_ssadd32 helper_gvec_ssadd32_mipsel
|
||||
#define helper_gvec_ssadd64 helper_gvec_ssadd64_mipsel
|
||||
#define helper_gvec_sssub8 helper_gvec_sssub8_mipsel
|
||||
#define helper_gvec_sssub16 helper_gvec_sssub16_mipsel
|
||||
#define helper_gvec_sssub32 helper_gvec_sssub32_mipsel
|
||||
#define helper_gvec_sssub64 helper_gvec_sssub64_mipsel
|
||||
#define helper_gvec_usadd8 helper_gvec_usadd8_mipsel
|
||||
#define helper_gvec_usadd16 helper_gvec_usadd16_mipsel
|
||||
#define helper_gvec_usadd32 helper_gvec_usadd32_mipsel
|
||||
#define helper_gvec_usadd64 helper_gvec_usadd64_mipsel
|
||||
#define helper_gvec_ussub8 helper_gvec_ussub8_mipsel
|
||||
#define helper_gvec_ussub16 helper_gvec_ussub16_mipsel
|
||||
#define helper_gvec_ussub32 helper_gvec_ussub32_mipsel
|
||||
#define helper_gvec_ussub64 helper_gvec_ussub64_mipsel
|
||||
#define helper_gvec_xor helper_gvec_xor_mipsel
|
||||
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_mipsel
|
||||
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_mipsel
|
||||
|
|
@ -3185,7 +3201,11 @@
|
|||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_mipsel
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_mipsel
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_mipsel
|
||||
#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_mipsel
|
||||
#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_mipsel
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_mipsel
|
||||
#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_mipsel
|
||||
#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_mipsel
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_mipsel
|
||||
#define tcg_gen_insn_start tcg_gen_insn_start_mipsel
|
||||
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_mipsel
|
||||
|
|
|
|||
|
|
@ -1671,6 +1671,22 @@
|
|||
#define helper_gvec_sub16 helper_gvec_sub16_powerpc
|
||||
#define helper_gvec_sub32 helper_gvec_sub32_powerpc
|
||||
#define helper_gvec_sub64 helper_gvec_sub64_powerpc
|
||||
#define helper_gvec_ssadd8 helper_gvec_ssadd8_powerpc
|
||||
#define helper_gvec_ssadd16 helper_gvec_ssadd16_powerpc
|
||||
#define helper_gvec_ssadd32 helper_gvec_ssadd32_powerpc
|
||||
#define helper_gvec_ssadd64 helper_gvec_ssadd64_powerpc
|
||||
#define helper_gvec_sssub8 helper_gvec_sssub8_powerpc
|
||||
#define helper_gvec_sssub16 helper_gvec_sssub16_powerpc
|
||||
#define helper_gvec_sssub32 helper_gvec_sssub32_powerpc
|
||||
#define helper_gvec_sssub64 helper_gvec_sssub64_powerpc
|
||||
#define helper_gvec_usadd8 helper_gvec_usadd8_powerpc
|
||||
#define helper_gvec_usadd16 helper_gvec_usadd16_powerpc
|
||||
#define helper_gvec_usadd32 helper_gvec_usadd32_powerpc
|
||||
#define helper_gvec_usadd64 helper_gvec_usadd64_powerpc
|
||||
#define helper_gvec_ussub8 helper_gvec_ussub8_powerpc
|
||||
#define helper_gvec_ussub16 helper_gvec_ussub16_powerpc
|
||||
#define helper_gvec_ussub32 helper_gvec_ussub32_powerpc
|
||||
#define helper_gvec_ussub64 helper_gvec_ussub64_powerpc
|
||||
#define helper_gvec_xor helper_gvec_xor_powerpc
|
||||
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_powerpc
|
||||
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_powerpc
|
||||
|
|
@ -3185,7 +3201,11 @@
|
|||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_powerpc
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_powerpc
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_powerpc
|
||||
#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_powerpc
|
||||
#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_powerpc
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_powerpc
|
||||
#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_powerpc
|
||||
#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_powerpc
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_powerpc
|
||||
#define tcg_gen_insn_start tcg_gen_insn_start_powerpc
|
||||
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_powerpc
|
||||
|
|
|
|||
20
qemu/sparc.h
20
qemu/sparc.h
|
|
@ -1671,6 +1671,22 @@
|
|||
#define helper_gvec_sub16 helper_gvec_sub16_sparc
|
||||
#define helper_gvec_sub32 helper_gvec_sub32_sparc
|
||||
#define helper_gvec_sub64 helper_gvec_sub64_sparc
|
||||
#define helper_gvec_ssadd8 helper_gvec_ssadd8_sparc
|
||||
#define helper_gvec_ssadd16 helper_gvec_ssadd16_sparc
|
||||
#define helper_gvec_ssadd32 helper_gvec_ssadd32_sparc
|
||||
#define helper_gvec_ssadd64 helper_gvec_ssadd64_sparc
|
||||
#define helper_gvec_sssub8 helper_gvec_sssub8_sparc
|
||||
#define helper_gvec_sssub16 helper_gvec_sssub16_sparc
|
||||
#define helper_gvec_sssub32 helper_gvec_sssub32_sparc
|
||||
#define helper_gvec_sssub64 helper_gvec_sssub64_sparc
|
||||
#define helper_gvec_usadd8 helper_gvec_usadd8_sparc
|
||||
#define helper_gvec_usadd16 helper_gvec_usadd16_sparc
|
||||
#define helper_gvec_usadd32 helper_gvec_usadd32_sparc
|
||||
#define helper_gvec_usadd64 helper_gvec_usadd64_sparc
|
||||
#define helper_gvec_ussub8 helper_gvec_ussub8_sparc
|
||||
#define helper_gvec_ussub16 helper_gvec_ussub16_sparc
|
||||
#define helper_gvec_ussub32 helper_gvec_ussub32_sparc
|
||||
#define helper_gvec_ussub64 helper_gvec_ussub64_sparc
|
||||
#define helper_gvec_xor helper_gvec_xor_sparc
|
||||
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_sparc
|
||||
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_sparc
|
||||
|
|
@ -3185,7 +3201,11 @@
|
|||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_sparc
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_sparc
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_sparc
|
||||
#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_sparc
|
||||
#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_sparc
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_sparc
|
||||
#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_sparc
|
||||
#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_sparc
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_sparc
|
||||
#define tcg_gen_insn_start tcg_gen_insn_start_sparc
|
||||
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_sparc
|
||||
|
|
|
|||
|
|
@ -1671,6 +1671,22 @@
|
|||
#define helper_gvec_sub16 helper_gvec_sub16_sparc64
|
||||
#define helper_gvec_sub32 helper_gvec_sub32_sparc64
|
||||
#define helper_gvec_sub64 helper_gvec_sub64_sparc64
|
||||
#define helper_gvec_ssadd8 helper_gvec_ssadd8_sparc64
|
||||
#define helper_gvec_ssadd16 helper_gvec_ssadd16_sparc64
|
||||
#define helper_gvec_ssadd32 helper_gvec_ssadd32_sparc64
|
||||
#define helper_gvec_ssadd64 helper_gvec_ssadd64_sparc64
|
||||
#define helper_gvec_sssub8 helper_gvec_sssub8_sparc64
|
||||
#define helper_gvec_sssub16 helper_gvec_sssub16_sparc64
|
||||
#define helper_gvec_sssub32 helper_gvec_sssub32_sparc64
|
||||
#define helper_gvec_sssub64 helper_gvec_sssub64_sparc64
|
||||
#define helper_gvec_usadd8 helper_gvec_usadd8_sparc64
|
||||
#define helper_gvec_usadd16 helper_gvec_usadd16_sparc64
|
||||
#define helper_gvec_usadd32 helper_gvec_usadd32_sparc64
|
||||
#define helper_gvec_usadd64 helper_gvec_usadd64_sparc64
|
||||
#define helper_gvec_ussub8 helper_gvec_ussub8_sparc64
|
||||
#define helper_gvec_ussub16 helper_gvec_ussub16_sparc64
|
||||
#define helper_gvec_ussub32 helper_gvec_ussub32_sparc64
|
||||
#define helper_gvec_ussub64 helper_gvec_ussub64_sparc64
|
||||
#define helper_gvec_xor helper_gvec_xor_sparc64
|
||||
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_sparc64
|
||||
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_sparc64
|
||||
|
|
@ -3185,7 +3201,11 @@
|
|||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_sparc64
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_sparc64
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_sparc64
|
||||
#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_sparc64
|
||||
#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_sparc64
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_sparc64
|
||||
#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_sparc64
|
||||
#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_sparc64
|
||||
#define tcg_gen_gvec_xor tcg_gen_gvec_xor_sparc64
|
||||
#define tcg_gen_insn_start tcg_gen_insn_start_sparc64
|
||||
#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_sparc64
|
||||
|
|
|
|||
|
|
@ -547,3 +547,271 @@ DO_CMP2(64)
|
|||
#undef DO_CMP0
|
||||
#undef DO_CMP1
|
||||
#undef DO_CMP2
|
||||
|
||||
void HELPER(gvec_ssadd8)(void *d, void *a, void *b, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(int8_t)) {
|
||||
int r = *(int8_t *)(a + i) + *(int8_t *)(b + i);
|
||||
if (r > INT8_MAX) {
|
||||
r = INT8_MAX;
|
||||
} else if (r < INT8_MIN) {
|
||||
r = INT8_MIN;
|
||||
}
|
||||
*(int8_t *)(d + i) = r;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_ssadd16)(void *d, void *a, void *b, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(int16_t)) {
|
||||
int r = *(int16_t *)(a + i) + *(int16_t *)(b + i);
|
||||
if (r > INT16_MAX) {
|
||||
r = INT16_MAX;
|
||||
} else if (r < INT16_MIN) {
|
||||
r = INT16_MIN;
|
||||
}
|
||||
*(int16_t *)(d + i) = r;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_ssadd32)(void *d, void *a, void *b, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(int32_t)) {
|
||||
int32_t ai = *(int32_t *)(a + i);
|
||||
int32_t bi = *(int32_t *)(b + i);
|
||||
int32_t di = ai + bi;
|
||||
if (((di ^ ai) &~ (ai ^ bi)) < 0) {
|
||||
/* Signed overflow. */
|
||||
di = (di < 0 ? INT32_MAX : INT32_MIN);
|
||||
}
|
||||
*(int32_t *)(d + i) = di;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_ssadd64)(void *d, void *a, void *b, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(int64_t)) {
|
||||
int64_t ai = *(int64_t *)(a + i);
|
||||
int64_t bi = *(int64_t *)(b + i);
|
||||
int64_t di = ai + bi;
|
||||
if (((di ^ ai) &~ (ai ^ bi)) < 0) {
|
||||
/* Signed overflow. */
|
||||
di = (di < 0 ? INT64_MAX : INT64_MIN);
|
||||
}
|
||||
*(int64_t *)(d + i) = di;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_sssub8)(void *d, void *a, void *b, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
|
||||
int r = *(int8_t *)(a + i) - *(int8_t *)(b + i);
|
||||
if (r > INT8_MAX) {
|
||||
r = INT8_MAX;
|
||||
} else if (r < INT8_MIN) {
|
||||
r = INT8_MIN;
|
||||
}
|
||||
*(uint8_t *)(d + i) = r;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_sssub16)(void *d, void *a, void *b, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(int16_t)) {
|
||||
int r = *(int16_t *)(a + i) - *(int16_t *)(b + i);
|
||||
if (r > INT16_MAX) {
|
||||
r = INT16_MAX;
|
||||
} else if (r < INT16_MIN) {
|
||||
r = INT16_MIN;
|
||||
}
|
||||
*(int16_t *)(d + i) = r;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_sssub32)(void *d, void *a, void *b, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(int32_t)) {
|
||||
int32_t ai = *(int32_t *)(a + i);
|
||||
int32_t bi = *(int32_t *)(b + i);
|
||||
int32_t di = ai - bi;
|
||||
if (((di ^ ai) & (ai ^ bi)) < 0) {
|
||||
/* Signed overflow. */
|
||||
di = (di < 0 ? INT32_MAX : INT32_MIN);
|
||||
}
|
||||
*(int32_t *)(d + i) = di;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_sssub64)(void *d, void *a, void *b, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(int64_t)) {
|
||||
int64_t ai = *(int64_t *)(a + i);
|
||||
int64_t bi = *(int64_t *)(b + i);
|
||||
int64_t di = ai - bi;
|
||||
if (((di ^ ai) & (ai ^ bi)) < 0) {
|
||||
/* Signed overflow. */
|
||||
di = (di < 0 ? INT64_MAX : INT64_MIN);
|
||||
}
|
||||
*(int64_t *)(d + i) = di;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_usadd8)(void *d, void *a, void *b, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
|
||||
unsigned r = *(uint8_t *)(a + i) + *(uint8_t *)(b + i);
|
||||
if (r > UINT8_MAX) {
|
||||
r = UINT8_MAX;
|
||||
}
|
||||
*(uint8_t *)(d + i) = r;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_usadd16)(void *d, void *a, void *b, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
|
||||
unsigned r = *(uint16_t *)(a + i) + *(uint16_t *)(b + i);
|
||||
if (r > UINT16_MAX) {
|
||||
r = UINT16_MAX;
|
||||
}
|
||||
*(uint16_t *)(d + i) = r;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_usadd32)(void *d, void *a, void *b, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
|
||||
uint32_t ai = *(uint32_t *)(a + i);
|
||||
uint32_t bi = *(uint32_t *)(b + i);
|
||||
uint32_t di = ai + bi;
|
||||
if (di < ai) {
|
||||
di = UINT32_MAX;
|
||||
}
|
||||
*(uint32_t *)(d + i) = di;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_usadd64)(void *d, void *a, void *b, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
|
||||
uint64_t ai = *(uint64_t *)(a + i);
|
||||
uint64_t bi = *(uint64_t *)(b + i);
|
||||
uint64_t di = ai + bi;
|
||||
if (di < ai) {
|
||||
di = UINT64_MAX;
|
||||
}
|
||||
*(uint64_t *)(d + i) = di;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_ussub8)(void *d, void *a, void *b, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(uint8_t)) {
|
||||
int r = *(uint8_t *)(a + i) - *(uint8_t *)(b + i);
|
||||
if (r < 0) {
|
||||
r = 0;
|
||||
}
|
||||
*(uint8_t *)(d + i) = r;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_ussub16)(void *d, void *a, void *b, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(uint16_t)) {
|
||||
int r = *(uint16_t *)(a + i) - *(uint16_t *)(b + i);
|
||||
if (r < 0) {
|
||||
r = 0;
|
||||
}
|
||||
*(uint16_t *)(d + i) = r;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_ussub32)(void *d, void *a, void *b, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(uint32_t)) {
|
||||
uint32_t ai = *(uint32_t *)(a + i);
|
||||
uint32_t bi = *(uint32_t *)(b + i);
|
||||
uint32_t di = ai - bi;
|
||||
if (ai < bi) {
|
||||
di = 0;
|
||||
}
|
||||
*(uint32_t *)(d + i) = di;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
||||
void HELPER(gvec_ussub64)(void *d, void *a, void *b, uint32_t desc)
|
||||
{
|
||||
intptr_t oprsz = simd_oprsz(desc);
|
||||
intptr_t i;
|
||||
|
||||
for (i = 0; i < oprsz; i += sizeof(uint64_t)) {
|
||||
uint64_t ai = *(uint64_t *)(a + i);
|
||||
uint64_t bi = *(uint64_t *)(b + i);
|
||||
uint64_t di = ai - bi;
|
||||
if (ai < bi) {
|
||||
di = 0;
|
||||
}
|
||||
*(uint64_t *)(d + i) = di;
|
||||
}
|
||||
clear_high(d, oprsz, desc);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1310,6 +1310,98 @@ void tcg_gen_gvec_mul(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs
|
|||
tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
|
||||
}
|
||||
|
||||
void tcg_gen_gvec_ssadd(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
|
||||
{
|
||||
static const GVecGen3 g[4] = {
|
||||
{ .fno = gen_helper_gvec_ssadd8, .vece = MO_8 },
|
||||
{ .fno = gen_helper_gvec_ssadd16, .vece = MO_16 },
|
||||
{ .fno = gen_helper_gvec_ssadd32, .vece = MO_32 },
|
||||
{ .fno = gen_helper_gvec_ssadd64, .vece = MO_64 }
|
||||
};
|
||||
tcg_debug_assert(vece <= MO_64);
|
||||
tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
|
||||
}
|
||||
|
||||
void tcg_gen_gvec_sssub(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
|
||||
{
|
||||
static const GVecGen3 g[4] = {
|
||||
{ .fno = gen_helper_gvec_sssub8, .vece = MO_8 },
|
||||
{ .fno = gen_helper_gvec_sssub16, .vece = MO_16 },
|
||||
{ .fno = gen_helper_gvec_sssub32, .vece = MO_32 },
|
||||
{ .fno = gen_helper_gvec_sssub64, .vece = MO_64 }
|
||||
};
|
||||
tcg_debug_assert(vece <= MO_64);
|
||||
tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
|
||||
}
|
||||
|
||||
static void tcg_gen_vec_usadd32_i32(TCGContext *s, TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
|
||||
{
|
||||
TCGv_i32 max = tcg_const_i32(s, -1);
|
||||
tcg_gen_add_i32(s, d, a, b);
|
||||
tcg_gen_movcond_i32(s, TCG_COND_LTU, d, d, a, max, d);
|
||||
tcg_temp_free_i32(s, max);
|
||||
}
|
||||
|
||||
static void tcg_gen_vec_usadd32_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
|
||||
{
|
||||
TCGv_i64 max = tcg_const_i64(s, -1);
|
||||
tcg_gen_add_i64(s, d, a, b);
|
||||
tcg_gen_movcond_i64(s, TCG_COND_LTU, d, d, a, max, d);
|
||||
tcg_temp_free_i64(s, max);
|
||||
}
|
||||
|
||||
void tcg_gen_gvec_usadd(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
|
||||
{
|
||||
static const GVecGen3 g[4] = {
|
||||
{ .fno = gen_helper_gvec_usadd8, .vece = MO_8 },
|
||||
{ .fno = gen_helper_gvec_usadd16, .vece = MO_16 },
|
||||
{ .fni4 = tcg_gen_vec_usadd32_i32,
|
||||
.fno = gen_helper_gvec_usadd32,
|
||||
.vece = MO_32 },
|
||||
{ .fni8 = tcg_gen_vec_usadd32_i64,
|
||||
.fno = gen_helper_gvec_usadd64,
|
||||
.vece = MO_64 }
|
||||
};
|
||||
tcg_debug_assert(vece <= MO_64);
|
||||
tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
|
||||
}
|
||||
|
||||
static void tcg_gen_vec_ussub32_i32(TCGContext *s, TCGv_i32 d, TCGv_i32 a, TCGv_i32 b)
|
||||
{
|
||||
TCGv_i32 min = tcg_const_i32(s, 0);
|
||||
tcg_gen_sub_i32(s, d, a, b);
|
||||
tcg_gen_movcond_i32(s, TCG_COND_LTU, d, a, b, min, d);
|
||||
tcg_temp_free_i32(s, min);
|
||||
}
|
||||
|
||||
static void tcg_gen_vec_ussub32_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
|
||||
{
|
||||
TCGv_i64 min = tcg_const_i64(s, 0);
|
||||
tcg_gen_sub_i64(s, d, a, b);
|
||||
tcg_gen_movcond_i64(s, TCG_COND_LTU, d, a, b, min, d);
|
||||
tcg_temp_free_i64(s, min);
|
||||
}
|
||||
|
||||
void tcg_gen_gvec_ussub(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
|
||||
{
|
||||
static const GVecGen3 g[4] = {
|
||||
{ .fno = gen_helper_gvec_ussub8, .vece = MO_8 },
|
||||
{ .fno = gen_helper_gvec_ussub16, .vece = MO_16 },
|
||||
{ .fni4 = tcg_gen_vec_ussub32_i32,
|
||||
.fno = gen_helper_gvec_ussub32,
|
||||
.vece = MO_32 },
|
||||
{ .fni8 = tcg_gen_vec_ussub32_i64,
|
||||
.fno = gen_helper_gvec_ussub64,
|
||||
.vece = MO_64 }
|
||||
};
|
||||
tcg_debug_assert(vece <= MO_64);
|
||||
tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g[vece]);
|
||||
}
|
||||
|
||||
/* Perform a vector negation using normal negation and a mask.
|
||||
Compare gen_subv_mask above. */
|
||||
static void gen_negv_mask(TCGContext *s, TCGv_i64 d, TCGv_i64 b, TCGv_i64 m)
|
||||
|
|
|
|||
|
|
@ -179,6 +179,16 @@ void tcg_gen_gvec_sub(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
|
|||
void tcg_gen_gvec_mul(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
|
||||
|
||||
/* Saturated arithmetic. */
|
||||
void tcg_gen_gvec_ssadd(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
|
||||
void tcg_gen_gvec_sssub(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
|
||||
void tcg_gen_gvec_usadd(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
|
||||
void tcg_gen_gvec_ussub(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
|
||||
|
||||
void tcg_gen_gvec_and(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
|
||||
void tcg_gen_gvec_or(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
|
||||
|
|
|
|||
|
|
@ -163,6 +163,26 @@ DEF_HELPER_FLAGS_3(gvec_neg16, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
|
|||
DEF_HELPER_FLAGS_3(gvec_neg32, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_3(gvec_neg64, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(gvec_ssadd8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_ssadd16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_ssadd32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_ssadd64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(gvec_sssub8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_sssub16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_sssub32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_sssub64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(gvec_usadd8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_usadd16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_usadd32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_usadd64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_4(gvec_ussub8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_ussub16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_ussub32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_ussub64, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
|
||||
DEF_HELPER_FLAGS_3(gvec_not, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_and, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
DEF_HELPER_FLAGS_4(gvec_or, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
|
||||
|
|
|
|||
|
|
@ -1671,6 +1671,22 @@
|
|||
#define helper_gvec_sub16 helper_gvec_sub16_x86_64
|
||||
#define helper_gvec_sub32 helper_gvec_sub32_x86_64
|
||||
#define helper_gvec_sub64 helper_gvec_sub64_x86_64
|
||||
#define helper_gvec_ssadd8 helper_gvec_ssadd8_x86_64
|
||||
#define helper_gvec_ssadd16 helper_gvec_ssadd16_x86_64
|
||||
#define helper_gvec_ssadd32 helper_gvec_ssadd32_x86_64
|
||||
#define helper_gvec_ssadd64 helper_gvec_ssadd64_x86_64
|
||||
#define helper_gvec_sssub8 helper_gvec_sssub8_x86_64
|
||||
#define helper_gvec_sssub16 helper_gvec_sssub16_x86_64
|
||||
#define helper_gvec_sssub32 helper_gvec_sssub32_x86_64
|
||||
#define helper_gvec_sssub64 helper_gvec_sssub64_x86_64
|
||||
#define helper_gvec_usadd8 helper_gvec_usadd8_x86_64
|
||||
#define helper_gvec_usadd16 helper_gvec_usadd16_x86_64
|
||||
#define helper_gvec_usadd32 helper_gvec_usadd32_x86_64
|
||||
#define helper_gvec_usadd64 helper_gvec_usadd64_x86_64
|
||||
#define helper_gvec_ussub8 helper_gvec_ussub8_x86_64
|
||||
#define helper_gvec_ussub16 helper_gvec_ussub16_x86_64
|
||||
#define helper_gvec_ussub32 helper_gvec_ussub32_x86_64
|
||||
#define helper_gvec_ussub64 helper_gvec_ussub64_x86_64
|
||||
#define helper_gvec_xor helper_gvec_xor_x86_64
|
||||
#define helper_iwmmxt_addcb helper_iwmmxt_addcb_x86_64
|
||||
#define helper_iwmmxt_addcl helper_iwmmxt_addcl_x86_64
|
||||
|
|
@ -3185,7 +3201,11 @@
|
|||
#define tcg_gen_gvec_sari tcg_gen_gvec_sari_x86_64
|
||||
#define tcg_gen_gvec_shli tcg_gen_gvec_shli_x86_64
|
||||
#define tcg_gen_gvec_shri tcg_gen_gvec_shri_x86_64
|
||||
#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_x86_64
|
||||
#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_x86_64
|
||||
#define tcg_gen_gvec_sub tcg_gen_gvec_sub_x86_64
|
||||
#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_x86_64
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#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_x86_64
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#define tcg_gen_gvec_xor tcg_gen_gvec_xor_x86_64
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#define tcg_gen_insn_start tcg_gen_insn_start_x86_64
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#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_x86_64
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Reference in a new issue