mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2025-01-03 17:45:47 +00:00
target/riscv: vector single-width integer multiply-add instructions
Backports 54df813a331d3badfb83604c36bef7cb1de4315a
This commit is contained in:
parent
436e092e36
commit
58891e213d
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@ -6773,6 +6773,38 @@ riscv_symbols = (
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'helpet_vwmulsu_vx_b',
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'helpet_vwmulsu_vx_h',
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'helpet_vwmulsu_vx_w',
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'helper_vmacc_vv_b',
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'helper_vmacc_vv_h',
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'helper_vmacc_vv_w',
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'helper_vmacc_vv_d',
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'helper_vnmsac_vv_b',
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'helper_vnmsac_vv_h',
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'helper_vnmsac_vv_w',
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'helper_vnmsac_vv_d',
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'helper_vmadd_vv_b',
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'helper_vmadd_vv_h',
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'helper_vmadd_vv_w',
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'helper_vmadd_vv_d',
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'helper_vnmsub_vv_b',
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'helper_vnmsub_vv_h',
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'helper_vnmsub_vv_w',
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'helper_vnmsub_vv_d',
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'helper_vmacc_vx_b',
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'helper_vmacc_vx_h',
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'helper_vmacc_vx_w',
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'helper_vmacc_vx_d',
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'helper_vnmsac_vx_b',
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'helper_vnmsac_vx_h',
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'helper_vnmsac_vx_w',
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'helper_vnmsac_vx_d',
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'helper_vmadd_vx_b',
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'helper_vmadd_vx_h',
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'helper_vmadd_vx_w',
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'helper_vmadd_vx_d',
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'helper_vnmsub_vx_b',
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'helper_vnmsub_vx_h',
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'helper_vnmsub_vx_w',
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'helper_vnmsub_vx_d',
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'pmp_hart_has_privs',
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'pmpaddr_csr_read',
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'pmpaddr_csr_write',
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@ -4209,6 +4209,38 @@
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#define helpet_vwmulsu_vx_b helpet_vwmulsu_vx_b_riscv32
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#define helpet_vwmulsu_vx_h helpet_vwmulsu_vx_h_riscv32
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#define helpet_vwmulsu_vx_w helpet_vwmulsu_vx_w_riscv32
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#define helper_vmacc_vv_b helper_vmacc_vv_b_riscv32
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#define helper_vmacc_vv_h helper_vmacc_vv_h_riscv32
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#define helper_vmacc_vv_w helper_vmacc_vv_w_riscv32
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#define helper_vmacc_vv_d helper_vmacc_vv_d_riscv32
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#define helper_vnmsac_vv_b helper_vnmsac_vv_b_riscv32
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#define helper_vnmsac_vv_h helper_vnmsac_vv_h_riscv32
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#define helper_vnmsac_vv_w helper_vnmsac_vv_w_riscv32
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#define helper_vnmsac_vv_d helper_vnmsac_vv_d_riscv32
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#define helper_vmadd_vv_b helper_vmadd_vv_b_riscv32
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#define helper_vmadd_vv_h helper_vmadd_vv_h_riscv32
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#define helper_vmadd_vv_w helper_vmadd_vv_w_riscv32
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#define helper_vmadd_vv_d helper_vmadd_vv_d_riscv32
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#define helper_vnmsub_vv_b helper_vnmsub_vv_b_riscv32
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#define helper_vnmsub_vv_h helper_vnmsub_vv_h_riscv32
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#define helper_vnmsub_vv_w helper_vnmsub_vv_w_riscv32
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#define helper_vnmsub_vv_d helper_vnmsub_vv_d_riscv32
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#define helper_vmacc_vx_b helper_vmacc_vx_b_riscv32
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#define helper_vmacc_vx_h helper_vmacc_vx_h_riscv32
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#define helper_vmacc_vx_w helper_vmacc_vx_w_riscv32
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#define helper_vmacc_vx_d helper_vmacc_vx_d_riscv32
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#define helper_vnmsac_vx_b helper_vnmsac_vx_b_riscv32
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#define helper_vnmsac_vx_h helper_vnmsac_vx_h_riscv32
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#define helper_vnmsac_vx_w helper_vnmsac_vx_w_riscv32
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#define helper_vnmsac_vx_d helper_vnmsac_vx_d_riscv32
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#define helper_vmadd_vx_b helper_vmadd_vx_b_riscv32
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#define helper_vmadd_vx_h helper_vmadd_vx_h_riscv32
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#define helper_vmadd_vx_w helper_vmadd_vx_w_riscv32
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#define helper_vmadd_vx_d helper_vmadd_vx_d_riscv32
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#define helper_vnmsub_vx_b helper_vnmsub_vx_b_riscv32
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#define helper_vnmsub_vx_h helper_vnmsub_vx_h_riscv32
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#define helper_vnmsub_vx_w helper_vnmsub_vx_w_riscv32
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#define helper_vnmsub_vx_d helper_vnmsub_vx_d_riscv32
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#define pmp_hart_has_privs pmp_hart_has_privs_riscv32
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#define pmpaddr_csr_read pmpaddr_csr_read_riscv32
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#define pmpaddr_csr_write pmpaddr_csr_write_riscv32
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@ -4209,6 +4209,38 @@
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#define helpet_vwmulsu_vx_b helpet_vwmulsu_vx_b_riscv64
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#define helpet_vwmulsu_vx_h helpet_vwmulsu_vx_h_riscv64
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#define helpet_vwmulsu_vx_w helpet_vwmulsu_vx_w_riscv64
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#define helper_vmacc_vv_b helper_vmacc_vv_b_riscv64
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#define helper_vmacc_vv_h helper_vmacc_vv_h_riscv64
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#define helper_vmacc_vv_w helper_vmacc_vv_w_riscv64
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#define helper_vmacc_vv_d helper_vmacc_vv_d_riscv64
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#define helper_vnmsac_vv_b helper_vnmsac_vv_b_riscv64
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#define helper_vnmsac_vv_h helper_vnmsac_vv_h_riscv64
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#define helper_vnmsac_vv_w helper_vnmsac_vv_w_riscv64
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#define helper_vnmsac_vv_d helper_vnmsac_vv_d_riscv64
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#define helper_vmadd_vv_b helper_vmadd_vv_b_riscv64
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#define helper_vmadd_vv_h helper_vmadd_vv_h_riscv64
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#define helper_vmadd_vv_w helper_vmadd_vv_w_riscv64
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#define helper_vmadd_vv_d helper_vmadd_vv_d_riscv64
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#define helper_vnmsub_vv_b helper_vnmsub_vv_b_riscv64
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#define helper_vnmsub_vv_h helper_vnmsub_vv_h_riscv64
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#define helper_vnmsub_vv_w helper_vnmsub_vv_w_riscv64
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#define helper_vnmsub_vv_d helper_vnmsub_vv_d_riscv64
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#define helper_vmacc_vx_b helper_vmacc_vx_b_riscv64
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#define helper_vmacc_vx_h helper_vmacc_vx_h_riscv64
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#define helper_vmacc_vx_w helper_vmacc_vx_w_riscv64
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#define helper_vmacc_vx_d helper_vmacc_vx_d_riscv64
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#define helper_vnmsac_vx_b helper_vnmsac_vx_b_riscv64
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#define helper_vnmsac_vx_h helper_vnmsac_vx_h_riscv64
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#define helper_vnmsac_vx_w helper_vnmsac_vx_w_riscv64
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#define helper_vnmsac_vx_d helper_vnmsac_vx_d_riscv64
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#define helper_vmadd_vx_b helper_vmadd_vx_b_riscv64
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#define helper_vmadd_vx_h helper_vmadd_vx_h_riscv64
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#define helper_vmadd_vx_w helper_vmadd_vx_w_riscv64
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#define helper_vmadd_vx_d helper_vmadd_vx_d_riscv64
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#define helper_vnmsub_vx_b helper_vnmsub_vx_b_riscv64
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#define helper_vnmsub_vx_h helper_vnmsub_vx_h_riscv64
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#define helper_vnmsub_vx_w helper_vnmsub_vx_w_riscv64
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#define helper_vnmsub_vx_d helper_vnmsub_vx_d_riscv64
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#define pmp_hart_has_privs pmp_hart_has_privs_riscv64
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#define pmpaddr_csr_read pmpaddr_csr_read_riscv64
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#define pmpaddr_csr_write pmpaddr_csr_write_riscv64
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@ -610,3 +610,36 @@ DEF_HELPER_6(vwmulu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwmulsu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwmulsu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vwmulsu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vmacc_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vmacc_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vnmsac_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vnmsac_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vnmsac_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vnmsac_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vmadd_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vmadd_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vmadd_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vmadd_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vnmsub_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vnmsub_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vnmsub_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vnmsub_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
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DEF_HELPER_6(vmacc_vx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vmacc_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vmacc_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vmacc_vx_d, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vnmsac_vx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vnmsac_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vnmsac_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vnmsac_vx_d, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vmadd_vx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vmadd_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vmadd_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vmadd_vx_d, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vnmsub_vx_b, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vnmsub_vx_h, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vnmsub_vx_w, void, ptr, ptr, tl, ptr, env, i32)
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DEF_HELPER_6(vnmsub_vx_d, void, ptr, ptr, tl, ptr, env, i32)
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@ -381,6 +381,14 @@ vwmulsu_vv 111010 . ..... ..... 010 ..... 1010111 @r_vm
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vwmulsu_vx 111010 . ..... ..... 110 ..... 1010111 @r_vm
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vwmul_vv 111011 . ..... ..... 010 ..... 1010111 @r_vm
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vwmul_vx 111011 . ..... ..... 110 ..... 1010111 @r_vm
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vmacc_vv 101101 . ..... ..... 010 ..... 1010111 @r_vm
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vmacc_vx 101101 . ..... ..... 110 ..... 1010111 @r_vm
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vnmsac_vv 101111 . ..... ..... 010 ..... 1010111 @r_vm
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vnmsac_vx 101111 . ..... ..... 110 ..... 1010111 @r_vm
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vmadd_vv 101001 . ..... ..... 010 ..... 1010111 @r_vm
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vmadd_vx 101001 . ..... ..... 110 ..... 1010111 @r_vm
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vnmsub_vv 101011 . ..... ..... 010 ..... 1010111 @r_vm
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vnmsub_vx 101011 . ..... ..... 110 ..... 1010111 @r_vm
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vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
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vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
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@ -1530,3 +1530,13 @@ GEN_OPIVV_WIDEN_TRANS(vwmulsu_vv, opivv_widen_check)
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GEN_OPIVX_WIDEN_TRANS(vwmul_vx)
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GEN_OPIVX_WIDEN_TRANS(vwmulu_vx)
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GEN_OPIVX_WIDEN_TRANS(vwmulsu_vx)
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/* Vector Single-Width Integer Multiply-Add Instructions */
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GEN_OPIVV_TRANS(vmacc_vv, opivv_check)
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GEN_OPIVV_TRANS(vnmsac_vv, opivv_check)
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GEN_OPIVV_TRANS(vmadd_vv, opivv_check)
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GEN_OPIVV_TRANS(vnmsub_vv, opivv_check)
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GEN_OPIVX_TRANS(vmacc_vx, opivx_check)
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GEN_OPIVX_TRANS(vnmsac_vx, opivx_check)
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GEN_OPIVX_TRANS(vmadd_vx, opivx_check)
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GEN_OPIVX_TRANS(vnmsub_vx, opivx_check)
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@ -1878,3 +1878,91 @@ GEN_VEXT_VX(vwmulu_vx_w, 4, 8, clearq)
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GEN_VEXT_VX(vwmulsu_vx_b, 1, 2, clearh)
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GEN_VEXT_VX(vwmulsu_vx_h, 2, 4, clearl)
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GEN_VEXT_VX(vwmulsu_vx_w, 4, 8, clearq)
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/* Vector Single-Width Integer Multiply-Add Instructions */
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#define OPIVV3(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \
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static void do_##NAME(void *vd, void *vs1, void *vs2, int i) \
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{ \
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TX1 s1 = *((T1 *)vs1 + HS1(i)); \
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TX2 s2 = *((T2 *)vs2 + HS2(i)); \
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TD d = *((TD *)vd + HD(i)); \
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*((TD *)vd + HD(i)) = OP(s2, s1, d); \
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}
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#define DO_MACC(N, M, D) (M * N + D)
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#define DO_NMSAC(N, M, D) (-(M * N) + D)
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#define DO_MADD(N, M, D) (M * D + N)
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#define DO_NMSUB(N, M, D) (-(M * D) + N)
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RVVCALL(OPIVV3, vmacc_vv_b, OP_SSS_B, H1, H1, H1, DO_MACC)
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RVVCALL(OPIVV3, vmacc_vv_h, OP_SSS_H, H2, H2, H2, DO_MACC)
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RVVCALL(OPIVV3, vmacc_vv_w, OP_SSS_W, H4, H4, H4, DO_MACC)
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RVVCALL(OPIVV3, vmacc_vv_d, OP_SSS_D, H8, H8, H8, DO_MACC)
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RVVCALL(OPIVV3, vnmsac_vv_b, OP_SSS_B, H1, H1, H1, DO_NMSAC)
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RVVCALL(OPIVV3, vnmsac_vv_h, OP_SSS_H, H2, H2, H2, DO_NMSAC)
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RVVCALL(OPIVV3, vnmsac_vv_w, OP_SSS_W, H4, H4, H4, DO_NMSAC)
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RVVCALL(OPIVV3, vnmsac_vv_d, OP_SSS_D, H8, H8, H8, DO_NMSAC)
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RVVCALL(OPIVV3, vmadd_vv_b, OP_SSS_B, H1, H1, H1, DO_MADD)
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RVVCALL(OPIVV3, vmadd_vv_h, OP_SSS_H, H2, H2, H2, DO_MADD)
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RVVCALL(OPIVV3, vmadd_vv_w, OP_SSS_W, H4, H4, H4, DO_MADD)
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RVVCALL(OPIVV3, vmadd_vv_d, OP_SSS_D, H8, H8, H8, DO_MADD)
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RVVCALL(OPIVV3, vnmsub_vv_b, OP_SSS_B, H1, H1, H1, DO_NMSUB)
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RVVCALL(OPIVV3, vnmsub_vv_h, OP_SSS_H, H2, H2, H2, DO_NMSUB)
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RVVCALL(OPIVV3, vnmsub_vv_w, OP_SSS_W, H4, H4, H4, DO_NMSUB)
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RVVCALL(OPIVV3, vnmsub_vv_d, OP_SSS_D, H8, H8, H8, DO_NMSUB)
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GEN_VEXT_VV(vmacc_vv_b, 1, 1, clearb)
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GEN_VEXT_VV(vmacc_vv_h, 2, 2, clearh)
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GEN_VEXT_VV(vmacc_vv_w, 4, 4, clearl)
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GEN_VEXT_VV(vmacc_vv_d, 8, 8, clearq)
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GEN_VEXT_VV(vnmsac_vv_b, 1, 1, clearb)
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GEN_VEXT_VV(vnmsac_vv_h, 2, 2, clearh)
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GEN_VEXT_VV(vnmsac_vv_w, 4, 4, clearl)
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GEN_VEXT_VV(vnmsac_vv_d, 8, 8, clearq)
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GEN_VEXT_VV(vmadd_vv_b, 1, 1, clearb)
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GEN_VEXT_VV(vmadd_vv_h, 2, 2, clearh)
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GEN_VEXT_VV(vmadd_vv_w, 4, 4, clearl)
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GEN_VEXT_VV(vmadd_vv_d, 8, 8, clearq)
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GEN_VEXT_VV(vnmsub_vv_b, 1, 1, clearb)
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GEN_VEXT_VV(vnmsub_vv_h, 2, 2, clearh)
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GEN_VEXT_VV(vnmsub_vv_w, 4, 4, clearl)
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GEN_VEXT_VV(vnmsub_vv_d, 8, 8, clearq)
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#define OPIVX3(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \
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static void do_##NAME(void *vd, target_long s1, void *vs2, int i) \
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{ \
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TX2 s2 = *((T2 *)vs2 + HS2(i)); \
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TD d = *((TD *)vd + HD(i)); \
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*((TD *)vd + HD(i)) = OP(s2, (TX1)(T1)s1, d); \
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}
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RVVCALL(OPIVX3, vmacc_vx_b, OP_SSS_B, H1, H1, DO_MACC)
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RVVCALL(OPIVX3, vmacc_vx_h, OP_SSS_H, H2, H2, DO_MACC)
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RVVCALL(OPIVX3, vmacc_vx_w, OP_SSS_W, H4, H4, DO_MACC)
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RVVCALL(OPIVX3, vmacc_vx_d, OP_SSS_D, H8, H8, DO_MACC)
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RVVCALL(OPIVX3, vnmsac_vx_b, OP_SSS_B, H1, H1, DO_NMSAC)
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RVVCALL(OPIVX3, vnmsac_vx_h, OP_SSS_H, H2, H2, DO_NMSAC)
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RVVCALL(OPIVX3, vnmsac_vx_w, OP_SSS_W, H4, H4, DO_NMSAC)
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RVVCALL(OPIVX3, vnmsac_vx_d, OP_SSS_D, H8, H8, DO_NMSAC)
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RVVCALL(OPIVX3, vmadd_vx_b, OP_SSS_B, H1, H1, DO_MADD)
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RVVCALL(OPIVX3, vmadd_vx_h, OP_SSS_H, H2, H2, DO_MADD)
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RVVCALL(OPIVX3, vmadd_vx_w, OP_SSS_W, H4, H4, DO_MADD)
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RVVCALL(OPIVX3, vmadd_vx_d, OP_SSS_D, H8, H8, DO_MADD)
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RVVCALL(OPIVX3, vnmsub_vx_b, OP_SSS_B, H1, H1, DO_NMSUB)
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RVVCALL(OPIVX3, vnmsub_vx_h, OP_SSS_H, H2, H2, DO_NMSUB)
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RVVCALL(OPIVX3, vnmsub_vx_w, OP_SSS_W, H4, H4, DO_NMSUB)
|
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RVVCALL(OPIVX3, vnmsub_vx_d, OP_SSS_D, H8, H8, DO_NMSUB)
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GEN_VEXT_VX(vmacc_vx_b, 1, 1, clearb)
|
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GEN_VEXT_VX(vmacc_vx_h, 2, 2, clearh)
|
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GEN_VEXT_VX(vmacc_vx_w, 4, 4, clearl)
|
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GEN_VEXT_VX(vmacc_vx_d, 8, 8, clearq)
|
||||
GEN_VEXT_VX(vnmsac_vx_b, 1, 1, clearb)
|
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GEN_VEXT_VX(vnmsac_vx_h, 2, 2, clearh)
|
||||
GEN_VEXT_VX(vnmsac_vx_w, 4, 4, clearl)
|
||||
GEN_VEXT_VX(vnmsac_vx_d, 8, 8, clearq)
|
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GEN_VEXT_VX(vmadd_vx_b, 1, 1, clearb)
|
||||
GEN_VEXT_VX(vmadd_vx_h, 2, 2, clearh)
|
||||
GEN_VEXT_VX(vmadd_vx_w, 4, 4, clearl)
|
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GEN_VEXT_VX(vmadd_vx_d, 8, 8, clearq)
|
||||
GEN_VEXT_VX(vnmsub_vx_b, 1, 1, clearb)
|
||||
GEN_VEXT_VX(vnmsub_vx_h, 2, 2, clearh)
|
||||
GEN_VEXT_VX(vnmsub_vx_w, 4, 4, clearl)
|
||||
GEN_VEXT_VX(vnmsub_vx_d, 8, 8, clearq)
|
||||
|
|
Loading…
Reference in a new issue