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target/mips: Introduce MXU registers

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Define and initialize the 16 MXU registers - 15 general computational
register, and 1 control register). There is also a zero register, but
it does not have any corresponding variable.

Backports commit eb5559f67dc8dc12335dd996877bb6daaea32eb2 from qemu.
This commit is contained in:
Craig Janeczek 2018-11-11 05:45:09 -05:00 committed by Lioncash
parent a1ba04ae44
commit 58dc377890
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GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 30 additions and 0 deletions
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10
qemu/target/mips/cpu.h
View file

@ -171,6 +171,16 @@ struct TCState {
MSACSR_FS_MASK)
float_status msa_fp_status;
#define NUMBER_OF_MXU_REGISTERS 16
target_ulong mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1];
target_ulong mxu_cr;
#define MXU_CR_LC 31
#define MXU_CR_RC 30
#define MXU_CR_BIAS 2
#define MXU_CR_RD_EN 1
#define MXU_CR_MXU_EN 0
};
typedef struct CPUMIPSState CPUMIPSState;

18
qemu/target/mips/translate.c
View file

@ -2440,6 +2440,7 @@ typedef struct DisasContext {
bool mrp;
bool nan2008;
bool abs2008;
// Unicorn engine
struct uc_struct *uc;
} DisasContext;
@ -2488,6 +2489,11 @@ static const char * const msaregnames[] = {
"w30.d0", "w30.d1", "w31.d0", "w31.d1",
};
static const char * const mxuregnames[] = {
"XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8",
"XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR",
};
#define LOG_DISAS(...) \
do { \
if (MIPS_DEBUG_DISAS) { \
@ -27409,6 +27415,18 @@ void mips_tcg_init(struct uc_struct *uc)
tcg_ctx->fpu_fcr31 = tcg_global_mem_new_i32(tcg_ctx, tcg_ctx->cpu_env,
offsetof(CPUMIPSState, active_fpu.fcr31),
"fcr31");
for (i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) {
tcg_ctx->mxu_gpr[i] = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
offsetof(CPUMIPSState,
active_tc.mxu_gpr[i]),
mxuregnames[i]);
}
tcg_ctx->mxu_CR = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env,
offsetof(CPUMIPSState, active_tc.mxu_cr),
mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]);
uc->init_tcg = true;
}

2
qemu/tcg/tcg.h
View file

@ -891,6 +891,8 @@ struct TCGContext {
TCGv_i32 fpu_fcr31;
TCGv_i64 fpu_f64[32];
TCGv_i64 msa_wr_d[64];
TCGv mxu_gpr[16 - 1]; // NUMBER_OF_MXU_REGISTERS - 1
TCGv mxu_CR;
/* qemu/target-sparc/translate.c */
/* global register indexes */