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target/arm: Implement the IRG instruction

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Backports commit da54941f45b820cbaca72aa6efd5669b3dc86e2f from qemu
This commit is contained in:
Richard Henderson 2021-02-25 14:35:39 -05:00 committed by Lioncash
parent 6bec295bf8
commit 58f3dd2cc7
7 changed files with 30 additions and 1 deletions
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1
qemu/aarch64.h
View file

@ -3575,6 +3575,7 @@
#define helper_gvec_usra_d helper_gvec_usra_d_aarch64
#define helper_gvec_usra_h helper_gvec_usra_h_aarch64
#define helper_gvec_usra_s helper_gvec_usra_s_aarch64
#define helper_irg helper_irg_aarch64
#define helper_msr_i_daifclear helper_msr_i_daifclear_aarch64
#define helper_msr_i_daifset helper_msr_i_daifset_aarch64
#define helper_msr_i_spsel helper_msr_i_spsel_aarch64

1
qemu/aarch64eb.h
View file

@ -3575,6 +3575,7 @@
#define helper_gvec_usra_d helper_gvec_usra_d_aarch64eb
#define helper_gvec_usra_h helper_gvec_usra_h_aarch64eb
#define helper_gvec_usra_s helper_gvec_usra_s_aarch64eb
#define helper_irg helper_irg_aarch64eb
#define helper_msr_i_daifclear helper_msr_i_daifclear_aarch64eb
#define helper_msr_i_daifset helper_msr_i_daifset_aarch64eb
#define helper_msr_i_spsel helper_msr_i_spsel_aarch64eb

1
qemu/header_gen.py
View file

@ -3709,6 +3709,7 @@ aarch64_symbols = (
'helper_gvec_usra_d',
'helper_gvec_usra_h',
'helper_gvec_usra_s',
'helper_irg',
'helper_msr_i_daifclear',
'helper_msr_i_daifset',
'helper_msr_i_spsel',

1
qemu/target/arm/Makefile.objs
View file

@ -79,3 +79,4 @@ obj-$(CONFIG_SOFTMMU) += psci.o
obj-$(TARGET_AARCH64) += translate-a64.o helper-a64.o
obj-$(TARGET_AARCH64) += translate-sve.o sve_helper.o
obj-$(TARGET_AARCH64) += pauth_helper.o
obj-$(TARGET_AARCH64) += mte_helper.o

4
qemu/target/arm/helper-a64.h
View file

@ -102,4 +102,6 @@ DEF_HELPER_FLAGS_3(autib, TCG_CALL_NO_WG, i64, env, i64, i64)
DEF_HELPER_FLAGS_3(autda, TCG_CALL_NO_WG, i64, env, i64, i64)
DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64, i64)
DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64)
DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64)
DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64)
DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64)

5
qemu/target/arm/internals.h
View file

@ -1265,4 +1265,9 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
*/
#define GMID_EL1_BS 6
static inline uint64_t address_with_allocation_tag(uint64_t ptr, int rtag)
{
return deposit64(ptr, 56, 4, rtag);
}
#endif

18
qemu/target/arm/translate-a64.c
View file

@ -363,6 +363,12 @@ static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr)
return clean;
}
/* Insert a zero tag into src, with the result at dst. */
static void gen_address_with_allocation_tag0(TCGContext *s, TCGv_i64 dst, TCGv_i64 src)
{
tcg_gen_andi_i64(s, dst, src, ~MAKE_64BIT_MASK(56, 4));
}
typedef struct DisasCompare64 {
TCGCond cond;
TCGv_i64 value;
@ -5506,6 +5512,18 @@ static void disas_data_proc_2src(DisasContext *s, uint32_t insn)
case 3: /* SDIV */
handle_div(s, true, sf, rm, rn, rd);
break;
case 4: /* IRG */
if (sf == 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) {
goto do_unallocated;
}
if (s->ata) {
gen_helper_irg(tcg_ctx, cpu_reg_sp(s, rd), tcg_ctx->cpu_env,
cpu_reg_sp(s, rn), cpu_reg(s, rm));
} else {
gen_address_with_allocation_tag0(tcg_ctx, cpu_reg_sp(s, rd),
cpu_reg_sp(s, rn));
}
break;
case 8: /* LSLV */
handle_shift_reg(s, A64_SHIFT_TYPE_LSL, sf, rm, rn, rd);
break;