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target/arm: Convert Neon VPADD 3-reg-same insns to decodetree

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Convert the Neon integer VPADD 3-reg-same insns to decodetree. These
are 'pairwise' operations. (Note that VQRDMLAH, which shares the
same primary opcode but has U=1, has already been converted.)

Backports commit fa22827d4eb078b6c58cd3d19af0b50ed951e832 from qemu
This commit is contained in:
Peter Maydell 2020-05-15 23:01:23 -04:00 committed by Lioncash
parent 1cc6451cb6
commit 59818edb3c
3 changed files with 5 additions and 18 deletions
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2
qemu/target/arm/neon-dp.decode
View file

@ -152,6 +152,8 @@ VPMAX_U_3s 1111 001 1 0 . .. .... .... 1010 . . . 0 .... @3same_q0
VPMIN_S_3s 1111 001 0 0 . .. .... .... 1010 . . . 1 .... @3same_q0 VPMIN_S_3s 1111 001 0 0 . .. .... .... 1010 . . . 1 .... @3same_q0
VPMIN_U_3s 1111 001 1 0 . .. .... .... 1010 . . . 1 .... @3same_q0 VPMIN_U_3s 1111 001 1 0 . .. .... .... 1010 . . . 1 .... @3same_q0
VPADD_3s 1111 001 0 0 . .. .... .... 1011 . . . 1 .... @3same_q0
VQRDMLAH_3s 1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same VQRDMLAH_3s 1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same
SHA1_3s 1111 001 0 0 . optype:2 .... .... 1100 . 1 . 0 .... \ SHA1_3s 1111 001 0 0 . optype:2 .... .... 1100 . 1 . 0 .... \

2
qemu/target/arm/translate-neon.inc.c
View file

@ -1008,8 +1008,10 @@ static bool do_3same_pair(DisasContext *s, arg_3same *a, NeonGenTwoOpFn *fn)
#define gen_helper_neon_pmax_u32 tcg_gen_umax_i32 #define gen_helper_neon_pmax_u32 tcg_gen_umax_i32
#define gen_helper_neon_pmin_s32 tcg_gen_smin_i32 #define gen_helper_neon_pmin_s32 tcg_gen_smin_i32
#define gen_helper_neon_pmin_u32 tcg_gen_umin_i32 #define gen_helper_neon_pmin_u32 tcg_gen_umin_i32
#define gen_helper_neon_padd_u32 tcg_gen_add_i32
DO_3SAME_PAIR(VPMAX_S, pmax_s) DO_3SAME_PAIR(VPMAX_S, pmax_s)
DO_3SAME_PAIR(VPMIN_S, pmin_s) DO_3SAME_PAIR(VPMIN_S, pmin_s)
DO_3SAME_PAIR(VPMAX_U, pmax_u) DO_3SAME_PAIR(VPMAX_U, pmax_u)
DO_3SAME_PAIR(VPMIN_U, pmin_u) DO_3SAME_PAIR(VPMIN_U, pmin_u)
DO_3SAME_PAIR(VPADD, padd_u)

19
qemu/target/arm/translate.c
View file

@ -5524,13 +5524,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
return 1; return 1;
} }
switch (op) { switch (op) {
case NEON_3R_VPADD_VQRDMLAH:
if (!u) {
break; /* VPADD */
}
/* VQRDMLAH : handled by decodetree */
return 1;
case NEON_3R_VFM_VQRDMLSH: case NEON_3R_VFM_VQRDMLSH:
if (!u) { if (!u) {
/* VFM, VFMS */ /* VFM, VFMS */
@ -5565,6 +5558,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
case NEON_3R_VQRSHL: case NEON_3R_VQRSHL:
case NEON_3R_VPMAX: case NEON_3R_VPMAX:
case NEON_3R_VPMIN: case NEON_3R_VPMIN:
case NEON_3R_VPADD_VQRDMLAH:
/* Already handled by decodetree */ /* Already handled by decodetree */
return 1; return 1;
} }
@ -5575,9 +5569,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
} }
pairwise = 0; pairwise = 0;
switch (op) { switch (op) {
case NEON_3R_VPADD_VQRDMLAH:
pairwise = 1;
break;
case NEON_3R_FLOAT_ARITH: case NEON_3R_FLOAT_ARITH:
pairwise = (u && size < 2); /* if VPADD (float) */ pairwise = (u && size < 2); /* if VPADD (float) */
break; break;
@ -5655,14 +5646,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
} }
} }
break; break;
case NEON_3R_VPADD_VQRDMLAH:
switch (size) {
case 0: gen_helper_neon_padd_u8(tcg_ctx, tmp, tmp, tmp2); break;
case 1: gen_helper_neon_padd_u16(tcg_ctx, tmp, tmp, tmp2); break;
case 2: tcg_gen_add_i32(tcg_ctx, tmp, tmp, tmp2); break;
default: abort();
}
break;
case NEON_3R_FLOAT_ARITH: /* Floating point arithmetic. */ case NEON_3R_FLOAT_ARITH: /* Floating point arithmetic. */
{ {
TCGv_ptr fpstatus = get_fpstatus_ptr(s, 1); TCGv_ptr fpstatus = get_fpstatus_ptr(s, 1);