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target/arm: Implement SVE bitwise shift by vector (predicated)

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Backports commit 27721dbb7ae5e2a52f06588cf38854e4cbc613c0 from qemu
This commit is contained in:
Richard Henderson 2018-05-20 03:06:35 -04:00 committed by Lioncash
parent 7bb3067b95
commit 5aa51a3a74
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GPG key ID: 4E3C3CC1031BA9C7
7 changed files with 100 additions and 0 deletions
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12
qemu/aarch64.h
View file

@ -3287,6 +3287,10 @@
#define helper_sve_andv_d helper_sve_andv_d_aarch64
#define helper_sve_andv_h helper_sve_andv_h_aarch64
#define helper_sve_andv_s helper_sve_andv_s_aarch64
#define helper_sve_asr_zpzz_b helper_sve_asr_zpzz_b_aarch64
#define helper_sve_asr_zpzz_d helper_sve_asr_zpzz_d_aarch64
#define helper_sve_asr_zpzz_h helper_sve_asr_zpzz_h_aarch64
#define helper_sve_asr_zpzz_s helper_sve_asr_zpzz_s_aarch64
#define helper_sve_asrd_b helper_sve_asrd_b_aarch64
#define helper_sve_asrd_d helper_sve_asrd_d_aarch64
#define helper_sve_asrd_h helper_sve_asrd_h_aarch64
@ -3317,10 +3321,18 @@
#define helper_sve_lsl_zpzi_d helper_sve_lsl_zpzi_d_aarch64
#define helper_sve_lsl_zpzi_h helper_sve_lsl_zpzi_h_aarch64
#define helper_sve_lsl_zpzi_s helper_sve_lsl_zpzi_s_aarch64
#define helper_sve_lsl_zpzz_b helper_sve_lsl_zpzz_b_aarch64
#define helper_sve_lsl_zpzz_d helper_sve_lsl_zpzz_d_aarch64
#define helper_sve_lsl_zpzz_h helper_sve_lsl_zpzz_h_aarch64
#define helper_sve_lsl_zpzz_s helper_sve_lsl_zpzz_s_aarch64
#define helper_sve_lsr_zpzi_b helper_sve_lsr_zpzi_b_aarch64
#define helper_sve_lsr_zpzi_d helper_sve_lsr_zpzi_d_aarch64
#define helper_sve_lsr_zpzi_h helper_sve_lsr_zpzi_h_aarch64
#define helper_sve_lsr_zpzi_s helper_sve_lsr_zpzi_s_aarch64
#define helper_sve_lsr_zpzz_b helper_sve_lsr_zpzz_b_aarch64
#define helper_sve_lsr_zpzz_d helper_sve_lsr_zpzz_d_aarch64
#define helper_sve_lsr_zpzz_h helper_sve_lsr_zpzz_h_aarch64
#define helper_sve_lsr_zpzz_s helper_sve_lsr_zpzz_s_aarch64
#define helper_sve_mul_zpzz_b helper_sve_mul_zpzz_b_aarch64
#define helper_sve_mul_zpzz_d helper_sve_mul_zpzz_d_aarch64
#define helper_sve_mul_zpzz_h helper_sve_mul_zpzz_h_aarch64

12
qemu/aarch64eb.h
View file

@ -3287,6 +3287,10 @@
#define helper_sve_andv_d helper_sve_andv_d_aarch64eb
#define helper_sve_andv_h helper_sve_andv_h_aarch64eb
#define helper_sve_andv_s helper_sve_andv_s_aarch64eb
#define helper_sve_asr_zpzz_b helper_sve_asr_zpzz_b_aarch64eb
#define helper_sve_asr_zpzz_d helper_sve_asr_zpzz_d_aarch64eb
#define helper_sve_asr_zpzz_h helper_sve_asr_zpzz_h_aarch64eb
#define helper_sve_asr_zpzz_s helper_sve_asr_zpzz_s_aarch64eb
#define helper_sve_asrd_b helper_sve_asrd_b_aarch64eb
#define helper_sve_asrd_d helper_sve_asrd_d_aarch64eb
#define helper_sve_asrd_h helper_sve_asrd_h_aarch64eb
@ -3317,10 +3321,18 @@
#define helper_sve_lsl_zpzi_d helper_sve_lsl_zpzi_d_aarch64eb
#define helper_sve_lsl_zpzi_h helper_sve_lsl_zpzi_h_aarch64eb
#define helper_sve_lsl_zpzi_s helper_sve_lsl_zpzi_s_aarch64eb
#define helper_sve_lsl_zpzz_b helper_sve_lsl_zpzz_b_aarch64eb
#define helper_sve_lsl_zpzz_d helper_sve_lsl_zpzz_d_aarch64eb
#define helper_sve_lsl_zpzz_h helper_sve_lsl_zpzz_h_aarch64eb
#define helper_sve_lsl_zpzz_s helper_sve_lsl_zpzz_s_aarch64eb
#define helper_sve_lsr_zpzi_b helper_sve_lsr_zpzi_b_aarch64eb
#define helper_sve_lsr_zpzi_d helper_sve_lsr_zpzi_d_aarch64eb
#define helper_sve_lsr_zpzi_h helper_sve_lsr_zpzi_h_aarch64eb
#define helper_sve_lsr_zpzi_s helper_sve_lsr_zpzi_s_aarch64eb
#define helper_sve_lsr_zpzz_b helper_sve_lsr_zpzz_b_aarch64eb
#define helper_sve_lsr_zpzz_d helper_sve_lsr_zpzz_d_aarch64eb
#define helper_sve_lsr_zpzz_h helper_sve_lsr_zpzz_h_aarch64eb
#define helper_sve_lsr_zpzz_s helper_sve_lsr_zpzz_s_aarch64eb
#define helper_sve_mul_zpzz_b helper_sve_mul_zpzz_b_aarch64eb
#define helper_sve_mul_zpzz_d helper_sve_mul_zpzz_d_aarch64eb
#define helper_sve_mul_zpzz_h helper_sve_mul_zpzz_h_aarch64eb

12
qemu/header_gen.py
View file

@ -3308,6 +3308,10 @@ aarch64_symbols = (
'helper_sve_andv_d',
'helper_sve_andv_h',
'helper_sve_andv_s',
'helper_sve_asr_zpzz_b',
'helper_sve_asr_zpzz_d',
'helper_sve_asr_zpzz_h',
'helper_sve_asr_zpzz_s',
'helper_sve_asrd_b',
'helper_sve_asrd_d',
'helper_sve_asrd_h',
@ -3338,10 +3342,18 @@ aarch64_symbols = (
'helper_sve_lsl_zpzi_d',
'helper_sve_lsl_zpzi_h',
'helper_sve_lsl_zpzi_s',
'helper_sve_lsl_zpzz_b',
'helper_sve_lsl_zpzz_d',
'helper_sve_lsl_zpzz_h',
'helper_sve_lsl_zpzz_s',
'helper_sve_lsr_zpzi_b',
'helper_sve_lsr_zpzi_d',
'helper_sve_lsr_zpzi_h',
'helper_sve_lsr_zpzi_s',
'helper_sve_lsr_zpzz_b',
'helper_sve_lsr_zpzz_d',
'helper_sve_lsr_zpzz_h',
'helper_sve_lsr_zpzz_s',
'helper_sve_mul_zpzz_b',
'helper_sve_mul_zpzz_d',
'helper_sve_mul_zpzz_h',

27
qemu/target/arm/helper-sve.h
View file

@ -168,6 +168,33 @@ DEF_HELPER_FLAGS_5(sve_udiv_zpzz_s, TCG_CALL_NO_RWG,
DEF_HELPER_FLAGS_5(sve_udiv_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_asr_zpzz_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_asr_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_asr_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_asr_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_lsr_zpzz_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_lsr_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_lsr_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_lsr_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_lsl_zpzz_b, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_lsl_zpzz_h, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_lsl_zpzz_s, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_5(sve_lsl_zpzz_d, TCG_CALL_NO_RWG,
void, ptr, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_orv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_orv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
DEF_HELPER_FLAGS_3(sve_orv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)

8
qemu/target/arm/sve.decode
View file

@ -149,6 +149,14 @@ LSL_zpzi 00000100 .. 000 011 100 ... .. ... ..... \
ASRD 00000100 .. 000 100 100 ... .. ... ..... \
@rdn_pg_tszimm imm=%tszimm_shr
# SVE bitwise shift by vector (predicated)
ASR_zpzz 00000100 .. 010 000 100 ... ..... ..... @rdn_pg_rm
LSR_zpzz 00000100 .. 010 001 100 ... ..... ..... @rdn_pg_rm
LSL_zpzz 00000100 .. 010 011 100 ... ..... ..... @rdn_pg_rm
ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR
LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR
LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR
### SVE Logical - Unpredicated Group
# SVE bitwise logical operations (unpredicated)

25
qemu/target/arm/sve_helper.c
View file

@ -439,6 +439,28 @@ DO_ZPZZ_D(sve_sdiv_zpzz_d, int64_t, DO_DIV)
DO_ZPZZ(sve_udiv_zpzz_s, uint32_t, H1_4, DO_DIV)
DO_ZPZZ_D(sve_udiv_zpzz_d, uint64_t, DO_DIV)
/* Note that all bits of the shift are significant
and not modulo the element size. */
#define DO_ASR(N, M) (N >> MIN(M, sizeof(N) * 8 - 1))
#define DO_LSR(N, M) (M < sizeof(N) * 8 ? N >> M : 0)
#define DO_LSL(N, M) (M < sizeof(N) * 8 ? N << M : 0)
DO_ZPZZ(sve_asr_zpzz_b, int8_t, H1, DO_ASR)
DO_ZPZZ(sve_lsr_zpzz_b, uint8_t, H1_2, DO_LSR)
DO_ZPZZ(sve_lsl_zpzz_b, uint8_t, H1_4, DO_LSL)
DO_ZPZZ(sve_asr_zpzz_h, int16_t, H1, DO_ASR)
DO_ZPZZ(sve_lsr_zpzz_h, uint16_t, H1_2, DO_LSR)
DO_ZPZZ(sve_lsl_zpzz_h, uint16_t, H1_4, DO_LSL)
DO_ZPZZ(sve_asr_zpzz_s, int32_t, H1, DO_ASR)
DO_ZPZZ(sve_lsr_zpzz_s, uint32_t, H1_2, DO_LSR)
DO_ZPZZ(sve_lsl_zpzz_s, uint32_t, H1_4, DO_LSL)
DO_ZPZZ_D(sve_asr_zpzz_d, int64_t, DO_ASR)
DO_ZPZZ_D(sve_lsr_zpzz_d, uint64_t, DO_LSR)
DO_ZPZZ_D(sve_lsl_zpzz_d, uint64_t, DO_LSL)
#undef DO_ZPZZ
#undef DO_ZPZZ_D
@ -543,6 +565,9 @@ DO_VPZ_D(sve_uminv_d, uint64_t, uint64_t, -1, DO_MIN)
#undef DO_ABD
#undef DO_MUL
#undef DO_DIV
#undef DO_ASR
#undef DO_LSR
#undef DO_LSL
/* Similar to the ARM LastActiveElement pseudocode function, except the
result is multiplied by the element size. This includes the not found

4
qemu/target/arm/translate-sve.c
View file

@ -307,6 +307,10 @@ DO_ZPZZ(MUL, mul)
DO_ZPZZ(SMULH, smulh)
DO_ZPZZ(UMULH, umulh)
DO_ZPZZ(ASR, asr)
DO_ZPZZ(LSR, lsr)
DO_ZPZZ(LSL, lsl)
static bool trans_SDIV_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t insn)
{
static gen_helper_gvec_4 * const fns[4] = {