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target-arm: Fix IL bit reported for Thumb coprocessor traps
All Thumb coprocessor instructions are 32 bits, so the IL bit in the syndrome register should be set. Pass false to the syn_* function's is_16bit argument rather than s->thumb so we report the correct IL bit. Backports commit 4df322593037d2700f72dfdfb967300b7ad2e696 from qemu
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@ -7314,19 +7314,19 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn)
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case 14:
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if (is64) {
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syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
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isread, s->thumb);
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isread, false);
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} else {
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syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm,
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rt, isread, s->thumb);
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rt, isread, false);
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}
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break;
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case 15:
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if (is64) {
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syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2,
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isread, s->thumb);
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isread, false);
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} else {
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syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm,
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rt, isread, s->thumb);
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rt, isread, false);
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}
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break;
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default:
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