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target/riscv: vector element index instruction

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Backports 126bec3f6ff3379e1a49f4a7d36922bfd079a3cc
This commit is contained in:
LIU Zhiwei 2021-03-07 12:29:11 -05:00 committed by Lioncash
parent 2f7cdaee7b
commit 5ff1871e32
7 changed files with 70 additions and 0 deletions
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4
qemu/header_gen.py
View file

@ -7267,6 +7267,10 @@ riscv_symbols = (
'helper_viota_m_h',
'helper_viota_m_w',
'helper_viota_m_d',
'helper_vid_v_b',
'helper_vid_v_h',
'helper_vid_v_w',
'helper_vid_v_d',
'pmp_hart_has_privs',
'pmpaddr_csr_read',
'pmpaddr_csr_write',

4
qemu/riscv32.h
View file

@ -4703,6 +4703,10 @@
#define helper_viota_m_h helper_viota_m_h_riscv32
#define helper_viota_m_w helper_viota_m_w_riscv32
#define helper_viota_m_d helper_viota_m_d_riscv32
#define helper_vid_v_b helper_vid_v_b_riscv32
#define helper_vid_v_h helper_vid_v_h_riscv32
#define helper_vid_v_w helper_vid_v_w_riscv32
#define helper_vid_v_d helper_vid_v_d_riscv32
#define pmp_hart_has_privs pmp_hart_has_privs_riscv32
#define pmpaddr_csr_read pmpaddr_csr_read_riscv32
#define pmpaddr_csr_write pmpaddr_csr_write_riscv32

4
qemu/riscv64.h
View file

@ -4703,6 +4703,10 @@
#define helper_viota_m_h helper_viota_m_h_riscv64
#define helper_viota_m_w helper_viota_m_w_riscv64
#define helper_viota_m_d helper_viota_m_d_riscv64
#define helper_vid_v_b helper_vid_v_b_riscv64
#define helper_vid_v_h helper_vid_v_h_riscv64
#define helper_vid_v_w helper_vid_v_w_riscv64
#define helper_vid_v_d helper_vid_v_d_riscv64
#define pmp_hart_has_privs pmp_hart_has_privs_riscv64
#define pmpaddr_csr_read pmpaddr_csr_read_riscv64
#define pmpaddr_csr_write pmpaddr_csr_write_riscv64

5
qemu/target/riscv/helper.h
View file

@ -1117,3 +1117,8 @@ DEF_HELPER_5(viota_m_b, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(viota_m_h, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(viota_m_w, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_5(viota_m_d, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_4(vid_v_b, void, ptr, ptr, env, i32)
DEF_HELPER_4(vid_v_h, void, ptr, ptr, env, i32)
DEF_HELPER_4(vid_v_w, void, ptr, ptr, env, i32)
DEF_HELPER_4(vid_v_d, void, ptr, ptr, env, i32)

2
qemu/target/riscv/insn32.decode
View file

@ -70,6 +70,7 @@
@r2 ....... ..... ..... ... ..... ....... %rs1 %rd
@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
@r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
@r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd
@r_nfvm ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd
@r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd
@r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd
@ -561,6 +562,7 @@ vmsbf_m 010110 . ..... 00001 010 ..... 1010111 @r2_vm
vmsif_m 010110 . ..... 00011 010 ..... 1010111 @r2_vm
vmsof_m 010110 . ..... 00010 010 ..... 1010111 @r2_vm
viota_m 010110 . ..... 10000 010 ..... 1010111 @r2_vm
vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r

27
qemu/target/riscv/insn_trans/trans_rvv.inc.c
View file

@ -2553,3 +2553,30 @@ static bool trans_viota_m(DisasContext *s, arg_viota_m *a)
}
return false;
}
/* Vector Element Index Instruction */
static bool trans_vid_v(DisasContext *s, arg_vid_v *a)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
if (vext_check_isa_ill(s) &&
vext_check_reg(s, a->rd, false) &&
vext_check_overlap_mask(s, a->rd, a->vm, false)) {
uint32_t data = 0;
TCGLabel *over = gen_new_label(tcg_ctx);
tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_vl_risc, 0, over);
data = FIELD_DP32(data, VDATA, MLEN, s->mlen);
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
static gen_helper_gvec_2_ptr * const fns[4] = {
gen_helper_vid_v_b, gen_helper_vid_v_h,
gen_helper_vid_v_w, gen_helper_vid_v_d,
};
tcg_gen_gvec_2_ptr(tcg_ctx, vreg_ofs(s, a->rd), vreg_ofs(s, 0),
tcg_ctx->cpu_env, 0, s->vlen / 8, data, fns[s->sew]);
gen_set_label(tcg_ctx, over);
return true;
}
return false;
}

24
qemu/target/riscv/vector_helper.c
View file

@ -4649,3 +4649,27 @@ GEN_VEXT_VIOTA_M(viota_m_b, uint8_t, H1, clearb)
GEN_VEXT_VIOTA_M(viota_m_h, uint16_t, H2, clearh)
GEN_VEXT_VIOTA_M(viota_m_w, uint32_t, H4, clearl)
GEN_VEXT_VIOTA_M(viota_m_d, uint64_t, H8, clearq)
/* Vector Element Index Instruction */
#define GEN_VEXT_VID_V(NAME, ETYPE, H, CLEAR_FN) \
void HELPER(NAME)(void *vd, void *v0, CPURISCVState *env, uint32_t desc) \
{ \
uint32_t mlen = vext_mlen(desc); \
uint32_t vlmax = env_archcpu(env)->cfg.vlen / mlen; \
uint32_t vm = vext_vm(desc); \
uint32_t vl = env->vl; \
int i; \
\
for (i = 0; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, mlen, i)) { \
continue; \
} \
*((ETYPE *)vd + H(i)) = i; \
} \
CLEAR_FN(vd, vl, vl * sizeof(ETYPE), vlmax * sizeof(ETYPE)); \
}
GEN_VEXT_VID_V(vid_v_b, uint8_t, H1, clearb)
GEN_VEXT_VID_V(vid_v_h, uint16_t, H2, clearh)
GEN_VEXT_VID_V(vid_v_w, uint32_t, H4, clearl)
GEN_VEXT_VID_V(vid_v_d, uint64_t, H8, clearq)