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target-mips: Fix ALIGN instruction when bp=0

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If executing ALIGN with shift count bp=0 within mips64 emulation,
the result of the operation should be sign extended.

Taken from the official documentation (pseudo code) :

ALIGN:
tmp_rt_hi = unsigned_word(GPR[rt]) << (8*bp)
tmp_rs_lo = unsigned_word(GPR[rs]) >> (8*(4-bp))
tmp = tmp_rt_hi || tmp_rt_lo
GPR[rd] = sign_extend.32(tmp)

Backports commit 51243852af322f0a1103a90c936c43db84def82f from qemu
This commit is contained in:
Miodrag Dinic 2018-02-19 00:42:02 -05:00 committed by Lioncash
parent 2e8c6adc4b
commit 63dad98564
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 10 additions and 1 deletions
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11
qemu/target-mips/translate.c
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@ -4696,7 +4696,16 @@ static void gen_align(DisasContext *ctx, int opc, int rd, int rs, int rt,
t0 = tcg_temp_new(tcg_ctx);
gen_load_gpr(ctx, t0, rt);
if (bp == 0) {
tcg_gen_mov_tl(tcg_ctx, *cpu_gpr[rd], t0);
switch (opc) {
case OPC_ALIGN:
tcg_gen_ext32s_tl(tcg_ctx, *cpu_gpr[rd], t0);
break;
#if defined(TARGET_MIPS64)
case OPC_DALIGN:
tcg_gen_mov_tl(tcg_ctx, *cpu_gpr[rd], t0);
break;
#endif
}
} else {
TCGv t1 = tcg_temp_new(tcg_ctx);
gen_load_gpr(ctx, t1, rs);