yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-03-23 05:25:11 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/mips: Improve DSP R2/R3-related naming

Browse source 
Do following replacements:

ASE_DSPR2 -> ASE_DSP_R2
ASE_DSPR3 -> ASE_DSP_R3
MIPS_HFLAG_DSPR2 -> MIPS_HFLAG_DSP_R2
MIPS_HFLAG_DSPR3 -> MIPS_HFLAG_DSP_R3
check_dspr2() -> check_dsp_r2()
check_dspr3() -> check_dsp_r3()

and several other similar minor replacements.

Backports commit 908f6be1b9cbc270470230f805d6f7474ab3178d from qemu
This commit is contained in:
Stefan Markovic 2018-10-23 13:40:55 -04:00 committed by Lioncash
parent 6dd29739a9
commit 64bec62433
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
5 changed files with 120 additions and 112 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
qemu/target/mips/cpu.h
View file

@ -793,9 +793,9 @@ struct CPUMIPSState {
#define MIPS_HFLAG_BX 0x40000 /* branch exchanges execution mode */
#define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT)
/* MIPS DSP resources access. */
#define MIPS_HFLAG_DSP 0x080000 /* Enable access to MIPS DSP resources. */
#define MIPS_HFLAG_DSPR2 0x100000 /* Enable access to MIPS DSPR2 resources. */
#define MIPS_HFLAG_DSPR3 0x20000000 /* Enable access to MIPS DSPR3 resources.*/
#define MIPS_HFLAG_DSP 0x080000 /* Enable access to DSP resources. */
#define MIPS_HFLAG_DSP_R2 0x100000 /* Enable access to DSP R2 resources. */
#define MIPS_HFLAG_DSP_R3 0x20000000 /* Enable access to DSP R3 resources. */
/* Extra flag about HWREna register. */
#define MIPS_HFLAG_HWRENA_ULR 0x200000 /* ULR bit from HWREna is set. */
#define MIPS_HFLAG_SBRI 0x400000 /* R6 SDBBP causes RI excpt. in user mode */

30
qemu/target/mips/internal.h
View file

@ -310,8 +310,8 @@ static inline void compute_hflags(CPUMIPSState *env)
{
env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
MIPS_HFLAG_DSPR3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA |
MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
MIPS_HFLAG_DSP_R3 | MIPS_HFLAG_SBRI | MIPS_HFLAG_MSA |
MIPS_HFLAG_FRE | MIPS_HFLAG_ELPA | MIPS_HFLAG_ERL);
if (env->CP0_Status & (1 << CP0St_ERL)) {
env->hflags |= MIPS_HFLAG_ERL;
@ -359,21 +359,29 @@ static inline void compute_hflags(CPUMIPSState *env)
(env->CP0_Config5 & (1 << CP0C5_SBRI))) {
env->hflags |= MIPS_HFLAG_SBRI;
}
if (env->insn_flags & ASE_DSPR3) {
if (env->insn_flags & ASE_DSP_R3) {
/*
* Our cpu supports DSP R3 ASE, so enable
* access to DSP R3 resources.
*/
if (env->CP0_Status & (1 << CP0St_MX)) {
env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2 |
MIPS_HFLAG_DSPR3;
env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2 |
MIPS_HFLAG_DSP_R3;
}
} else if (env->insn_flags & ASE_DSPR2) {
/* Enables access MIPS DSP resources, now our cpu is DSP ASER2,
so enable to access DSPR2 resources. */
} else if (env->insn_flags & ASE_DSP_R2) {
/*
* Our cpu supports DSP R2 ASE, so enable
* access to DSP R2 resources.
*/
if (env->CP0_Status & (1 << CP0St_MX)) {
env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2;
env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSP_R2;
}
} else if (env->insn_flags & ASE_DSP) {
/* Enables access MIPS DSP resources, now our cpu is DSP ASE,
so enable to access DSP resources. */
/*
* Our cpu supports DSP ASE, so enable
* access to DSP resources.
*/
if (env->CP0_Status & (1 << CP0St_MX)) {
env->hflags |= MIPS_HFLAG_DSP;
}

4
qemu/target/mips/mips-defs.h
View file

@ -48,8 +48,8 @@
#define ASE_MIPS3D 0x0000000200000000ULL
#define ASE_MDMX 0x0000000400000000ULL
#define ASE_DSP 0x0000000800000000ULL
#define ASE_DSPR2 0x0000001000000000ULL
#define ASE_DSPR3 0x0000002000000000ULL
#define ASE_DSP_R2 0x0000001000000000ULL
#define ASE_DSP_R3 0x0000002000000000ULL
#define ASE_MT 0x0000004000000000ULL
#define ASE_SMARTMIPS 0x0000008000000000ULL
#define ASE_MICROMIPS 0x0000010000000000ULL

184
qemu/target/mips/translate.c
View file

@ -2404,9 +2404,9 @@ static inline void check_dsp(DisasContext *ctx)
}
}
static inline void check_dspr2(DisasContext *ctx)
static inline void check_dsp_r2(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR2))) {
if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R2))) {
if (ctx->insn_flags & ASE_DSP) {
generate_exception_end(ctx, EXCP_DSPDIS);
} else {
@ -2415,9 +2415,9 @@ static inline void check_dspr2(DisasContext *ctx)
}
}
static inline void check_dspr3(DisasContext *ctx)
static inline void check_dsp_r3(DisasContext *ctx)
{
if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR3))) {
if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP_R3))) {
if (ctx->insn_flags & ASE_DSP) {
generate_exception_end(ctx, EXCP_DSPDIS);
} else {
@ -18123,7 +18123,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
case NM_POOL32AXF_2_0_7:
switch (extract32(ctx->opcode, 9, 3)) {
case NM_DPA_W_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_dpa_w_ph(tcg_ctx, t0, v1, v0, tcg_ctx->cpu_env);
break;
case NM_DPAQ_S_W_PH:
@ -18131,7 +18131,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
gen_helper_dpaq_s_w_ph(tcg_ctx, t0, v1, v0, tcg_ctx->cpu_env);
break;
case NM_DPS_W_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_dps_w_ph(tcg_ctx, t0, v1, v0, tcg_ctx->cpu_env);
break;
case NM_DPSQ_S_W_PH:
@ -18146,7 +18146,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
case NM_POOL32AXF_2_8_15:
switch (extract32(ctx->opcode, 9, 3)) {
case NM_DPAX_W_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_dpax_w_ph(tcg_ctx, t0, v0, v1, tcg_ctx->cpu_env);
break;
case NM_DPAQ_SA_L_W:
@ -18154,7 +18154,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
gen_helper_dpaq_sa_l_w(tcg_ctx, t0, v0, v1, tcg_ctx->cpu_env);
break;
case NM_DPSX_W_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_dpsx_w_ph(tcg_ctx, t0, v0, v1, tcg_ctx->cpu_env);
break;
case NM_DPSQ_SA_L_W:
@ -18173,7 +18173,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
gen_helper_dpau_h_qbl(tcg_ctx, t0, v0, v1, tcg_ctx->cpu_env);
break;
case NM_DPAQX_S_W_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_dpaqx_s_w_ph(tcg_ctx, t0, v0, v1, tcg_ctx->cpu_env);
break;
case NM_DPSU_H_QBL:
@ -18181,11 +18181,11 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
gen_helper_dpsu_h_qbl(tcg_ctx, t0, v0, v1, tcg_ctx->cpu_env);
break;
case NM_DPSQX_S_W_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_dpsqx_s_w_ph(tcg_ctx, t0, v0, v1, tcg_ctx->cpu_env);
break;
case NM_MULSA_W_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_mulsa_w_ph(tcg_ctx, t0, v0, v1, tcg_ctx->cpu_env);
break;
default:
@ -18200,7 +18200,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
gen_helper_dpau_h_qbr(tcg_ctx, t0, v1, v0, tcg_ctx->cpu_env);
break;
case NM_DPAQX_SA_W_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_dpaqx_sa_w_ph(tcg_ctx, t0, v1, v0, tcg_ctx->cpu_env);
break;
case NM_DPSU_H_QBR:
@ -18208,7 +18208,7 @@ static void gen_pool32axf_2_multiply(DisasContext *ctx, uint32_t opc,
gen_helper_dpsu_h_qbr(tcg_ctx, t0, v1, v0, tcg_ctx->cpu_env);
break;
case NM_DPSQX_SA_W_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_dpsqx_sa_w_ph(tcg_ctx, t0, v1, v0, tcg_ctx->cpu_env);
break;
case NM_MULSAQ_S_W_PH:
@ -18251,7 +18251,7 @@ static void gen_pool32axf_2_nanomips_insn(DisasContext *ctx, uint32_t opc,
gen_pool32axf_2_multiply(ctx, opc, v0_t, v1_t, rd);
break;
case NM_BALIGN:
check_dspr2(ctx);
check_dsp_r2(ctx);
if (rt != 0) {
gen_load_gpr(ctx, t0, rs);
rd &= 3;
@ -18482,7 +18482,7 @@ static void gen_pool32axf_4_nanomips_insn(DisasContext *ctx, uint32_t opc,
switch (opc) {
case NM_ABSQ_S_QB:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_absq_s_qb(tcg_ctx, v0_t, v0_t, tcg_ctx->cpu_env);
gen_store_gpr(ctx, v0_t, ret);
break;
@ -18622,7 +18622,7 @@ static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc,
switch (opc) {
case NM_SHRA_R_QB:
check_dspr2(ctx);
check_dsp_r2(ctx);
tcg_gen_movi_tl(tcg_ctx, t0, rd >> 2);
switch (extract32(ctx->opcode, 12, 1)) {
case 0:
@ -18638,7 +18638,7 @@ static void gen_pool32axf_7_nanomips_insn(DisasContext *ctx, uint32_t opc,
}
break;
case NM_SHRL_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
tcg_gen_movi_tl(tcg_ctx, t0, rd >> 1);
gen_helper_shrl_ph(tcg_ctx, t0, t0, rs_t);
gen_store_gpr(ctx, t0, rt);
@ -19570,19 +19570,19 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
gen_store_gpr(ctx, v1_t, ret);
break;
case NM_CMPGDU_EQ_QB:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_cmpgu_eq_qb(tcg_ctx, v1_t, v1_t, v2_t);
tcg_gen_deposit_tl(tcg_ctx, tcg_ctx->cpu_dspctrl, tcg_ctx->cpu_dspctrl, v1_t, 24, 4);
gen_store_gpr(ctx, v1_t, ret);
break;
case NM_CMPGDU_LT_QB:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_cmpgu_lt_qb(tcg_ctx, v1_t, v1_t, v2_t);
tcg_gen_deposit_tl(tcg_ctx, tcg_ctx->cpu_dspctrl, tcg_ctx->cpu_dspctrl, v1_t, 24, 4);
gen_store_gpr(ctx, v1_t, ret);
break;
case NM_CMPGDU_LE_QB:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_cmpgu_le_qb(tcg_ctx, v1_t, v1_t, v2_t);
tcg_gen_deposit_tl(tcg_ctx, tcg_ctx->cpu_dspctrl, tcg_ctx->cpu_dspctrl, v1_t, 24, 4);
gen_store_gpr(ctx, v1_t, ret);
@ -19638,7 +19638,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
}
break;
case NM_ADDQH_R_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* ADDQH_PH */
@ -19653,7 +19653,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
}
break;
case NM_ADDQH_R_W:
check_dspr2(ctx);
check_dsp_r2(ctx);
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* ADDQH_W */
@ -19683,7 +19683,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
}
break;
case NM_ADDU_S_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* ADDU_PH */
@ -19698,7 +19698,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
}
break;
case NM_ADDUH_R_QB:
check_dspr2(ctx);
check_dsp_r2(ctx);
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* ADDUH_QB */
@ -19728,7 +19728,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
}
break;
case NM_SHRAV_R_QB:
check_dspr2(ctx);
check_dsp_r2(ctx);
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* SHRAV_QB */
@ -19758,7 +19758,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
}
break;
case NM_SUBQH_R_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* SUBQH_PH */
@ -19773,7 +19773,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
}
break;
case NM_SUBQH_R_W:
check_dspr2(ctx);
check_dsp_r2(ctx);
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* SUBQH_W */
@ -19803,7 +19803,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
}
break;
case NM_SUBU_S_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* SUBU_PH */
@ -19818,7 +19818,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
}
break;
case NM_SUBUH_R_QB:
check_dspr2(ctx);
check_dsp_r2(ctx);
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* SUBUH_QB */
@ -19848,7 +19848,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
}
break;
case NM_PRECR_SRA_R_PH_W:
check_dspr2(ctx);
check_dsp_r2(ctx);
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* PRECR_SRA_PH_W */
@ -19888,22 +19888,22 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
gen_store_gpr(ctx, v1_t, ret);
break;
case NM_MULQ_S_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_mulq_s_ph(tcg_ctx, v1_t, v1_t, v2_t, tcg_ctx->cpu_env);
gen_store_gpr(ctx, v1_t, ret);
break;
case NM_MULQ_RS_W:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_mulq_rs_w(tcg_ctx, v1_t, v1_t, v2_t, tcg_ctx->cpu_env);
gen_store_gpr(ctx, v1_t, ret);
break;
case NM_MULQ_S_W:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_mulq_s_w(tcg_ctx, v1_t, v1_t, v2_t, tcg_ctx->cpu_env);
gen_store_gpr(ctx, v1_t, ret);
break;
case NM_APPEND:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_load_gpr(ctx, t0, rs);
if (rd != 0) {
tcg_gen_deposit_tl(tcg_ctx, tcg_ctx->cpu_gpr[rt], t0, tcg_ctx->cpu_gpr[rt], rd, 32 - rd);
@ -19921,7 +19921,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
gen_store_gpr(ctx, v1_t, ret);
break;
case NM_SHRLV_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_shrl_ph(tcg_ctx, v1_t, v1_t, v2_t);
gen_store_gpr(ctx, v1_t, ret);
break;
@ -19963,7 +19963,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
gen_store_gpr(ctx, v1_t, ret);
break;
case NM_MUL_S_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
switch (extract32(ctx->opcode, 10, 1)) {
case 0:
/* MUL_PH */
@ -19978,7 +19978,7 @@ static void gen_pool32a5_nanomips_insn(DisasContext *ctx, int opc,
}
break;
case NM_PRECR_QB_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_precr_qb_ph(tcg_ctx, v1_t, v1_t, v2_t);
gen_store_gpr(ctx, v1_t, ret);
break;
@ -20789,7 +20789,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
gen_compute_branch_cp1_nm(ctx, OPC_BC1NEZ, rt, s);
break;
case NM_BPOSGE32C:
check_dspr3(ctx);
check_dsp_r3(ctx);
{
int32_t imm = extract32(ctx->opcode, 1, 13) |
extract32(ctx->opcode, 0, 1) << 13;
@ -21298,7 +21298,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
switch (op1) {
/* OPC_MULT_G_2E is equal OPC_ADDUH_QB_DSP */
case OPC_MULT_G_2E:
check_dspr2(ctx);
check_dsp_r2(ctx);
switch (op2) {
case OPC_ADDUH_QB:
gen_helper_adduh_qb(tcg_ctx, cpu_gpr[ret], v1_t, v2_t);
@ -21341,7 +21341,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
case OPC_ABSQ_S_PH_DSP:
switch (op2) {
case OPC_ABSQ_S_QB:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_absq_s_qb(tcg_ctx, cpu_gpr[ret], v2_t, tcg_ctx->cpu_env);
break;
case OPC_ABSQ_S_PH:
@ -21420,11 +21420,11 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_addu_s_qb(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_ADDU_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_addu_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_ADDU_S_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_addu_s_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_SUBQ_PH:
@ -21448,11 +21448,11 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_subu_s_qb(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_SUBU_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_subu_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_SUBU_S_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_subu_s_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_ADDSC:
@ -21476,7 +21476,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
case OPC_CMPU_EQ_QB_DSP:
switch (op2) {
case OPC_PRECR_QB_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_precr_qb_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t);
break;
case OPC_PRECRQ_QB_PH:
@ -21484,7 +21484,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_precrq_qb_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t);
break;
case OPC_PRECR_SRA_PH_W:
check_dspr2(ctx);
check_dsp_r2(ctx);
{
TCGv_i32 sa_t = tcg_const_i32(tcg_ctx, v2);
gen_helper_precr_sra_ph_w(tcg_ctx, cpu_gpr[ret], sa_t, v1_t,
@ -21493,7 +21493,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
break;
}
case OPC_PRECR_SRA_R_PH_W:
check_dspr2(ctx);
check_dsp_r2(ctx);
{
TCGv_i32 sa_t = tcg_const_i32(tcg_ctx, v2);
gen_helper_precr_sra_r_ph_w(tcg_ctx, cpu_gpr[ret], sa_t, v1_t,
@ -21575,7 +21575,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_preceu_qh_obra(tcg_ctx, cpu_gpr[ret], v2_t);
break;
case OPC_ABSQ_S_OB:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_absq_s_ob(tcg_ctx, cpu_gpr[ret], v2_t, tcg_ctx->cpu_env);
break;
case OPC_ABSQ_S_PW:
@ -21619,19 +21619,19 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_subu_s_ob(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_SUBU_QH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_subu_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_SUBU_S_QH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_subu_s_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_SUBUH_OB:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_subuh_ob(tcg_ctx, cpu_gpr[ret], v1_t, v2_t);
break;
case OPC_SUBUH_R_OB:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_subuh_r_ob(tcg_ctx, cpu_gpr[ret], v1_t, v2_t);
break;
case OPC_ADDQ_PW:
@ -21659,19 +21659,19 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_addu_s_ob(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_ADDU_QH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_addu_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_ADDU_S_QH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_addu_s_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_ADDUH_OB:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_adduh_ob(tcg_ctx, cpu_gpr[ret], v1_t, v2_t);
break;
case OPC_ADDUH_R_OB:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_adduh_r_ob(tcg_ctx, cpu_gpr[ret], v1_t, v2_t);
break;
}
@ -21679,11 +21679,11 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
case OPC_CMPU_EQ_OB_DSP:
switch (op2) {
case OPC_PRECR_OB_QH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_precr_ob_qh(tcg_ctx, cpu_gpr[ret], v1_t, v2_t);
break;
case OPC_PRECR_SRA_QH_PW:
check_dspr2(ctx);
check_dsp_r2(ctx);
{
TCGv_i32 ret_t = tcg_const_i32(tcg_ctx, ret);
gen_helper_precr_sra_qh_pw(tcg_ctx, v2_t, v1_t, v2_t, ret_t);
@ -21691,7 +21691,7 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2,
break;
}
case OPC_PRECR_SRA_R_QH_PW:
check_dspr2(ctx);
check_dsp_r2(ctx);
{
TCGv_i32 sa_v = tcg_const_i32(tcg_ctx, ret);
gen_helper_precr_sra_r_qh_pw(tcg_ctx, v2_t, v1_t, v2_t, sa_v);
@ -21796,27 +21796,27 @@ static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
gen_helper_shrl_qb(tcg_ctx, cpu_gpr[ret], v1_t, v2_t);
break;
case OPC_SHRL_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_shrl_ph(tcg_ctx, cpu_gpr[ret], t0, v2_t);
break;
case OPC_SHRLV_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_shrl_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t);
break;
case OPC_SHRA_QB:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_shra_qb(tcg_ctx, cpu_gpr[ret], t0, v2_t);
break;
case OPC_SHRA_R_QB:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_shra_r_qb(tcg_ctx, cpu_gpr[ret], t0, v2_t);
break;
case OPC_SHRAV_QB:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_shra_qb(tcg_ctx, cpu_gpr[ret], v1_t, v2_t);
break;
case OPC_SHRAV_R_QB:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_shra_r_qb(tcg_ctx, cpu_gpr[ret], v1_t, v2_t);
break;
case OPC_SHRA_PH:
@ -21895,19 +21895,19 @@ static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
gen_helper_shll_s_qh(tcg_ctx, cpu_gpr[ret], v2_t, v1_t, tcg_ctx->cpu_env);
break;
case OPC_SHRA_OB:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_shra_ob(tcg_ctx, cpu_gpr[ret], v2_t, t0);
break;
case OPC_SHRAV_OB:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_shra_ob(tcg_ctx, cpu_gpr[ret], v2_t, v1_t);
break;
case OPC_SHRA_R_OB:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_shra_r_ob(tcg_ctx, cpu_gpr[ret], v2_t, t0);
break;
case OPC_SHRAV_R_OB:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_shra_r_ob(tcg_ctx, cpu_gpr[ret], v2_t, v1_t);
break;
case OPC_SHRA_PW:
@ -21951,11 +21951,11 @@ static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc,
gen_helper_shrl_ob(tcg_ctx, cpu_gpr[ret], v2_t, v1_t);
break;
case OPC_SHRL_QH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_shrl_qh(tcg_ctx, cpu_gpr[ret], v2_t, t0);
break;
case OPC_SHRLV_QH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_shrl_qh(tcg_ctx, cpu_gpr[ret], v2_t, v1_t);
break;
default: /* Invalid */
@ -21998,7 +21998,7 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
/* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
* the same mask and op1. */
case OPC_MULT_G_2E:
check_dspr2(ctx);
check_dsp_r2(ctx);
switch (op2) {
case OPC_MUL_PH:
gen_helper_mul_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
@ -22033,11 +22033,11 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_dpsu_h_qbr(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_DPA_W_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_dpa_w_ph(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_DPAX_W_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_dpax_w_ph(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_DPAQ_S_W_PH:
@ -22045,19 +22045,19 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_dpaq_s_w_ph(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_DPAQX_S_W_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_dpaqx_s_w_ph(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_DPAQX_SA_W_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_dpaqx_sa_w_ph(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_DPS_W_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_dps_w_ph(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_DPSX_W_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_dpsx_w_ph(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_DPSQ_S_W_PH:
@ -22065,11 +22065,11 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_dpsq_s_w_ph(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_DPSQX_S_W_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_dpsqx_s_w_ph(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_DPSQX_SA_W_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_dpsqx_sa_w_ph(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_MULSAQ_S_W_PH:
@ -22101,7 +22101,7 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_maq_sa_w_phr(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_MULSA_W_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_mulsa_w_ph(tcg_ctx, t0, v1_t, v2_t, tcg_ctx->cpu_env);
break;
}
@ -22130,7 +22130,7 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_dmsubu(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
break;
case OPC_DPA_W_QH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_dpa_w_qh(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
break;
case OPC_DPAQ_S_W_QH:
@ -22150,7 +22150,7 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_dpau_h_obr(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
break;
case OPC_DPS_W_QH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_dps_w_qh(tcg_ctx, v1_t, v2_t, t0, tcg_ctx->cpu_env);
break;
case OPC_DPSQ_S_W_QH:
@ -22244,7 +22244,7 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2,
gen_helper_muleq_s_w_phr(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_MULQ_S_PH:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_mulq_s_ph(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
break;
}
@ -22472,7 +22472,7 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
gen_helper_cmpgu_le_qb(tcg_ctx, cpu_gpr[ret], v1_t, v2_t);
break;
case OPC_CMPGDU_EQ_QB:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_cmpgu_eq_qb(tcg_ctx, t1, v1_t, v2_t);
tcg_gen_mov_tl(tcg_ctx, cpu_gpr[ret], t1);
tcg_gen_andi_tl(tcg_ctx, tcg_ctx->cpu_dspctrl, tcg_ctx->cpu_dspctrl, 0xF0FFFFFF);
@ -22480,7 +22480,7 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
tcg_gen_or_tl(tcg_ctx, tcg_ctx->cpu_dspctrl, tcg_ctx->cpu_dspctrl, t1);
break;
case OPC_CMPGDU_LT_QB:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_cmpgu_lt_qb(tcg_ctx, t1, v1_t, v2_t);
tcg_gen_mov_tl(tcg_ctx, cpu_gpr[ret], t1);
tcg_gen_andi_tl(tcg_ctx, tcg_ctx->cpu_dspctrl, tcg_ctx->cpu_dspctrl, 0xF0FFFFFF);
@ -22488,7 +22488,7 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
tcg_gen_or_tl(tcg_ctx, tcg_ctx->cpu_dspctrl, tcg_ctx->cpu_dspctrl, t1);
break;
case OPC_CMPGDU_LE_QB:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_cmpgu_le_qb(tcg_ctx, t1, v1_t, v2_t);
tcg_gen_mov_tl(tcg_ctx, cpu_gpr[ret], t1);
tcg_gen_andi_tl(tcg_ctx, tcg_ctx->cpu_dspctrl, tcg_ctx->cpu_dspctrl, 0xF0FFFFFF);
@ -22549,15 +22549,15 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx,
gen_helper_cmp_le_qh(tcg_ctx, v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_CMPGDU_EQ_OB:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_cmpgdu_eq_ob(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_CMPGDU_LT_OB:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_cmpgdu_lt_ob(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_CMPGDU_LE_OB:
check_dspr2(ctx);
check_dsp_r2(ctx);
gen_helper_cmpgdu_le_ob(tcg_ctx, cpu_gpr[ret], v1_t, v2_t, tcg_ctx->cpu_env);
break;
case OPC_CMPGU_EQ_OB:
@ -22617,7 +22617,7 @@ static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx,
TCGv *cpu_gpr = tcg_ctx->cpu_gpr;
TCGv t0;
check_dspr2(ctx);
check_dsp_r2(ctx);
if (rt == 0) {
/* Treat as NOP. */
@ -23499,7 +23499,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
case OPC_MULTU_G_2E:
/* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have
* the same mask and op1. */
if ((ctx->insn_flags & ASE_DSPR2) && (op1 == OPC_MULT_G_2E)) {
if ((ctx->insn_flags & ASE_DSP_R2) && (op1 == OPC_MULT_G_2E)) {
op2 = MASK_ADDUH_QB(ctx->opcode);
switch (op2) {
case OPC_ADDUH_QB:

8
qemu/target/mips/translate_init.c
View file

@ -444,7 +444,7 @@ const mips_def_t mips_defs[] =
32,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
0,
CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSP_R2,
MMU_TYPE_R4000,
},
{
@ -659,7 +659,7 @@ const mips_def_t mips_defs[] =
0,
(1 << CP0PG_IEC) | (1 << CP0PG_XIE) | (1U << CP0PG_RIE),
0,
CPU_NANOMIPS32 | ASE_DSP | ASE_DSPR2 | ASE_DSPR3 | ASE_MT,
CPU_NANOMIPS32 | ASE_DSP | ASE_DSP_R2 | ASE_DSP_R3 | ASE_MT,
MMU_TYPE_R4000,
},
#if defined(TARGET_MIPS64)
@ -1052,7 +1052,7 @@ const mips_def_t mips_defs[] =
MMU_TYPE_R4000,
},
{
/* A generic CPU providing MIPS64 ASE DSP 2 features.
/* A generic CPU providing MIPS64 DSP R2 ASE features.
FIXME: Eventually this should be replaced by a real CPU model. */
"mips64dspr2",
0x00010000,
@ -1089,7 +1089,7 @@ const mips_def_t mips_defs[] =
36,
0,0, 0,0, 0,0, 0,0, 0,0, 0,0,
0,
CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
CPU_MIPS64R2 | ASE_DSP | ASE_DSP_R2,
MMU_TYPE_R4000,
},
#endif