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fpu/softfloat: Clean up parts_default_nan

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Reduce the number of ifdefs. Correct the result for OpenRISC
and TriCore (although TriCore fixed in target-specific code).

Backports commit 8fb3d90203f328d1bebcf7f20934027bfc4e7f3f from qemu
This commit is contained in:
Richard Henderson 2018-05-20 00:11:24 -04:00 committed by Lioncash
parent df3436b518
commit 65c768593c
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1 changed files with 14 additions and 7 deletions
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21
qemu/fpu/softfloat-specialize.h
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@ -130,22 +130,29 @@ static FloatParts parts_default_nan(float_status *status)
FloatParts result;
#if defined(TARGET_SPARC) || defined(TARGET_M68K)
/* !snan_bit_is_one, set all bits */
frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \
defined(TARGET_S390X) || defined(TARGET_RISCV)
#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
|| defined(TARGET_MICROBLAZE)
/* !snan_bit_is_one, set sign and msb */
frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
sign = 1;
#elif defined(TARGET_HPPA)
/* snan_bit_is_one, set msb-1. */
frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
#else
/* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
* S390, SH4, TriCore, and Xtensa. I cannot find documentation
* for Unicore32; the choice from the original commit is unchanged.
* Our other supported targets, CRIS, LM32, Moxie, Nios2, and Tile,
* do not have floating-point.
*/
if (snan_bit_is_one(status)) {
/* set all bits other than msb */
frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
} else {
#if defined(TARGET_MIPS)
/* set msb */
frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
#else
frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
sign = 1;
#endif
}
#endif