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fpu/softfloat: Clean up parts_default_nan
Reduce the number of ifdefs. Correct the result for OpenRISC and TriCore (although TriCore fixed in target-specific code). Backports commit 8fb3d90203f328d1bebcf7f20934027bfc4e7f3f from qemu
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@ -130,22 +130,29 @@ static FloatParts parts_default_nan(float_status *status)
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FloatParts result;
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FloatParts result;
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#if defined(TARGET_SPARC) || defined(TARGET_M68K)
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#if defined(TARGET_SPARC) || defined(TARGET_M68K)
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/* !snan_bit_is_one, set all bits */
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frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
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frac = (1ULL << DECOMPOSED_BINARY_POINT) - 1;
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#elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA) || \
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#elif defined(TARGET_I386) || defined(TARGET_X86_64) \
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defined(TARGET_S390X) || defined(TARGET_RISCV)
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|| defined(TARGET_MICROBLAZE)
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frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
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/* !snan_bit_is_one, set sign and msb */
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#elif defined(TARGET_HPPA)
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frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
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#else
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if (snan_bit_is_one(status)) {
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frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
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} else {
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#if defined(TARGET_MIPS)
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frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
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#else
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frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
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frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
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sign = 1;
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sign = 1;
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#endif
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#elif defined(TARGET_HPPA)
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/* snan_bit_is_one, set msb-1. */
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frac = 1ULL << (DECOMPOSED_BINARY_POINT - 2);
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#else
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/* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V,
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* S390, SH4, TriCore, and Xtensa. I cannot find documentation
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* for Unicore32; the choice from the original commit is unchanged.
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* Our other supported targets, CRIS, LM32, Moxie, Nios2, and Tile,
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* do not have floating-point.
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*/
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if (snan_bit_is_one(status)) {
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/* set all bits other than msb */
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frac = (1ULL << (DECOMPOSED_BINARY_POINT - 1)) - 1;
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} else {
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/* set msb */
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frac = 1ULL << (DECOMPOSED_BINARY_POINT - 1);
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}
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}
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#endif
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#endif
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