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https://github.com/yuzu-emu/unicorn.git
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target-arm: Add registers for PMSAv7
Define the arm CP registers for PMSAv7 and their accessor functions. RGNR serves as a shared index that indexes into arrays storing the DRBAR, DRSR and DRACR registers. DRBAR and friends have to be VMSDd separately from the CP interface using a new PMSA specific VMSD subsection. Backports commit 6cb0b013a1fa421cdfb83257cd33f855cc90649a from qemu
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7d933a6ba9
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@ -497,6 +497,12 @@ static int arm_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err
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error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32 "\n", nr);
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return -1;
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}
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if (nr) {
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env->pmsav7.drbar = g_new0(uint32_t, nr);
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env->pmsav7.drsr = g_new0(uint32_t, nr);
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env->pmsav7.dracr = g_new0(uint32_t, nr);
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}
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}
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if (arm_feature(env, ARM_FEATURE_EL3)) {
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@ -288,6 +288,9 @@ typedef struct CPUARMState {
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};
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uint64_t par_el[4];
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};
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uint32_t c6_rgnr;
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uint32_t c9_insn; /* Cache lockdown registers. */
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uint32_t c9_data;
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uint64_t c9_pmcr; /* performance monitor control register */
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@ -487,6 +490,13 @@ typedef struct CPUARMState {
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/* Internal CPU feature flags. */
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uint64_t features;
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/* PMSAv7 MPU */
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struct {
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uint32_t *drbar;
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uint32_t *drsr;
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uint32_t *dracr;
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} pmsav7;
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void *nvic;
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const struct arm_boot_info *boot_info;
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@ -1485,6 +1485,77 @@ static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
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return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
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}
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static uint64_t pmsav7_read(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
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if (!u32p) {
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return 0;
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}
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u32p += env->cp15.c6_rgnr;
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return *u32p;
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}
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static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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ARMCPU *cpu = arm_env_get_cpu(env);
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uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
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if (!u32p) {
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return;
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}
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u32p += env->cp15.c6_rgnr;
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tlb_flush(CPU(cpu), 1); /* Mappings may have changed - purge! */
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*u32p = value;
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}
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static void pmsav7_reset(CPUARMState *env, const ARMCPRegInfo *ri)
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{
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ARMCPU *cpu = arm_env_get_cpu(env);
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uint32_t *u32p = *(uint32_t **)raw_ptr(env, ri);
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if (!u32p) {
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return;
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}
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memset(u32p, 0, sizeof(*u32p) * cpu->pmsav7_dregion);
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}
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static void pmsav7_rgnr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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ARMCPU *cpu = arm_env_get_cpu(env);
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uint32_t nrgs = cpu->pmsav7_dregion;
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if (value >= nrgs) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"PMSAv7 RGNR write >= # supported regions, %" PRIu32
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" > %" PRIu32 "\n", (uint32_t)value, nrgs);
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return;
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}
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raw_write(env, ri, value);
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}
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static const ARMCPRegInfo pmsav7_cp_reginfo[] = {
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{ "DRBAR", 15,6,1, 0,0,0, 0,ARM_CP_NO_RAW,
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PL1_RW, 0, NULL, 0, offsetof(CPUARMState, pmsav7.drbar), {0, 0},
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NULL, pmsav7_read, pmsav7_write, NULL, NULL, pmsav7_reset },
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{ "DRSR", 15,6,1, 0,0,2, 0,ARM_CP_NO_RAW,
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PL1_RW, 0, NULL, 0, offsetof(CPUARMState, pmsav7.drsr), {0, 0},
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NULL, pmsav7_read, pmsav7_write, NULL, NULL, pmsav7_reset },
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{ "DRACR", 15,6,1, 0,0,4, 0,ARM_CP_NO_RAW,
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PL1_RW, 0, NULL, 0, offsetof(CPUARMState, pmsav7.dracr), {0, 0},
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NULL, pmsav7_read, pmsav7_write, NULL, NULL, pmsav7_reset },
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{ "RGNR", 15,6,2, 0,0,0, 0,0,
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PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.c6_rgnr), {0, 0},
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NULL, NULL, pmsav7_rgnr_write },
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REGINFO_SENTINEL
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};
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static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
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{ "DATA_AP", 15,5,0, 0,0,0, 0,
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ARM_CP_ALIAS, PL1_RW, 0, NULL, 0, offsetof(CPUARMState, cp15.pmsav5_data_ap), {0, 0},
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@ -2862,13 +2933,14 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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define_one_arm_cp_reg(cpu, &rvbar);
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}
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if (arm_feature(env, ARM_FEATURE_MPU)) {
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/* These are the MPU registers prior to PMSAv6. Any new
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* PMSA core later than the ARM946 will require that we
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* implement the PMSAv6 or PMSAv7 registers, which are
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* completely different.
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*/
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assert(!arm_feature(env, ARM_FEATURE_V6));
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define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
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if (arm_feature(env, ARM_FEATURE_V6)) {
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/* PMSAv6 not implemented */
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assert(arm_feature(env, ARM_FEATURE_V7));
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define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
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define_arm_cp_regs(cpu, pmsav7_cp_reginfo);
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} else {
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define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
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}
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} else {
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define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo);
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define_arm_cp_regs(cpu, vmsa_cp_reginfo);
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@ -21,27 +21,27 @@ void arm_release(void* ctx);
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void arm_release(void* ctx)
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{
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ARMCPU* cpu;
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struct uc_struct* uc;
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TCGContext *s = (TCGContext *) ctx;
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struct uc_struct* uc = s->uc;
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ARMCPU* cpu = (ARMCPU*) uc->cpu;
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CPUArchState *env = &cpu->env;
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g_free(s->tb_ctx.tbs);
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uc = s->uc;
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cpu = (ARMCPU*) uc->cpu;
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g_free(cpu->cpreg_indexes);
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g_free(cpu->cpreg_values);
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g_free(cpu->cpreg_vmstate_indexes);
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g_free(cpu->cpreg_vmstate_values);
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g_free(env->pmsav7.drbar);
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g_free(env->pmsav7.drsr);
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g_free(env->pmsav7.dracr);
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release_common(ctx);
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}
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void arm_reg_reset(struct uc_struct *uc)
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{
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CPUArchState *env;
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(void)uc;
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CPUArchState *env = uc->cpu->env_ptr;
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env = uc->cpu->env_ptr;
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memset(env->regs, 0, sizeof(env->regs));
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env->pc = 0;
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