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target-arm: Fix RVBAR_EL1 register encoding

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Fix the RVBAR_EL1 CP register opc2 encoding from 2 to 1

Backports commit 569b49f864e7593a14182acae5a7f5981f6ec24f from qemu
This commit is contained in:
Greg Bellows 2018-02-12 10:27:06 -05:00 committed by Lioncash
parent 9b28dc55c8
commit 6c33ec25fc
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 1 additions and 1 deletions
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2
qemu/target-arm/helper.c
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@ -2601,7 +2601,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
REGINFO_SENTINEL
};
ARMCPRegInfo rvbar = {
"RVBAR_EL1", 0,12,0, 3,0,2, ARM_CP_STATE_AA64,
"RVBAR_EL1", 0,12,0, 3,0,1, ARM_CP_STATE_AA64,
ARM_CP_CONST, PL1_R, 0, NULL, cpu->rvbar
};
define_one_arm_cp_reg(cpu, &rvbar);