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target-m68k: Implement bfffo

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Backports commit a45f1763cc501861ea4f5eed06e6f58aa681a082 from qemu
This commit is contained in:
Richard Henderson 2018-03-01 19:10:53 -05:00 committed by Lioncash
parent 797e5d44e9
commit 6f5081314b
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GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 62 additions and 1 deletions
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3
qemu/target-m68k/helper.h
View file

@ -53,10 +53,13 @@ DEF_HELPER_2(set_ccr, void, env, i32)
DEF_HELPER_FLAGS_1(get_ccr, TCG_CALL_NO_WG_SE, i32, env)
DEF_HELPER_2(raise_exception, void, env, i32)
DEF_HELPER_FLAGS_3(bfffo_reg, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32)
DEF_HELPER_FLAGS_4(bfexts_mem, TCG_CALL_NO_WG, i32, env, i32, s32, i32)
DEF_HELPER_FLAGS_4(bfextu_mem, TCG_CALL_NO_WG, i64, env, i32, s32, i32)
DEF_HELPER_FLAGS_5(bfins_mem, TCG_CALL_NO_WG, i32, env, i32, i32, s32, i32)
DEF_HELPER_FLAGS_4(bfchg_mem, TCG_CALL_NO_WG, i32, env, i32, s32, i32)
DEF_HELPER_FLAGS_4(bfclr_mem, TCG_CALL_NO_WG, i32, env, i32, s32, i32)
DEF_HELPER_FLAGS_4(bfset_mem, TCG_CALL_NO_WG, i32, env, i32, s32, i32)
DEF_HELPER_FLAGS_4(bfffo_mem, TCG_CALL_NO_WG, i64, env, i32, s32, i32)

21
qemu/target-m68k/op_helper.c
View file

@ -646,3 +646,24 @@ uint32_t HELPER(bfset_mem)(CPUM68KState *env, uint32_t addr,
return ((data & mask) << d.bofs) >> 32;
}
uint32_t HELPER(bfffo_reg)(uint32_t n, uint32_t ofs, uint32_t len)
{
return (n ? clz32(n) : len) + ofs;
}
uint64_t HELPER(bfffo_mem)(CPUM68KState *env, uint32_t addr,
int32_t ofs, uint32_t len)
{
uintptr_t ra = GETPC();
struct bf_data d = bf_prep(addr, ofs, len);
uint64_t data = bf_load(env, d.addr, d.blen, ra);
uint64_t mask = -1ull << (64 - d.len) >> d.bofs;
uint64_t n = (data & mask) << d.bofs;
uint32_t ffo = helper_bfffo_reg(n >> 32, ofs, d.len);
/* Return FFO in the low word and N in the high word.
Note that because of MASK and the shift, the low word
is already zero. */
return n | ffo;
}

39
qemu/target-m68k/translate.c
View file

@ -3767,7 +3767,14 @@ DISAS_INSN(bfop_reg)
TCGv src = DREG(insn, 0);
int len = ((extract32(ext, 0, 5) - 1) & 31) + 1;
int ofs = extract32(ext, 6, 5); /* big bit-endian */
TCGv mask;
TCGv mask, tofs, tlen;
TCGV_UNUSED(tofs);
TCGV_UNUSED(tlen);
if ((insn & 0x0f00) == 0x0d00) { /* bfffo */
tofs = tcg_temp_new(tcg_ctx);
tlen = tcg_temp_new(tcg_ctx);
}
if ((ext & 0x820) == 0) {
/* Immediate width and offset. */
@ -3779,6 +3786,10 @@ DISAS_INSN(bfop_reg)
}
tcg_gen_andi_i32(tcg_ctx, tcg_ctx->QREG_CC_N, tcg_ctx->QREG_CC_N, ~maski);
mask = tcg_const_i32(tcg_ctx, ror32(maski, ofs));
if (!TCGV_IS_UNUSED(tofs)) {
tcg_gen_movi_i32(tcg_ctx, tofs, ofs);
tcg_gen_movi_i32(tcg_ctx, tlen, len);
}
} else {
TCGv tmp = tcg_temp_new(tcg_ctx);
if (ext & 0x20) {
@ -3787,9 +3798,15 @@ DISAS_INSN(bfop_reg)
tcg_gen_andi_i32(tcg_ctx, tmp, tmp, 31);
mask = tcg_const_i32(tcg_ctx, 0x7fffffffu);
tcg_gen_shr_i32(tcg_ctx, mask, mask, tmp);
if (!TCGV_IS_UNUSED(tlen)) {
tcg_gen_addi_i32(tcg_ctx, tlen, tmp, 1);
}
} else {
/* Immediate width */
mask = tcg_const_i32(tcg_ctx, 0x7fffffffu >> (len - 1));
if (!TCGV_IS_UNUSED(tlen)) {
tcg_gen_movi_i32(tcg_ctx, tlen, len);
}
}
if (ext & 0x800) {
/* Variable offset */
@ -3797,11 +3814,17 @@ DISAS_INSN(bfop_reg)
tcg_gen_rotl_i32(tcg_ctx, tcg_ctx->QREG_CC_N, src, tmp);
tcg_gen_andc_i32(tcg_ctx, tcg_ctx->QREG_CC_N, tcg_ctx->QREG_CC_N, mask);
tcg_gen_rotr_i32(tcg_ctx, mask, mask, tmp);
if (!TCGV_IS_UNUSED(tofs)) {
tcg_gen_mov_i32(tcg_ctx, tofs, tmp);
}
} else {
/* Immediate offset (and variable width) */
tcg_gen_rotli_i32(tcg_ctx, tcg_ctx->QREG_CC_N, src, ofs);
tcg_gen_andc_i32(tcg_ctx, tcg_ctx->QREG_CC_N, tcg_ctx->QREG_CC_N, mask);
tcg_gen_rotri_i32(tcg_ctx, mask, mask, ofs);
if (!TCGV_IS_UNUSED(tofs)) {
tcg_gen_movi_i32(tcg_ctx, tofs, ofs);
}
}
tcg_temp_free(tcg_ctx, tmp);
}
@ -3814,6 +3837,11 @@ DISAS_INSN(bfop_reg)
case 0x0c00: /* bfclr */
tcg_gen_and_i32(tcg_ctx, src, src, mask);
break;
case 0x0d00: /* bfffo */
gen_helper_bfffo_reg(tcg_ctx, DREG(ext, 12), tcg_ctx->QREG_CC_N, tofs, tlen);
tcg_temp_free(tcg_ctx, tlen);
tcg_temp_free(tcg_ctx, tofs);
break;
case 0x0e00: /* bfset */
tcg_gen_orc_i32(tcg_ctx, src, src, mask);
break;
@ -3831,6 +3859,7 @@ DISAS_INSN(bfop_mem)
TCGContext *tcg_ctx = s->uc->tcg_ctx;
int ext = read_im16(env, s);
TCGv addr, len, ofs;
TCGv_i64 t64;
addr = gen_lea(env, s, insn, OS_UNSIZED);
if (IS_NULL_QREG(addr)) {
@ -3856,6 +3885,12 @@ DISAS_INSN(bfop_mem)
case 0x0c00: /* bfclr */
gen_helper_bfclr_mem(tcg_ctx, tcg_ctx->QREG_CC_N, tcg_ctx->cpu_env, addr, ofs, len);
break;
case 0x0d00: /* bfffo */
t64 = tcg_temp_new_i64(tcg_ctx);
gen_helper_bfffo_mem(tcg_ctx, t64, tcg_ctx->cpu_env, addr, ofs, len);
tcg_gen_extr_i64_i32(tcg_ctx, DREG(ext, 12), tcg_ctx->QREG_CC_N, t64);
tcg_temp_free_i64(tcg_ctx, t64);
break;
case 0x0e00: /* bfset */
gen_helper_bfset_mem(tcg_ctx, tcg_ctx->QREG_CC_N, tcg_ctx->cpu_env, addr, ofs, len);
break;
@ -5114,6 +5149,8 @@ void register_m68k_insns (CPUM68KState *env)
INSN(bfop_reg, eac0, fff8, BITFIELD); /* bfchg */
INSN(bfop_mem, ecc0, ffc0, BITFIELD); /* bfclr */
INSN(bfop_reg, ecc0, fff8, BITFIELD); /* bfclr */
INSN(bfop_mem, edc0, ffc0, BITFIELD); /* bfffo */
INSN(bfop_reg, edc0, fff8, BITFIELD); /* bfffo */
INSN(bfop_mem, eec0, ffc0, BITFIELD); /* bfset */
INSN(bfop_reg, eec0, fff8, BITFIELD); /* bfset */
INSN(bfop_mem, e8c0, ffc0, BITFIELD); /* bftst */