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aarch64: Add exception syndrome pseudo register.

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This commit is contained in:
bunnei 2018-01-03 19:41:12 -05:00
parent ec39a51d60
commit 73f4573535
2 changed files with 4 additions and 0 deletions
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1
include/unicorn/arm64.h
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@ -284,6 +284,7 @@ typedef enum uc_arm64_reg {
UC_ARM64_REG_PC, // program counter register UC_ARM64_REG_PC, // program counter register
UC_ARM64_REG_CPACR_EL1, UC_ARM64_REG_CPACR_EL1,
UC_ARM64_REG_ESR,
//> thread registers //> thread registers
UC_ARM64_REG_TPIDR_EL0, UC_ARM64_REG_TPIDR_EL0,

3
qemu/target-arm/unicorn_aarch64.c
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@ -79,6 +79,9 @@ int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int co
case UC_ARM64_REG_CPACR_EL1: case UC_ARM64_REG_CPACR_EL1:
*(uint32_t *)value = ARM_CPU(uc, mycpu)->env.cp15.c1_coproc; *(uint32_t *)value = ARM_CPU(uc, mycpu)->env.cp15.c1_coproc;
break; break;
case UC_ARM64_REG_ESR:
*(uint32_t *)value = ARM_CPU(uc, mycpu)->env.exception.syndrome;
break;
case UC_ARM64_REG_TPIDR_EL0: case UC_ARM64_REG_TPIDR_EL0:
*(int64_t *)value = ARM_CPU(uc, mycpu)->env.cp15.tpidr_el0; *(int64_t *)value = ARM_CPU(uc, mycpu)->env.cp15.tpidr_el0;
break; break;