target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN

Writes to AdvSIMD registers flush the bits above 128.

Backports commit 33649de62e40df0060a1c514574e4ef25c4e52e1 from qemu
This commit is contained in:
Richard Henderson 2020-03-21 17:56:37 -04:00 committed by Lioncash
parent 6eb8472344
commit 74cbfceb56

View file

@ -7309,6 +7309,7 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
tcg_temp_free_i64(tcg_ctx, tcg_resl);
write_vec_element(s, tcg_resh, rd, 1, MO_64);
tcg_temp_free_i64(tcg_ctx, tcg_resh);
clear_vec_high(s, true, rd);
}
/*