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target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN
Writes to AdvSIMD registers flush the bits above 128. Backports commit 33649de62e40df0060a1c514574e4ef25c4e52e1 from qemu
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@ -7309,6 +7309,7 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn)
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tcg_temp_free_i64(tcg_ctx, tcg_resl);
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write_vec_element(s, tcg_resh, rd, 1, MO_64);
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tcg_temp_free_i64(tcg_ctx, tcg_resh);
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clear_vec_high(s, true, rd);
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}
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/*
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