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target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode

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In the ARM ldr/str decode path, rather than directly testing
"insn & (1 << 21)" and "insn & (1 << 24)", abstract these
bits out into wbit and pbit local flags. (We will want to
do more tests against them to determine whether we need to
provide syndrome information.)

Backports commit 63f26fcfda8e19f94ce23336726d14805250a5b6 from qemu
This commit is contained in:
Peter Maydell 2018-03-02 00:26:50 -05:00 committed by Lioncash
parent cc217b0c90
commit 74d42aa939
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 6 additions and 3 deletions
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9
qemu/target/arm/translate.c
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@ -8935,6 +8935,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) // qq
} else {
int address_offset;
bool load = insn & (1 << 20);
bool wbit = insn & (1 << 21);
bool pbit = insn & (1 << 24);
bool doubleword = false;
/* Misc load/store */
rn = (insn >> 16) & 0xf;
@ -8952,8 +8954,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) // qq
}
addr = load_reg(s, rn);
if (insn & (1 << 24))
if (pbit) {
gen_add_datah_offset(s, insn, 0, addr);
}
address_offset = 0;
if (doubleword) {
@ -9002,10 +9005,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn) // qq
ensure correct behavior with overlapping index registers.
ldrd with base writeback is is undefined if the
destination and index registers overlap. */
if (!(insn & (1 << 24))) {
if (!pbit) {
gen_add_datah_offset(s, insn, address_offset, addr);
store_reg(s, rn, addr);
} else if (insn & (1 << 21)) {
} else if (wbit) {
if (address_offset)
tcg_gen_addi_i32(tcg_ctx, addr, addr, address_offset);
store_reg(s, rn, addr);