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xorstream 2017-01-21 12:28:22 +11:00
parent df41c49e2d
commit 770c5616e2
69 changed files with 3839 additions and 3839 deletions
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4
bindings/java/unicorn_Unicorn.c
View file

@ -334,7 +334,7 @@ JNIEXPORT jlong JNICALL Java_unicorn_Unicorn_open
*/ */
JNIEXPORT jint JNICALL Java_unicorn_Unicorn_version JNIEXPORT jint JNICALL Java_unicorn_Unicorn_version
(JNIEnv *env, jclass clz) { (JNIEnv *env, jclass clz) {
return (jint)uc_version(NULL, NULL); return (jint)uc_version(NULL, NULL);
} }
/* /*
@ -344,7 +344,7 @@ JNIEXPORT jint JNICALL Java_unicorn_Unicorn_version
*/ */
JNIEXPORT jboolean JNICALL Java_unicorn_Unicorn_arch_1supported JNIEXPORT jboolean JNICALL Java_unicorn_Unicorn_arch_1supported
(JNIEnv *env, jclass clz, jint arch) { (JNIEnv *env, jclass clz, jint arch) {
return (jboolean)(uc_arch_supported((uc_arch)arch) != 0); return (jboolean)(uc_arch_supported((uc_arch)arch) != 0);
} }
/* /*

100
bindings/msvc/samples/main.c
View file

@ -31,11 +31,11 @@
// It should loop 3 times before ending. // It should loop 3 times before ending.
const uint64_t addr = 0x100000; const uint64_t addr = 0x100000;
const unsigned char loop_test_code[] = { const unsigned char loop_test_code[] = {
0x02,0x00,0x04,0x24, // 100000: li $a0, 2 0x02,0x00,0x04,0x24, // 100000: li $a0, 2
// loop1 // loop1
0x00,0x00,0x00,0x00, // 100004: nop 0x00,0x00,0x00,0x00, // 100004: nop
0xFE,0xFF,0x80,0x14, // 100008: bnez $a0, loop1 0xFE,0xFF,0x80,0x14, // 100008: bnez $a0, loop1
0xFF,0xFF,0x84,0x24, // 10000C: addiu $a0, -1 0xFF,0xFF,0x84,0x24, // 10000C: addiu $a0, -1
}; };
bool test_passed_ok = false; bool test_passed_ok = false;
int loop_count = 0; int loop_count = 0;
@ -43,14 +43,14 @@ int loop_count = 0;
static void mips_codehook(uc_engine *uc, uint64_t address, uint32_t size, void *user_data) static void mips_codehook(uc_engine *uc, uint64_t address, uint32_t size, void *user_data)
{ {
if( address == 0x10000C ) if( address == 0x10000C )
test_passed_ok = true; test_passed_ok = true;
if( address == 0x100004 ) if( address == 0x100004 )
{ {
printf("\nloop %d:\n", loop_count); printf("\nloop %d:\n", loop_count);
loop_count++; loop_count++;
} }
printf("Code: %llX\n", address); printf("Code: %llX\n", address);
} }
@ -58,76 +58,76 @@ int main(int argc, char **argv, char **envp)
{ {
uc_engine *uc; uc_engine *uc;
uc_err err; uc_err err;
uc_hook hhc; uc_hook hhc;
uint32_t val; uint32_t val;
// dynamically load shared library // dynamically load shared library
#ifdef DYNLOAD #ifdef DYNLOAD
if( !uc_dyn_load(NULL, 0) ) if( !uc_dyn_load(NULL, 0) )
{ {
printf("Error dynamically loading shared library.\n"); printf("Error dynamically loading shared library.\n");
printf("Please check that unicorn.dll/unicorn.so is available as well as\n"); printf("Please check that unicorn.dll/unicorn.so is available as well as\n");
printf("any other dependent dll/so files.\n"); printf("any other dependent dll/so files.\n");
printf("The easiest way is to place them in the same directory as this app.\n"); printf("The easiest way is to place them in the same directory as this app.\n");
return 1; return 1;
} }
#endif #endif
// Initialize emulator in MIPS 32bit little endian mode // Initialize emulator in MIPS 32bit little endian mode
err = uc_open(UC_ARCH_MIPS, UC_MODE_MIPS32 | UC_MODE_LITTLE_ENDIAN, &uc); err = uc_open(UC_ARCH_MIPS, UC_MODE_MIPS32 | UC_MODE_LITTLE_ENDIAN, &uc);
if (err) if (err)
{ {
printf("Failed on uc_open() with error returned: %u\n", err); printf("Failed on uc_open() with error returned: %u\n", err);
return err; return err;
} }
// map in a page of mem // map in a page of mem
err = uc_mem_map(uc, addr, 0x1000, UC_PROT_ALL); err = uc_mem_map(uc, addr, 0x1000, UC_PROT_ALL);
if (err) if (err)
{ {
printf("Failed on uc_mem_map() with error returned: %u\n", err); printf("Failed on uc_mem_map() with error returned: %u\n", err);
return err; return err;
} }
// write machine code to be emulated to memory // write machine code to be emulated to memory
err = uc_mem_write(uc, addr, loop_test_code, sizeof(loop_test_code)); err = uc_mem_write(uc, addr, loop_test_code, sizeof(loop_test_code));
if( err ) if( err )
{ {
printf("Failed on uc_mem_write() with error returned: %u\n", err); printf("Failed on uc_mem_write() with error returned: %u\n", err);
return err; return err;
} }
// hook all instructions by having @begin > @end // hook all instructions by having @begin > @end
uc_hook_add(uc, &hhc, UC_HOOK_CODE, mips_codehook, NULL, (uint64_t)1, (uint64_t)0); uc_hook_add(uc, &hhc, UC_HOOK_CODE, mips_codehook, NULL, (uint64_t)1, (uint64_t)0);
if( err ) if( err )
{ {
printf("Failed on uc_hook_add(code) with error returned: %u\n", err); printf("Failed on uc_hook_add(code) with error returned: %u\n", err);
return err; return err;
} }
// execute code // execute code
printf("---- Executing Code ----\n"); printf("---- Executing Code ----\n");
err = uc_emu_start(uc, addr, addr + sizeof(loop_test_code), 0, 0); err = uc_emu_start(uc, addr, addr + sizeof(loop_test_code), 0, 0);
if (err) if (err)
{ {
printf("Failed on uc_emu_start() with error returned %u: %s\n", printf("Failed on uc_emu_start() with error returned %u: %s\n",
err, uc_strerror(err)); err, uc_strerror(err));
return err; return err;
} }
// done executing, print some reg values as a test // done executing, print some reg values as a test
printf("---- Execution Complete ----\n\n"); printf("---- Execution Complete ----\n\n");
uc_reg_read(uc, UC_MIPS_REG_PC, &val); printf("pc is %X\n", val); uc_reg_read(uc, UC_MIPS_REG_PC, &val); printf("pc is %X\n", val);
uc_reg_read(uc, UC_MIPS_REG_A0, &val); printf("a0 is %X\n", val); uc_reg_read(uc, UC_MIPS_REG_A0, &val); printf("a0 is %X\n", val);
// free resources // free resources
uc_close(uc); uc_close(uc);
// dynamically free shared library // dynamically free shared library
#ifdef DYNLOAD #ifdef DYNLOAD
uc_dyn_free(); uc_dyn_free();
#endif #endif
return 0; return 0;
} }

26
bindings/msvc/unicorn_dynload.c
View file

@ -154,12 +154,12 @@ bool uc_dyn_load(const char* path, int flags)
gp_uc_mem_protect = (uc_mem_protect_t)DYNLOAD_GETFUNC(g_dyn_handle, "uc_mem_protect"); gp_uc_mem_protect = (uc_mem_protect_t)DYNLOAD_GETFUNC(g_dyn_handle, "uc_mem_protect");
gp_uc_mem_regions = (uc_mem_regions_t)DYNLOAD_GETFUNC(g_dyn_handle, "uc_mem_regions"); gp_uc_mem_regions = (uc_mem_regions_t)DYNLOAD_GETFUNC(g_dyn_handle, "uc_mem_regions");
gp_uc_context_alloc = (uc_context_alloc_t)DYNLOAD_GETFUNC(g_dyn_handle, "uc_context_alloc"); gp_uc_context_alloc = (uc_context_alloc_t)DYNLOAD_GETFUNC(g_dyn_handle, "uc_context_alloc");
gp_uc_context_save = (uc_context_save_t)DYNLOAD_GETFUNC(g_dyn_handle, "uc_context_save"); gp_uc_context_save = (uc_context_save_t)DYNLOAD_GETFUNC(g_dyn_handle, "uc_context_save");
gp_uc_context_restore = (uc_context_restore_t)DYNLOAD_GETFUNC(g_dyn_handle, "uc_context_restore"); gp_uc_context_restore = (uc_context_restore_t)DYNLOAD_GETFUNC(g_dyn_handle, "uc_context_restore");
gp_uc_free = (uc_free_t)DYNLOAD_GETFUNC(g_dyn_handle, "uc_free"); gp_uc_free = (uc_free_t)DYNLOAD_GETFUNC(g_dyn_handle, "uc_free");
//support old compiled dlls //support old compiled dlls
if(gp_uc_free==0) gp_uc_free = (uc_free_t)DYNLOAD_GETFUNC(g_dyn_handle, "uc_context_free"); if(gp_uc_free==0) gp_uc_free = (uc_free_t)DYNLOAD_GETFUNC(g_dyn_handle, "uc_context_free");
return true; return true;
} }
@ -194,10 +194,10 @@ bool uc_dyn_free(void)
gp_uc_mem_unmap = NULL; gp_uc_mem_unmap = NULL;
gp_uc_mem_protect = NULL; gp_uc_mem_protect = NULL;
gp_uc_mem_regions = NULL; gp_uc_mem_regions = NULL;
gp_uc_context_alloc = NULL; gp_uc_context_alloc = NULL;
gp_uc_context_save = NULL; gp_uc_context_save = NULL;
gp_uc_context_restore = NULL; gp_uc_context_restore = NULL;
gp_uc_free = NULL; gp_uc_free = NULL;
return true; return true;
} }
@ -350,20 +350,20 @@ uc_err uc_mem_regions(uc_engine *uc, uc_mem_region **regions, uint32_t *count)
} }
uc_err uc_context_alloc(uc_engine *uc, uc_context **context){ uc_err uc_context_alloc(uc_engine *uc, uc_context **context){
return gp_uc_context_alloc(uc,context); return gp_uc_context_alloc(uc,context);
} }
uc_err uc_context_save(uc_engine *uc, uc_context *context) uc_err uc_context_save(uc_engine *uc, uc_context *context)
{ {
return gp_uc_context_save(uc,context); return gp_uc_context_save(uc,context);
} }
uc_err uc_context_restore(uc_engine *uc, uc_context *context){ uc_err uc_context_restore(uc_engine *uc, uc_context *context){
return gp_uc_context_restore(uc,context); return gp_uc_context_restore(uc,context);
} }
uc_err uc_free(void *mem){ uc_err uc_free(void *mem){
return gp_uc_free(mem); return gp_uc_free(mem);
} }

240
include/unicorn/arm.h
View file

@ -14,129 +14,129 @@ extern "C" {
//> ARM registers //> ARM registers
typedef enum uc_arm_reg { typedef enum uc_arm_reg {
UC_ARM_REG_INVALID = 0, UC_ARM_REG_INVALID = 0,
UC_ARM_REG_APSR, UC_ARM_REG_APSR,
UC_ARM_REG_APSR_NZCV, UC_ARM_REG_APSR_NZCV,
UC_ARM_REG_CPSR, UC_ARM_REG_CPSR,
UC_ARM_REG_FPEXC, UC_ARM_REG_FPEXC,
UC_ARM_REG_FPINST, UC_ARM_REG_FPINST,
UC_ARM_REG_FPSCR, UC_ARM_REG_FPSCR,
UC_ARM_REG_FPSCR_NZCV, UC_ARM_REG_FPSCR_NZCV,
UC_ARM_REG_FPSID, UC_ARM_REG_FPSID,
UC_ARM_REG_ITSTATE, UC_ARM_REG_ITSTATE,
UC_ARM_REG_LR, UC_ARM_REG_LR,
UC_ARM_REG_PC, UC_ARM_REG_PC,
UC_ARM_REG_SP, UC_ARM_REG_SP,
UC_ARM_REG_SPSR, UC_ARM_REG_SPSR,
UC_ARM_REG_D0, UC_ARM_REG_D0,
UC_ARM_REG_D1, UC_ARM_REG_D1,
UC_ARM_REG_D2, UC_ARM_REG_D2,
UC_ARM_REG_D3, UC_ARM_REG_D3,
UC_ARM_REG_D4, UC_ARM_REG_D4,
UC_ARM_REG_D5, UC_ARM_REG_D5,
UC_ARM_REG_D6, UC_ARM_REG_D6,
UC_ARM_REG_D7, UC_ARM_REG_D7,
UC_ARM_REG_D8, UC_ARM_REG_D8,
UC_ARM_REG_D9, UC_ARM_REG_D9,
UC_ARM_REG_D10, UC_ARM_REG_D10,
UC_ARM_REG_D11, UC_ARM_REG_D11,
UC_ARM_REG_D12, UC_ARM_REG_D12,
UC_ARM_REG_D13, UC_ARM_REG_D13,
UC_ARM_REG_D14, UC_ARM_REG_D14,
UC_ARM_REG_D15, UC_ARM_REG_D15,
UC_ARM_REG_D16, UC_ARM_REG_D16,
UC_ARM_REG_D17, UC_ARM_REG_D17,
UC_ARM_REG_D18, UC_ARM_REG_D18,
UC_ARM_REG_D19, UC_ARM_REG_D19,
UC_ARM_REG_D20, UC_ARM_REG_D20,
UC_ARM_REG_D21, UC_ARM_REG_D21,
UC_ARM_REG_D22, UC_ARM_REG_D22,
UC_ARM_REG_D23, UC_ARM_REG_D23,
UC_ARM_REG_D24, UC_ARM_REG_D24,
UC_ARM_REG_D25, UC_ARM_REG_D25,
UC_ARM_REG_D26, UC_ARM_REG_D26,
UC_ARM_REG_D27, UC_ARM_REG_D27,
UC_ARM_REG_D28, UC_ARM_REG_D28,
UC_ARM_REG_D29, UC_ARM_REG_D29,
UC_ARM_REG_D30, UC_ARM_REG_D30,
UC_ARM_REG_D31, UC_ARM_REG_D31,
UC_ARM_REG_FPINST2, UC_ARM_REG_FPINST2,
UC_ARM_REG_MVFR0, UC_ARM_REG_MVFR0,
UC_ARM_REG_MVFR1, UC_ARM_REG_MVFR1,
UC_ARM_REG_MVFR2, UC_ARM_REG_MVFR2,
UC_ARM_REG_Q0, UC_ARM_REG_Q0,
UC_ARM_REG_Q1, UC_ARM_REG_Q1,
UC_ARM_REG_Q2, UC_ARM_REG_Q2,
UC_ARM_REG_Q3, UC_ARM_REG_Q3,
UC_ARM_REG_Q4, UC_ARM_REG_Q4,
UC_ARM_REG_Q5, UC_ARM_REG_Q5,
UC_ARM_REG_Q6, UC_ARM_REG_Q6,
UC_ARM_REG_Q7, UC_ARM_REG_Q7,
UC_ARM_REG_Q8, UC_ARM_REG_Q8,
UC_ARM_REG_Q9, UC_ARM_REG_Q9,
UC_ARM_REG_Q10, UC_ARM_REG_Q10,
UC_ARM_REG_Q11, UC_ARM_REG_Q11,
UC_ARM_REG_Q12, UC_ARM_REG_Q12,
UC_ARM_REG_Q13, UC_ARM_REG_Q13,
UC_ARM_REG_Q14, UC_ARM_REG_Q14,
UC_ARM_REG_Q15, UC_ARM_REG_Q15,
UC_ARM_REG_R0, UC_ARM_REG_R0,
UC_ARM_REG_R1, UC_ARM_REG_R1,
UC_ARM_REG_R2, UC_ARM_REG_R2,
UC_ARM_REG_R3, UC_ARM_REG_R3,
UC_ARM_REG_R4, UC_ARM_REG_R4,
UC_ARM_REG_R5, UC_ARM_REG_R5,
UC_ARM_REG_R6, UC_ARM_REG_R6,
UC_ARM_REG_R7, UC_ARM_REG_R7,
UC_ARM_REG_R8, UC_ARM_REG_R8,
UC_ARM_REG_R9, UC_ARM_REG_R9,
UC_ARM_REG_R10, UC_ARM_REG_R10,
UC_ARM_REG_R11, UC_ARM_REG_R11,
UC_ARM_REG_R12, UC_ARM_REG_R12,
UC_ARM_REG_S0, UC_ARM_REG_S0,
UC_ARM_REG_S1, UC_ARM_REG_S1,
UC_ARM_REG_S2, UC_ARM_REG_S2,
UC_ARM_REG_S3, UC_ARM_REG_S3,
UC_ARM_REG_S4, UC_ARM_REG_S4,
UC_ARM_REG_S5, UC_ARM_REG_S5,
UC_ARM_REG_S6, UC_ARM_REG_S6,
UC_ARM_REG_S7, UC_ARM_REG_S7,
UC_ARM_REG_S8, UC_ARM_REG_S8,
UC_ARM_REG_S9, UC_ARM_REG_S9,
UC_ARM_REG_S10, UC_ARM_REG_S10,
UC_ARM_REG_S11, UC_ARM_REG_S11,
UC_ARM_REG_S12, UC_ARM_REG_S12,
UC_ARM_REG_S13, UC_ARM_REG_S13,
UC_ARM_REG_S14, UC_ARM_REG_S14,
UC_ARM_REG_S15, UC_ARM_REG_S15,
UC_ARM_REG_S16, UC_ARM_REG_S16,
UC_ARM_REG_S17, UC_ARM_REG_S17,
UC_ARM_REG_S18, UC_ARM_REG_S18,
UC_ARM_REG_S19, UC_ARM_REG_S19,
UC_ARM_REG_S20, UC_ARM_REG_S20,
UC_ARM_REG_S21, UC_ARM_REG_S21,
UC_ARM_REG_S22, UC_ARM_REG_S22,
UC_ARM_REG_S23, UC_ARM_REG_S23,
UC_ARM_REG_S24, UC_ARM_REG_S24,
UC_ARM_REG_S25, UC_ARM_REG_S25,
UC_ARM_REG_S26, UC_ARM_REG_S26,
UC_ARM_REG_S27, UC_ARM_REG_S27,
UC_ARM_REG_S28, UC_ARM_REG_S28,
UC_ARM_REG_S29, UC_ARM_REG_S29,
UC_ARM_REG_S30, UC_ARM_REG_S30,
UC_ARM_REG_S31, UC_ARM_REG_S31,
UC_ARM_REG_ENDING, // <-- mark the end of the list or registers UC_ARM_REG_ENDING, // <-- mark the end of the list or registers
//> alias registers //> alias registers
UC_ARM_REG_R13 = UC_ARM_REG_SP, UC_ARM_REG_R13 = UC_ARM_REG_SP,
UC_ARM_REG_R14 = UC_ARM_REG_LR, UC_ARM_REG_R14 = UC_ARM_REG_LR,
UC_ARM_REG_R15 = UC_ARM_REG_PC, UC_ARM_REG_R15 = UC_ARM_REG_PC,
UC_ARM_REG_SB = UC_ARM_REG_R9, UC_ARM_REG_SB = UC_ARM_REG_R9,
UC_ARM_REG_SL = UC_ARM_REG_R10, UC_ARM_REG_SL = UC_ARM_REG_R10,
UC_ARM_REG_FP = UC_ARM_REG_R11, UC_ARM_REG_FP = UC_ARM_REG_R11,
UC_ARM_REG_IP = UC_ARM_REG_R12, UC_ARM_REG_IP = UC_ARM_REG_R12,
} uc_arm_reg; } uc_arm_reg;
#ifdef __cplusplus #ifdef __cplusplus

536
include/unicorn/arm64.h
View file

@ -14,280 +14,280 @@ extern "C" {
//> ARM64 registers //> ARM64 registers
typedef enum uc_arm64_reg { typedef enum uc_arm64_reg {
UC_ARM64_REG_INVALID = 0, UC_ARM64_REG_INVALID = 0,
UC_ARM64_REG_X29, UC_ARM64_REG_X29,
UC_ARM64_REG_X30, UC_ARM64_REG_X30,
UC_ARM64_REG_NZCV, UC_ARM64_REG_NZCV,
UC_ARM64_REG_SP, UC_ARM64_REG_SP,
UC_ARM64_REG_WSP, UC_ARM64_REG_WSP,
UC_ARM64_REG_WZR, UC_ARM64_REG_WZR,
UC_ARM64_REG_XZR, UC_ARM64_REG_XZR,
UC_ARM64_REG_B0, UC_ARM64_REG_B0,
UC_ARM64_REG_B1, UC_ARM64_REG_B1,
UC_ARM64_REG_B2, UC_ARM64_REG_B2,
UC_ARM64_REG_B3, UC_ARM64_REG_B3,
UC_ARM64_REG_B4, UC_ARM64_REG_B4,
UC_ARM64_REG_B5, UC_ARM64_REG_B5,
UC_ARM64_REG_B6, UC_ARM64_REG_B6,
UC_ARM64_REG_B7, UC_ARM64_REG_B7,
UC_ARM64_REG_B8, UC_ARM64_REG_B8,
UC_ARM64_REG_B9, UC_ARM64_REG_B9,
UC_ARM64_REG_B10, UC_ARM64_REG_B10,
UC_ARM64_REG_B11, UC_ARM64_REG_B11,
UC_ARM64_REG_B12, UC_ARM64_REG_B12,
UC_ARM64_REG_B13, UC_ARM64_REG_B13,
UC_ARM64_REG_B14, UC_ARM64_REG_B14,
UC_ARM64_REG_B15, UC_ARM64_REG_B15,
UC_ARM64_REG_B16, UC_ARM64_REG_B16,
UC_ARM64_REG_B17, UC_ARM64_REG_B17,
UC_ARM64_REG_B18, UC_ARM64_REG_B18,
UC_ARM64_REG_B19, UC_ARM64_REG_B19,
UC_ARM64_REG_B20, UC_ARM64_REG_B20,
UC_ARM64_REG_B21, UC_ARM64_REG_B21,
UC_ARM64_REG_B22, UC_ARM64_REG_B22,
UC_ARM64_REG_B23, UC_ARM64_REG_B23,
UC_ARM64_REG_B24, UC_ARM64_REG_B24,
UC_ARM64_REG_B25, UC_ARM64_REG_B25,
UC_ARM64_REG_B26, UC_ARM64_REG_B26,
UC_ARM64_REG_B27, UC_ARM64_REG_B27,
UC_ARM64_REG_B28, UC_ARM64_REG_B28,
UC_ARM64_REG_B29, UC_ARM64_REG_B29,
UC_ARM64_REG_B30, UC_ARM64_REG_B30,
UC_ARM64_REG_B31, UC_ARM64_REG_B31,
UC_ARM64_REG_D0, UC_ARM64_REG_D0,
UC_ARM64_REG_D1, UC_ARM64_REG_D1,
UC_ARM64_REG_D2, UC_ARM64_REG_D2,
UC_ARM64_REG_D3, UC_ARM64_REG_D3,
UC_ARM64_REG_D4, UC_ARM64_REG_D4,
UC_ARM64_REG_D5, UC_ARM64_REG_D5,
UC_ARM64_REG_D6, UC_ARM64_REG_D6,
UC_ARM64_REG_D7, UC_ARM64_REG_D7,
UC_ARM64_REG_D8, UC_ARM64_REG_D8,
UC_ARM64_REG_D9, UC_ARM64_REG_D9,
UC_ARM64_REG_D10, UC_ARM64_REG_D10,
UC_ARM64_REG_D11, UC_ARM64_REG_D11,
UC_ARM64_REG_D12, UC_ARM64_REG_D12,
UC_ARM64_REG_D13, UC_ARM64_REG_D13,
UC_ARM64_REG_D14, UC_ARM64_REG_D14,
UC_ARM64_REG_D15, UC_ARM64_REG_D15,
UC_ARM64_REG_D16, UC_ARM64_REG_D16,
UC_ARM64_REG_D17, UC_ARM64_REG_D17,
UC_ARM64_REG_D18, UC_ARM64_REG_D18,
UC_ARM64_REG_D19, UC_ARM64_REG_D19,
UC_ARM64_REG_D20, UC_ARM64_REG_D20,
UC_ARM64_REG_D21, UC_ARM64_REG_D21,
UC_ARM64_REG_D22, UC_ARM64_REG_D22,
UC_ARM64_REG_D23, UC_ARM64_REG_D23,
UC_ARM64_REG_D24, UC_ARM64_REG_D24,
UC_ARM64_REG_D25, UC_ARM64_REG_D25,
UC_ARM64_REG_D26, UC_ARM64_REG_D26,
UC_ARM64_REG_D27, UC_ARM64_REG_D27,
UC_ARM64_REG_D28, UC_ARM64_REG_D28,
UC_ARM64_REG_D29, UC_ARM64_REG_D29,
UC_ARM64_REG_D30, UC_ARM64_REG_D30,
UC_ARM64_REG_D31, UC_ARM64_REG_D31,
UC_ARM64_REG_H0, UC_ARM64_REG_H0,
UC_ARM64_REG_H1, UC_ARM64_REG_H1,
UC_ARM64_REG_H2, UC_ARM64_REG_H2,
UC_ARM64_REG_H3, UC_ARM64_REG_H3,
UC_ARM64_REG_H4, UC_ARM64_REG_H4,
UC_ARM64_REG_H5, UC_ARM64_REG_H5,
UC_ARM64_REG_H6, UC_ARM64_REG_H6,
UC_ARM64_REG_H7, UC_ARM64_REG_H7,
UC_ARM64_REG_H8, UC_ARM64_REG_H8,
UC_ARM64_REG_H9, UC_ARM64_REG_H9,
UC_ARM64_REG_H10, UC_ARM64_REG_H10,
UC_ARM64_REG_H11, UC_ARM64_REG_H11,
UC_ARM64_REG_H12, UC_ARM64_REG_H12,
UC_ARM64_REG_H13, UC_ARM64_REG_H13,
UC_ARM64_REG_H14, UC_ARM64_REG_H14,
UC_ARM64_REG_H15, UC_ARM64_REG_H15,
UC_ARM64_REG_H16, UC_ARM64_REG_H16,
UC_ARM64_REG_H17, UC_ARM64_REG_H17,
UC_ARM64_REG_H18, UC_ARM64_REG_H18,
UC_ARM64_REG_H19, UC_ARM64_REG_H19,
UC_ARM64_REG_H20, UC_ARM64_REG_H20,
UC_ARM64_REG_H21, UC_ARM64_REG_H21,
UC_ARM64_REG_H22, UC_ARM64_REG_H22,
UC_ARM64_REG_H23, UC_ARM64_REG_H23,
UC_ARM64_REG_H24, UC_ARM64_REG_H24,
UC_ARM64_REG_H25, UC_ARM64_REG_H25,
UC_ARM64_REG_H26, UC_ARM64_REG_H26,
UC_ARM64_REG_H27, UC_ARM64_REG_H27,
UC_ARM64_REG_H28, UC_ARM64_REG_H28,
UC_ARM64_REG_H29, UC_ARM64_REG_H29,
UC_ARM64_REG_H30, UC_ARM64_REG_H30,
UC_ARM64_REG_H31, UC_ARM64_REG_H31,
UC_ARM64_REG_Q0, UC_ARM64_REG_Q0,
UC_ARM64_REG_Q1, UC_ARM64_REG_Q1,
UC_ARM64_REG_Q2, UC_ARM64_REG_Q2,
UC_ARM64_REG_Q3, UC_ARM64_REG_Q3,
UC_ARM64_REG_Q4, UC_ARM64_REG_Q4,
UC_ARM64_REG_Q5, UC_ARM64_REG_Q5,
UC_ARM64_REG_Q6, UC_ARM64_REG_Q6,
UC_ARM64_REG_Q7, UC_ARM64_REG_Q7,
UC_ARM64_REG_Q8, UC_ARM64_REG_Q8,
UC_ARM64_REG_Q9, UC_ARM64_REG_Q9,
UC_ARM64_REG_Q10, UC_ARM64_REG_Q10,
UC_ARM64_REG_Q11, UC_ARM64_REG_Q11,
UC_ARM64_REG_Q12, UC_ARM64_REG_Q12,
UC_ARM64_REG_Q13, UC_ARM64_REG_Q13,
UC_ARM64_REG_Q14, UC_ARM64_REG_Q14,
UC_ARM64_REG_Q15, UC_ARM64_REG_Q15,
UC_ARM64_REG_Q16, UC_ARM64_REG_Q16,
UC_ARM64_REG_Q17, UC_ARM64_REG_Q17,
UC_ARM64_REG_Q18, UC_ARM64_REG_Q18,
UC_ARM64_REG_Q19, UC_ARM64_REG_Q19,
UC_ARM64_REG_Q20, UC_ARM64_REG_Q20,
UC_ARM64_REG_Q21, UC_ARM64_REG_Q21,
UC_ARM64_REG_Q22, UC_ARM64_REG_Q22,
UC_ARM64_REG_Q23, UC_ARM64_REG_Q23,
UC_ARM64_REG_Q24, UC_ARM64_REG_Q24,
UC_ARM64_REG_Q25, UC_ARM64_REG_Q25,
UC_ARM64_REG_Q26, UC_ARM64_REG_Q26,
UC_ARM64_REG_Q27, UC_ARM64_REG_Q27,
UC_ARM64_REG_Q28, UC_ARM64_REG_Q28,
UC_ARM64_REG_Q29, UC_ARM64_REG_Q29,
UC_ARM64_REG_Q30, UC_ARM64_REG_Q30,
UC_ARM64_REG_Q31, UC_ARM64_REG_Q31,
UC_ARM64_REG_S0, UC_ARM64_REG_S0,
UC_ARM64_REG_S1, UC_ARM64_REG_S1,
UC_ARM64_REG_S2, UC_ARM64_REG_S2,
UC_ARM64_REG_S3, UC_ARM64_REG_S3,
UC_ARM64_REG_S4, UC_ARM64_REG_S4,
UC_ARM64_REG_S5, UC_ARM64_REG_S5,
UC_ARM64_REG_S6, UC_ARM64_REG_S6,
UC_ARM64_REG_S7, UC_ARM64_REG_S7,
UC_ARM64_REG_S8, UC_ARM64_REG_S8,
UC_ARM64_REG_S9, UC_ARM64_REG_S9,
UC_ARM64_REG_S10, UC_ARM64_REG_S10,
UC_ARM64_REG_S11, UC_ARM64_REG_S11,
UC_ARM64_REG_S12, UC_ARM64_REG_S12,
UC_ARM64_REG_S13, UC_ARM64_REG_S13,
UC_ARM64_REG_S14, UC_ARM64_REG_S14,
UC_ARM64_REG_S15, UC_ARM64_REG_S15,
UC_ARM64_REG_S16, UC_ARM64_REG_S16,
UC_ARM64_REG_S17, UC_ARM64_REG_S17,
UC_ARM64_REG_S18, UC_ARM64_REG_S18,
UC_ARM64_REG_S19, UC_ARM64_REG_S19,
UC_ARM64_REG_S20, UC_ARM64_REG_S20,
UC_ARM64_REG_S21, UC_ARM64_REG_S21,
UC_ARM64_REG_S22, UC_ARM64_REG_S22,
UC_ARM64_REG_S23, UC_ARM64_REG_S23,
UC_ARM64_REG_S24, UC_ARM64_REG_S24,
UC_ARM64_REG_S25, UC_ARM64_REG_S25,
UC_ARM64_REG_S26, UC_ARM64_REG_S26,
UC_ARM64_REG_S27, UC_ARM64_REG_S27,
UC_ARM64_REG_S28, UC_ARM64_REG_S28,
UC_ARM64_REG_S29, UC_ARM64_REG_S29,
UC_ARM64_REG_S30, UC_ARM64_REG_S30,
UC_ARM64_REG_S31, UC_ARM64_REG_S31,
UC_ARM64_REG_W0, UC_ARM64_REG_W0,
UC_ARM64_REG_W1, UC_ARM64_REG_W1,
UC_ARM64_REG_W2, UC_ARM64_REG_W2,
UC_ARM64_REG_W3, UC_ARM64_REG_W3,
UC_ARM64_REG_W4, UC_ARM64_REG_W4,
UC_ARM64_REG_W5, UC_ARM64_REG_W5,
UC_ARM64_REG_W6, UC_ARM64_REG_W6,
UC_ARM64_REG_W7, UC_ARM64_REG_W7,
UC_ARM64_REG_W8, UC_ARM64_REG_W8,
UC_ARM64_REG_W9, UC_ARM64_REG_W9,
UC_ARM64_REG_W10, UC_ARM64_REG_W10,
UC_ARM64_REG_W11, UC_ARM64_REG_W11,
UC_ARM64_REG_W12, UC_ARM64_REG_W12,
UC_ARM64_REG_W13, UC_ARM64_REG_W13,
UC_ARM64_REG_W14, UC_ARM64_REG_W14,
UC_ARM64_REG_W15, UC_ARM64_REG_W15,
UC_ARM64_REG_W16, UC_ARM64_REG_W16,
UC_ARM64_REG_W17, UC_ARM64_REG_W17,
UC_ARM64_REG_W18, UC_ARM64_REG_W18,
UC_ARM64_REG_W19, UC_ARM64_REG_W19,
UC_ARM64_REG_W20, UC_ARM64_REG_W20,
UC_ARM64_REG_W21, UC_ARM64_REG_W21,
UC_ARM64_REG_W22, UC_ARM64_REG_W22,
UC_ARM64_REG_W23, UC_ARM64_REG_W23,
UC_ARM64_REG_W24, UC_ARM64_REG_W24,
UC_ARM64_REG_W25, UC_ARM64_REG_W25,
UC_ARM64_REG_W26, UC_ARM64_REG_W26,
UC_ARM64_REG_W27, UC_ARM64_REG_W27,
UC_ARM64_REG_W28, UC_ARM64_REG_W28,
UC_ARM64_REG_W29, UC_ARM64_REG_W29,
UC_ARM64_REG_W30, UC_ARM64_REG_W30,
UC_ARM64_REG_X0, UC_ARM64_REG_X0,
UC_ARM64_REG_X1, UC_ARM64_REG_X1,
UC_ARM64_REG_X2, UC_ARM64_REG_X2,
UC_ARM64_REG_X3, UC_ARM64_REG_X3,
UC_ARM64_REG_X4, UC_ARM64_REG_X4,
UC_ARM64_REG_X5, UC_ARM64_REG_X5,
UC_ARM64_REG_X6, UC_ARM64_REG_X6,
UC_ARM64_REG_X7, UC_ARM64_REG_X7,
UC_ARM64_REG_X8, UC_ARM64_REG_X8,
UC_ARM64_REG_X9, UC_ARM64_REG_X9,
UC_ARM64_REG_X10, UC_ARM64_REG_X10,
UC_ARM64_REG_X11, UC_ARM64_REG_X11,
UC_ARM64_REG_X12, UC_ARM64_REG_X12,
UC_ARM64_REG_X13, UC_ARM64_REG_X13,
UC_ARM64_REG_X14, UC_ARM64_REG_X14,
UC_ARM64_REG_X15, UC_ARM64_REG_X15,
UC_ARM64_REG_X16, UC_ARM64_REG_X16,
UC_ARM64_REG_X17, UC_ARM64_REG_X17,
UC_ARM64_REG_X18, UC_ARM64_REG_X18,
UC_ARM64_REG_X19, UC_ARM64_REG_X19,
UC_ARM64_REG_X20, UC_ARM64_REG_X20,
UC_ARM64_REG_X21, UC_ARM64_REG_X21,
UC_ARM64_REG_X22, UC_ARM64_REG_X22,
UC_ARM64_REG_X23, UC_ARM64_REG_X23,
UC_ARM64_REG_X24, UC_ARM64_REG_X24,
UC_ARM64_REG_X25, UC_ARM64_REG_X25,
UC_ARM64_REG_X26, UC_ARM64_REG_X26,
UC_ARM64_REG_X27, UC_ARM64_REG_X27,
UC_ARM64_REG_X28, UC_ARM64_REG_X28,
UC_ARM64_REG_V0, UC_ARM64_REG_V0,
UC_ARM64_REG_V1, UC_ARM64_REG_V1,
UC_ARM64_REG_V2, UC_ARM64_REG_V2,
UC_ARM64_REG_V3, UC_ARM64_REG_V3,
UC_ARM64_REG_V4, UC_ARM64_REG_V4,
UC_ARM64_REG_V5, UC_ARM64_REG_V5,
UC_ARM64_REG_V6, UC_ARM64_REG_V6,
UC_ARM64_REG_V7, UC_ARM64_REG_V7,
UC_ARM64_REG_V8, UC_ARM64_REG_V8,
UC_ARM64_REG_V9, UC_ARM64_REG_V9,
UC_ARM64_REG_V10, UC_ARM64_REG_V10,
UC_ARM64_REG_V11, UC_ARM64_REG_V11,
UC_ARM64_REG_V12, UC_ARM64_REG_V12,
UC_ARM64_REG_V13, UC_ARM64_REG_V13,
UC_ARM64_REG_V14, UC_ARM64_REG_V14,
UC_ARM64_REG_V15, UC_ARM64_REG_V15,
UC_ARM64_REG_V16, UC_ARM64_REG_V16,
UC_ARM64_REG_V17, UC_ARM64_REG_V17,
UC_ARM64_REG_V18, UC_ARM64_REG_V18,
UC_ARM64_REG_V19, UC_ARM64_REG_V19,
UC_ARM64_REG_V20, UC_ARM64_REG_V20,
UC_ARM64_REG_V21, UC_ARM64_REG_V21,
UC_ARM64_REG_V22, UC_ARM64_REG_V22,
UC_ARM64_REG_V23, UC_ARM64_REG_V23,
UC_ARM64_REG_V24, UC_ARM64_REG_V24,
UC_ARM64_REG_V25, UC_ARM64_REG_V25,
UC_ARM64_REG_V26, UC_ARM64_REG_V26,
UC_ARM64_REG_V27, UC_ARM64_REG_V27,
UC_ARM64_REG_V28, UC_ARM64_REG_V28,
UC_ARM64_REG_V29, UC_ARM64_REG_V29,
UC_ARM64_REG_V30, UC_ARM64_REG_V30,
UC_ARM64_REG_V31, UC_ARM64_REG_V31,
//> pseudo registers //> pseudo registers
UC_ARM64_REG_PC, // program counter register UC_ARM64_REG_PC, // program counter register
UC_ARM64_REG_ENDING, // <-- mark the end of the list of registers UC_ARM64_REG_ENDING, // <-- mark the end of the list of registers
//> alias registers //> alias registers
UC_ARM64_REG_IP1 = UC_ARM64_REG_X16, UC_ARM64_REG_IP1 = UC_ARM64_REG_X16,
UC_ARM64_REG_IP0 = UC_ARM64_REG_X17, UC_ARM64_REG_IP0 = UC_ARM64_REG_X17,
UC_ARM64_REG_FP = UC_ARM64_REG_X29, UC_ARM64_REG_FP = UC_ARM64_REG_X29,
UC_ARM64_REG_LR = UC_ARM64_REG_X30, UC_ARM64_REG_LR = UC_ARM64_REG_X30,
} uc_arm64_reg; } uc_arm64_reg;
#ifdef __cplusplus #ifdef __cplusplus

40
include/unicorn/m68k.h
View file

@ -16,30 +16,30 @@ extern "C" {
//> M68K registers //> M68K registers
typedef enum uc_m68k_reg { typedef enum uc_m68k_reg {
UC_M68K_REG_INVALID = 0, UC_M68K_REG_INVALID = 0,
UC_M68K_REG_A0, UC_M68K_REG_A0,
UC_M68K_REG_A1, UC_M68K_REG_A1,
UC_M68K_REG_A2, UC_M68K_REG_A2,
UC_M68K_REG_A3, UC_M68K_REG_A3,
UC_M68K_REG_A4, UC_M68K_REG_A4,
UC_M68K_REG_A5, UC_M68K_REG_A5,
UC_M68K_REG_A6, UC_M68K_REG_A6,
UC_M68K_REG_A7, UC_M68K_REG_A7,
UC_M68K_REG_D0, UC_M68K_REG_D0,
UC_M68K_REG_D1, UC_M68K_REG_D1,
UC_M68K_REG_D2, UC_M68K_REG_D2,
UC_M68K_REG_D3, UC_M68K_REG_D3,
UC_M68K_REG_D4, UC_M68K_REG_D4,
UC_M68K_REG_D5, UC_M68K_REG_D5,
UC_M68K_REG_D6, UC_M68K_REG_D6,
UC_M68K_REG_D7, UC_M68K_REG_D7,
UC_M68K_REG_SR, UC_M68K_REG_SR,
UC_M68K_REG_PC, UC_M68K_REG_PC,
UC_M68K_REG_ENDING, // <-- mark the end of the list of registers UC_M68K_REG_ENDING, // <-- mark the end of the list of registers
} uc_m68k_reg; } uc_m68k_reg;
#ifdef __cplusplus #ifdef __cplusplus

370
include/unicorn/mips.h
View file

@ -18,205 +18,205 @@ extern "C" {
//> MIPS registers //> MIPS registers
typedef enum UC_MIPS_REG { typedef enum UC_MIPS_REG {
UC_MIPS_REG_INVALID = 0, UC_MIPS_REG_INVALID = 0,
//> General purpose registers //> General purpose registers
UC_MIPS_REG_PC, UC_MIPS_REG_PC,
UC_MIPS_REG_0, UC_MIPS_REG_0,
UC_MIPS_REG_1, UC_MIPS_REG_1,
UC_MIPS_REG_2, UC_MIPS_REG_2,
UC_MIPS_REG_3, UC_MIPS_REG_3,
UC_MIPS_REG_4, UC_MIPS_REG_4,
UC_MIPS_REG_5, UC_MIPS_REG_5,
UC_MIPS_REG_6, UC_MIPS_REG_6,
UC_MIPS_REG_7, UC_MIPS_REG_7,
UC_MIPS_REG_8, UC_MIPS_REG_8,
UC_MIPS_REG_9, UC_MIPS_REG_9,
UC_MIPS_REG_10, UC_MIPS_REG_10,
UC_MIPS_REG_11, UC_MIPS_REG_11,
UC_MIPS_REG_12, UC_MIPS_REG_12,
UC_MIPS_REG_13, UC_MIPS_REG_13,
UC_MIPS_REG_14, UC_MIPS_REG_14,
UC_MIPS_REG_15, UC_MIPS_REG_15,
UC_MIPS_REG_16, UC_MIPS_REG_16,
UC_MIPS_REG_17, UC_MIPS_REG_17,
UC_MIPS_REG_18, UC_MIPS_REG_18,
UC_MIPS_REG_19, UC_MIPS_REG_19,
UC_MIPS_REG_20, UC_MIPS_REG_20,
UC_MIPS_REG_21, UC_MIPS_REG_21,
UC_MIPS_REG_22, UC_MIPS_REG_22,
UC_MIPS_REG_23, UC_MIPS_REG_23,
UC_MIPS_REG_24, UC_MIPS_REG_24,
UC_MIPS_REG_25, UC_MIPS_REG_25,
UC_MIPS_REG_26, UC_MIPS_REG_26,
UC_MIPS_REG_27, UC_MIPS_REG_27,
UC_MIPS_REG_28, UC_MIPS_REG_28,
UC_MIPS_REG_29, UC_MIPS_REG_29,
UC_MIPS_REG_30, UC_MIPS_REG_30,
UC_MIPS_REG_31, UC_MIPS_REG_31,
//> DSP registers //> DSP registers
UC_MIPS_REG_DSPCCOND, UC_MIPS_REG_DSPCCOND,
UC_MIPS_REG_DSPCARRY, UC_MIPS_REG_DSPCARRY,
UC_MIPS_REG_DSPEFI, UC_MIPS_REG_DSPEFI,
UC_MIPS_REG_DSPOUTFLAG, UC_MIPS_REG_DSPOUTFLAG,
UC_MIPS_REG_DSPOUTFLAG16_19, UC_MIPS_REG_DSPOUTFLAG16_19,
UC_MIPS_REG_DSPOUTFLAG20, UC_MIPS_REG_DSPOUTFLAG20,
UC_MIPS_REG_DSPOUTFLAG21, UC_MIPS_REG_DSPOUTFLAG21,
UC_MIPS_REG_DSPOUTFLAG22, UC_MIPS_REG_DSPOUTFLAG22,
UC_MIPS_REG_DSPOUTFLAG23, UC_MIPS_REG_DSPOUTFLAG23,
UC_MIPS_REG_DSPPOS, UC_MIPS_REG_DSPPOS,
UC_MIPS_REG_DSPSCOUNT, UC_MIPS_REG_DSPSCOUNT,
//> ACC registers //> ACC registers
UC_MIPS_REG_AC0, UC_MIPS_REG_AC0,
UC_MIPS_REG_AC1, UC_MIPS_REG_AC1,
UC_MIPS_REG_AC2, UC_MIPS_REG_AC2,
UC_MIPS_REG_AC3, UC_MIPS_REG_AC3,
//> COP registers //> COP registers
UC_MIPS_REG_CC0, UC_MIPS_REG_CC0,
UC_MIPS_REG_CC1, UC_MIPS_REG_CC1,
UC_MIPS_REG_CC2, UC_MIPS_REG_CC2,
UC_MIPS_REG_CC3, UC_MIPS_REG_CC3,
UC_MIPS_REG_CC4, UC_MIPS_REG_CC4,
UC_MIPS_REG_CC5, UC_MIPS_REG_CC5,
UC_MIPS_REG_CC6, UC_MIPS_REG_CC6,
UC_MIPS_REG_CC7, UC_MIPS_REG_CC7,
//> FPU registers //> FPU registers
UC_MIPS_REG_F0, UC_MIPS_REG_F0,
UC_MIPS_REG_F1, UC_MIPS_REG_F1,
UC_MIPS_REG_F2, UC_MIPS_REG_F2,
UC_MIPS_REG_F3, UC_MIPS_REG_F3,
UC_MIPS_REG_F4, UC_MIPS_REG_F4,
UC_MIPS_REG_F5, UC_MIPS_REG_F5,
UC_MIPS_REG_F6, UC_MIPS_REG_F6,
UC_MIPS_REG_F7, UC_MIPS_REG_F7,
UC_MIPS_REG_F8, UC_MIPS_REG_F8,
UC_MIPS_REG_F9, UC_MIPS_REG_F9,
UC_MIPS_REG_F10, UC_MIPS_REG_F10,
UC_MIPS_REG_F11, UC_MIPS_REG_F11,
UC_MIPS_REG_F12, UC_MIPS_REG_F12,
UC_MIPS_REG_F13, UC_MIPS_REG_F13,
UC_MIPS_REG_F14, UC_MIPS_REG_F14,
UC_MIPS_REG_F15, UC_MIPS_REG_F15,
UC_MIPS_REG_F16, UC_MIPS_REG_F16,
UC_MIPS_REG_F17, UC_MIPS_REG_F17,
UC_MIPS_REG_F18, UC_MIPS_REG_F18,
UC_MIPS_REG_F19, UC_MIPS_REG_F19,
UC_MIPS_REG_F20, UC_MIPS_REG_F20,
UC_MIPS_REG_F21, UC_MIPS_REG_F21,
UC_MIPS_REG_F22, UC_MIPS_REG_F22,
UC_MIPS_REG_F23, UC_MIPS_REG_F23,
UC_MIPS_REG_F24, UC_MIPS_REG_F24,
UC_MIPS_REG_F25, UC_MIPS_REG_F25,
UC_MIPS_REG_F26, UC_MIPS_REG_F26,
UC_MIPS_REG_F27, UC_MIPS_REG_F27,
UC_MIPS_REG_F28, UC_MIPS_REG_F28,
UC_MIPS_REG_F29, UC_MIPS_REG_F29,
UC_MIPS_REG_F30, UC_MIPS_REG_F30,
UC_MIPS_REG_F31, UC_MIPS_REG_F31,
UC_MIPS_REG_FCC0, UC_MIPS_REG_FCC0,
UC_MIPS_REG_FCC1, UC_MIPS_REG_FCC1,
UC_MIPS_REG_FCC2, UC_MIPS_REG_FCC2,
UC_MIPS_REG_FCC3, UC_MIPS_REG_FCC3,
UC_MIPS_REG_FCC4, UC_MIPS_REG_FCC4,
UC_MIPS_REG_FCC5, UC_MIPS_REG_FCC5,
UC_MIPS_REG_FCC6, UC_MIPS_REG_FCC6,
UC_MIPS_REG_FCC7, UC_MIPS_REG_FCC7,
//> AFPR128 //> AFPR128
UC_MIPS_REG_W0, UC_MIPS_REG_W0,
UC_MIPS_REG_W1, UC_MIPS_REG_W1,
UC_MIPS_REG_W2, UC_MIPS_REG_W2,
UC_MIPS_REG_W3, UC_MIPS_REG_W3,
UC_MIPS_REG_W4, UC_MIPS_REG_W4,
UC_MIPS_REG_W5, UC_MIPS_REG_W5,
UC_MIPS_REG_W6, UC_MIPS_REG_W6,
UC_MIPS_REG_W7, UC_MIPS_REG_W7,
UC_MIPS_REG_W8, UC_MIPS_REG_W8,
UC_MIPS_REG_W9, UC_MIPS_REG_W9,
UC_MIPS_REG_W10, UC_MIPS_REG_W10,
UC_MIPS_REG_W11, UC_MIPS_REG_W11,
UC_MIPS_REG_W12, UC_MIPS_REG_W12,
UC_MIPS_REG_W13, UC_MIPS_REG_W13,
UC_MIPS_REG_W14, UC_MIPS_REG_W14,
UC_MIPS_REG_W15, UC_MIPS_REG_W15,
UC_MIPS_REG_W16, UC_MIPS_REG_W16,
UC_MIPS_REG_W17, UC_MIPS_REG_W17,
UC_MIPS_REG_W18, UC_MIPS_REG_W18,
UC_MIPS_REG_W19, UC_MIPS_REG_W19,
UC_MIPS_REG_W20, UC_MIPS_REG_W20,
UC_MIPS_REG_W21, UC_MIPS_REG_W21,
UC_MIPS_REG_W22, UC_MIPS_REG_W22,
UC_MIPS_REG_W23, UC_MIPS_REG_W23,
UC_MIPS_REG_W24, UC_MIPS_REG_W24,
UC_MIPS_REG_W25, UC_MIPS_REG_W25,
UC_MIPS_REG_W26, UC_MIPS_REG_W26,
UC_MIPS_REG_W27, UC_MIPS_REG_W27,
UC_MIPS_REG_W28, UC_MIPS_REG_W28,
UC_MIPS_REG_W29, UC_MIPS_REG_W29,
UC_MIPS_REG_W30, UC_MIPS_REG_W30,
UC_MIPS_REG_W31, UC_MIPS_REG_W31,
UC_MIPS_REG_HI, UC_MIPS_REG_HI,
UC_MIPS_REG_LO, UC_MIPS_REG_LO,
UC_MIPS_REG_P0, UC_MIPS_REG_P0,
UC_MIPS_REG_P1, UC_MIPS_REG_P1,
UC_MIPS_REG_P2, UC_MIPS_REG_P2,
UC_MIPS_REG_MPL0, UC_MIPS_REG_MPL0,
UC_MIPS_REG_MPL1, UC_MIPS_REG_MPL1,
UC_MIPS_REG_MPL2, UC_MIPS_REG_MPL2,
UC_MIPS_REG_ENDING, // <-- mark the end of the list or registers UC_MIPS_REG_ENDING, // <-- mark the end of the list or registers
// alias registers // alias registers
UC_MIPS_REG_ZERO = UC_MIPS_REG_0, UC_MIPS_REG_ZERO = UC_MIPS_REG_0,
UC_MIPS_REG_AT = UC_MIPS_REG_1, UC_MIPS_REG_AT = UC_MIPS_REG_1,
UC_MIPS_REG_V0 = UC_MIPS_REG_2, UC_MIPS_REG_V0 = UC_MIPS_REG_2,
UC_MIPS_REG_V1 = UC_MIPS_REG_3, UC_MIPS_REG_V1 = UC_MIPS_REG_3,
UC_MIPS_REG_A0 = UC_MIPS_REG_4, UC_MIPS_REG_A0 = UC_MIPS_REG_4,
UC_MIPS_REG_A1 = UC_MIPS_REG_5, UC_MIPS_REG_A1 = UC_MIPS_REG_5,
UC_MIPS_REG_A2 = UC_MIPS_REG_6, UC_MIPS_REG_A2 = UC_MIPS_REG_6,
UC_MIPS_REG_A3 = UC_MIPS_REG_7, UC_MIPS_REG_A3 = UC_MIPS_REG_7,
UC_MIPS_REG_T0 = UC_MIPS_REG_8, UC_MIPS_REG_T0 = UC_MIPS_REG_8,
UC_MIPS_REG_T1 = UC_MIPS_REG_9, UC_MIPS_REG_T1 = UC_MIPS_REG_9,
UC_MIPS_REG_T2 = UC_MIPS_REG_10, UC_MIPS_REG_T2 = UC_MIPS_REG_10,
UC_MIPS_REG_T3 = UC_MIPS_REG_11, UC_MIPS_REG_T3 = UC_MIPS_REG_11,
UC_MIPS_REG_T4 = UC_MIPS_REG_12, UC_MIPS_REG_T4 = UC_MIPS_REG_12,
UC_MIPS_REG_T5 = UC_MIPS_REG_13, UC_MIPS_REG_T5 = UC_MIPS_REG_13,
UC_MIPS_REG_T6 = UC_MIPS_REG_14, UC_MIPS_REG_T6 = UC_MIPS_REG_14,
UC_MIPS_REG_T7 = UC_MIPS_REG_15, UC_MIPS_REG_T7 = UC_MIPS_REG_15,
UC_MIPS_REG_S0 = UC_MIPS_REG_16, UC_MIPS_REG_S0 = UC_MIPS_REG_16,
UC_MIPS_REG_S1 = UC_MIPS_REG_17, UC_MIPS_REG_S1 = UC_MIPS_REG_17,
UC_MIPS_REG_S2 = UC_MIPS_REG_18, UC_MIPS_REG_S2 = UC_MIPS_REG_18,
UC_MIPS_REG_S3 = UC_MIPS_REG_19, UC_MIPS_REG_S3 = UC_MIPS_REG_19,
UC_MIPS_REG_S4 = UC_MIPS_REG_20, UC_MIPS_REG_S4 = UC_MIPS_REG_20,
UC_MIPS_REG_S5 = UC_MIPS_REG_21, UC_MIPS_REG_S5 = UC_MIPS_REG_21,
UC_MIPS_REG_S6 = UC_MIPS_REG_22, UC_MIPS_REG_S6 = UC_MIPS_REG_22,
UC_MIPS_REG_S7 = UC_MIPS_REG_23, UC_MIPS_REG_S7 = UC_MIPS_REG_23,
UC_MIPS_REG_T8 = UC_MIPS_REG_24, UC_MIPS_REG_T8 = UC_MIPS_REG_24,
UC_MIPS_REG_T9 = UC_MIPS_REG_25, UC_MIPS_REG_T9 = UC_MIPS_REG_25,
UC_MIPS_REG_K0 = UC_MIPS_REG_26, UC_MIPS_REG_K0 = UC_MIPS_REG_26,
UC_MIPS_REG_K1 = UC_MIPS_REG_27, UC_MIPS_REG_K1 = UC_MIPS_REG_27,
UC_MIPS_REG_GP = UC_MIPS_REG_28, UC_MIPS_REG_GP = UC_MIPS_REG_28,
UC_MIPS_REG_SP = UC_MIPS_REG_29, UC_MIPS_REG_SP = UC_MIPS_REG_29,
UC_MIPS_REG_FP = UC_MIPS_REG_30, UC_MIPS_REG_S8 = UC_MIPS_REG_30, UC_MIPS_REG_FP = UC_MIPS_REG_30, UC_MIPS_REG_S8 = UC_MIPS_REG_30,
UC_MIPS_REG_RA = UC_MIPS_REG_31, UC_MIPS_REG_RA = UC_MIPS_REG_31,
UC_MIPS_REG_HI0 = UC_MIPS_REG_AC0, UC_MIPS_REG_HI0 = UC_MIPS_REG_AC0,
UC_MIPS_REG_HI1 = UC_MIPS_REG_AC1, UC_MIPS_REG_HI1 = UC_MIPS_REG_AC1,
UC_MIPS_REG_HI2 = UC_MIPS_REG_AC2, UC_MIPS_REG_HI2 = UC_MIPS_REG_AC2,
UC_MIPS_REG_HI3 = UC_MIPS_REG_AC3, UC_MIPS_REG_HI3 = UC_MIPS_REG_AC3,
UC_MIPS_REG_LO0 = UC_MIPS_REG_HI0, UC_MIPS_REG_LO0 = UC_MIPS_REG_HI0,
UC_MIPS_REG_LO1 = UC_MIPS_REG_HI1, UC_MIPS_REG_LO1 = UC_MIPS_REG_HI1,
UC_MIPS_REG_LO2 = UC_MIPS_REG_HI2, UC_MIPS_REG_LO2 = UC_MIPS_REG_HI2,
UC_MIPS_REG_LO3 = UC_MIPS_REG_HI3, UC_MIPS_REG_LO3 = UC_MIPS_REG_HI3,
} UC_MIPS_REG; } UC_MIPS_REG;
#ifdef __cplusplus #ifdef __cplusplus

34
include/unicorn/platform.h
View file

@ -1,5 +1,5 @@
/* /*
This file is primarily to support header files that are missing in MSVC and other non-standard compilers. This file is primarily to support header files that are missing in MSVC and other non-standard compilers.
*/ */
#ifndef UNICORN_PLATFORM_H #ifndef UNICORN_PLATFORM_H
@ -176,11 +176,11 @@ typedef _W64 unsigned int uintptr_t;
static int gettimeofday(struct timeval* t, void* timezone) static int gettimeofday(struct timeval* t, void* timezone)
{ {
struct _timeb timebuffer; struct _timeb timebuffer;
_ftime( &timebuffer ); _ftime( &timebuffer );
t->tv_sec = (long)timebuffer.time; t->tv_sec = (long)timebuffer.time;
t->tv_usec = 1000*timebuffer.millitm; t->tv_usec = 1000*timebuffer.millitm;
return 0; return 0;
} }
#else #else
@ -195,22 +195,22 @@ static int gettimeofday(struct timeval* t, void* timezone)
// TODO: add unistd stuff here ... // TODO: add unistd stuff here ...
static int usleep(uint32_t t) { static int usleep(uint32_t t) {
int ret, err_code; int ret, err_code;
long value = t; // time in microseconds long value = t; // time in microseconds
struct timeval tv; struct timeval tv;
FD_SET dummy_set; FD_SET dummy_set;
FD_ZERO(&dummy_set); FD_ZERO(&dummy_set);
tv.tv_sec = value / 1000000; tv.tv_sec = value / 1000000;
tv.tv_usec = value % 1000000; tv.tv_usec = value % 1000000;
ret = select(0, &dummy_set, NULL, NULL, &tv); ret = select(0, &dummy_set, NULL, NULL, &tv);
err_code = WSAGetLastError(); err_code = WSAGetLastError();
return ret==0 ? 0 : -1; return ret==0 ? 0 : -1;
} }
/* /*
#include <chrono> #include <chrono>
#include <thread> #include <thread>
static void usleep(const int64_t &t) { static void usleep(const int64_t &t) {
std::this_thread::sleep_for(std::chrono::microseconds(t)); std::this_thread::sleep_for(std::chrono::microseconds(t));
} }
*/ */

190
include/unicorn/sparc.h
View file

@ -20,106 +20,106 @@ extern "C" {
//> SPARC registers //> SPARC registers
typedef enum uc_sparc_reg { typedef enum uc_sparc_reg {
UC_SPARC_REG_INVALID = 0, UC_SPARC_REG_INVALID = 0,
UC_SPARC_REG_F0, UC_SPARC_REG_F0,
UC_SPARC_REG_F1, UC_SPARC_REG_F1,
UC_SPARC_REG_F2, UC_SPARC_REG_F2,
UC_SPARC_REG_F3, UC_SPARC_REG_F3,
UC_SPARC_REG_F4, UC_SPARC_REG_F4,
UC_SPARC_REG_F5, UC_SPARC_REG_F5,
UC_SPARC_REG_F6, UC_SPARC_REG_F6,
UC_SPARC_REG_F7, UC_SPARC_REG_F7,
UC_SPARC_REG_F8, UC_SPARC_REG_F8,
UC_SPARC_REG_F9, UC_SPARC_REG_F9,
UC_SPARC_REG_F10, UC_SPARC_REG_F10,
UC_SPARC_REG_F11, UC_SPARC_REG_F11,
UC_SPARC_REG_F12, UC_SPARC_REG_F12,
UC_SPARC_REG_F13, UC_SPARC_REG_F13,
UC_SPARC_REG_F14, UC_SPARC_REG_F14,
UC_SPARC_REG_F15, UC_SPARC_REG_F15,
UC_SPARC_REG_F16, UC_SPARC_REG_F16,
UC_SPARC_REG_F17, UC_SPARC_REG_F17,
UC_SPARC_REG_F18, UC_SPARC_REG_F18,
UC_SPARC_REG_F19, UC_SPARC_REG_F19,
UC_SPARC_REG_F20, UC_SPARC_REG_F20,
UC_SPARC_REG_F21, UC_SPARC_REG_F21,
UC_SPARC_REG_F22, UC_SPARC_REG_F22,
UC_SPARC_REG_F23, UC_SPARC_REG_F23,
UC_SPARC_REG_F24, UC_SPARC_REG_F24,
UC_SPARC_REG_F25, UC_SPARC_REG_F25,
UC_SPARC_REG_F26, UC_SPARC_REG_F26,
UC_SPARC_REG_F27, UC_SPARC_REG_F27,
UC_SPARC_REG_F28, UC_SPARC_REG_F28,
UC_SPARC_REG_F29, UC_SPARC_REG_F29,
UC_SPARC_REG_F30, UC_SPARC_REG_F30,
UC_SPARC_REG_F31, UC_SPARC_REG_F31,
UC_SPARC_REG_F32, UC_SPARC_REG_F32,
UC_SPARC_REG_F34, UC_SPARC_REG_F34,
UC_SPARC_REG_F36, UC_SPARC_REG_F36,
UC_SPARC_REG_F38, UC_SPARC_REG_F38,
UC_SPARC_REG_F40, UC_SPARC_REG_F40,
UC_SPARC_REG_F42, UC_SPARC_REG_F42,
UC_SPARC_REG_F44, UC_SPARC_REG_F44,
UC_SPARC_REG_F46, UC_SPARC_REG_F46,
UC_SPARC_REG_F48, UC_SPARC_REG_F48,
UC_SPARC_REG_F50, UC_SPARC_REG_F50,
UC_SPARC_REG_F52, UC_SPARC_REG_F52,
UC_SPARC_REG_F54, UC_SPARC_REG_F54,
UC_SPARC_REG_F56, UC_SPARC_REG_F56,
UC_SPARC_REG_F58, UC_SPARC_REG_F58,
UC_SPARC_REG_F60, UC_SPARC_REG_F60,
UC_SPARC_REG_F62, UC_SPARC_REG_F62,
UC_SPARC_REG_FCC0, // Floating condition codes UC_SPARC_REG_FCC0, // Floating condition codes
UC_SPARC_REG_FCC1, UC_SPARC_REG_FCC1,
UC_SPARC_REG_FCC2, UC_SPARC_REG_FCC2,
UC_SPARC_REG_FCC3, UC_SPARC_REG_FCC3,
UC_SPARC_REG_G0, UC_SPARC_REG_G0,
UC_SPARC_REG_G1, UC_SPARC_REG_G1,
UC_SPARC_REG_G2, UC_SPARC_REG_G2,
UC_SPARC_REG_G3, UC_SPARC_REG_G3,
UC_SPARC_REG_G4, UC_SPARC_REG_G4,
UC_SPARC_REG_G5, UC_SPARC_REG_G5,
UC_SPARC_REG_G6, UC_SPARC_REG_G6,
UC_SPARC_REG_G7, UC_SPARC_REG_G7,
UC_SPARC_REG_I0, UC_SPARC_REG_I0,
UC_SPARC_REG_I1, UC_SPARC_REG_I1,
UC_SPARC_REG_I2, UC_SPARC_REG_I2,
UC_SPARC_REG_I3, UC_SPARC_REG_I3,
UC_SPARC_REG_I4, UC_SPARC_REG_I4,
UC_SPARC_REG_I5, UC_SPARC_REG_I5,
UC_SPARC_REG_FP, UC_SPARC_REG_FP,
UC_SPARC_REG_I7, UC_SPARC_REG_I7,
UC_SPARC_REG_ICC, // Integer condition codes UC_SPARC_REG_ICC, // Integer condition codes
UC_SPARC_REG_L0, UC_SPARC_REG_L0,
UC_SPARC_REG_L1, UC_SPARC_REG_L1,
UC_SPARC_REG_L2, UC_SPARC_REG_L2,
UC_SPARC_REG_L3, UC_SPARC_REG_L3,
UC_SPARC_REG_L4, UC_SPARC_REG_L4,
UC_SPARC_REG_L5, UC_SPARC_REG_L5,
UC_SPARC_REG_L6, UC_SPARC_REG_L6,
UC_SPARC_REG_L7, UC_SPARC_REG_L7,
UC_SPARC_REG_O0, UC_SPARC_REG_O0,
UC_SPARC_REG_O1, UC_SPARC_REG_O1,
UC_SPARC_REG_O2, UC_SPARC_REG_O2,
UC_SPARC_REG_O3, UC_SPARC_REG_O3,
UC_SPARC_REG_O4, UC_SPARC_REG_O4,
UC_SPARC_REG_O5, UC_SPARC_REG_O5,
UC_SPARC_REG_SP, UC_SPARC_REG_SP,
UC_SPARC_REG_O7, UC_SPARC_REG_O7,
UC_SPARC_REG_Y, UC_SPARC_REG_Y,
// special register // special register
UC_SPARC_REG_XCC, UC_SPARC_REG_XCC,
// pseudo register // pseudo register
UC_SPARC_REG_PC, // program counter register UC_SPARC_REG_PC, // program counter register
UC_SPARC_REG_ENDING, // <-- mark the end of the list of registers UC_SPARC_REG_ENDING, // <-- mark the end of the list of registers
// extras // extras
UC_SPARC_REG_O6 = UC_SPARC_REG_SP, UC_SPARC_REG_O6 = UC_SPARC_REG_SP,
UC_SPARC_REG_I6 = UC_SPARC_REG_FP, UC_SPARC_REG_I6 = UC_SPARC_REG_FP,
} uc_sparc_reg; } uc_sparc_reg;
#ifdef __cplusplus #ifdef __cplusplus

2784
include/unicorn/x86.h
View file

File diff suppressed because it is too large Load diff

14
qemu/accel.c
View file

@ -59,13 +59,13 @@ static const TypeInfo accel_type = {
static const TypeInfo tcg_accel_type = { static const TypeInfo tcg_accel_type = {
TYPE_TCG_ACCEL, TYPE_TCG_ACCEL,
TYPE_ACCEL, TYPE_ACCEL,
0, 0,
0, 0,
NULL, NULL,
NULL, NULL,
NULL, NULL,
NULL, NULL,
NULL, NULL,
tcg_accel_class_init, tcg_accel_class_init,
}; };

30
qemu/exec.c
View file

@ -636,7 +636,7 @@ void cpu_single_step(CPUState *cpu, int enabled)
{ {
#if defined(TARGET_HAS_ICE) #if defined(TARGET_HAS_ICE)
if (cpu->singlestep_enabled != enabled) { if (cpu->singlestep_enabled != enabled) {
CPUArchState *env; CPUArchState *env;
cpu->singlestep_enabled = enabled; cpu->singlestep_enabled = enabled;
/* must flush all the translated code to avoid inconsistencies */ /* must flush all the translated code to avoid inconsistencies */
/* XXX: only flush what is necessary */ /* XXX: only flush what is necessary */
@ -1316,8 +1316,8 @@ static const MemoryRegionOps subpage_ops = {
subpage_write, subpage_write,
DEVICE_NATIVE_ENDIAN, DEVICE_NATIVE_ENDIAN,
{ {
0, 0, false, subpage_accepts, 0, 0, false, subpage_accepts,
}, },
}; };
static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end,
@ -1375,11 +1375,11 @@ static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
static const MemoryRegionOps notdirty_mem_ops = { static const MemoryRegionOps notdirty_mem_ops = {
NULL, NULL,
notdirty_mem_write, notdirty_mem_write,
DEVICE_NATIVE_ENDIAN, DEVICE_NATIVE_ENDIAN,
{ {
0, 0, false, notdirty_mem_accepts, 0, 0, false, notdirty_mem_accepts,
}, },
}; };
static void io_mem_init(struct uc_struct* uc) static void io_mem_init(struct uc_struct* uc)
@ -1418,12 +1418,12 @@ static uint16_t dummy_section(PhysPageMap *map, AddressSpace *as,
{ {
MemoryRegionSection section = MemoryRegionSection_make( MemoryRegionSection section = MemoryRegionSection_make(
mr, as, 0, mr, as, 0,
int128_2_64(), int128_2_64(),
false, false,
0 0
); );
assert(as); assert(as);
return phys_section_add(map, &section); return phys_section_add(map, &section);
} }
@ -1444,7 +1444,7 @@ static void mem_begin(MemoryListener *listener)
AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener); AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener);
AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1); AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1);
uint16_t n; uint16_t n;
PhysPageEntry ppe = { 1, PHYS_MAP_NODE_NIL }; PhysPageEntry ppe = { 1, PHYS_MAP_NODE_NIL };
struct uc_struct *uc = as->uc; struct uc_struct *uc = as->uc;
n = dummy_section(&d->map, as, &uc->io_mem_unassigned); n = dummy_section(&d->map, as, &uc->io_mem_unassigned);
@ -1493,12 +1493,12 @@ void address_space_init_dispatch(AddressSpace *as)
mem_begin, mem_begin,
mem_commit, mem_commit,
mem_add, mem_add,
NULL, NULL,
mem_add, mem_add,
NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL, NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,
0, 0,
}; };
as->dispatch = NULL; as->dispatch = NULL;
as->dispatch_listener = ml; as->dispatch_listener = ml;
memory_listener_register(as->uc, &as->dispatch_listener, as); memory_listener_register(as->uc, &as->dispatch_listener, as);
} }

6
qemu/fpu/softfloat.c
View file

@ -1415,7 +1415,7 @@ float128 int64_to_float128(int64_t a STATUS_PARAM)
float128 uint64_to_float128(uint64_t a STATUS_PARAM) float128 uint64_to_float128(uint64_t a STATUS_PARAM)
{ {
if (a == 0) { if (a == 0) {
float128 zero = {0}; float128 zero = {0};
return zero; return zero;
} }
return normalizeRoundAndPackFloat128(0, 0x406E, a, 0 STATUS_VAR); return normalizeRoundAndPackFloat128(0, 0x406E, a, 0 STATUS_VAR);
@ -1641,7 +1641,7 @@ uint64 float32_to_uint64(float32 a STATUS_PARAM)
uint64 float32_to_uint64_round_to_zero(float32 a STATUS_PARAM) uint64 float32_to_uint64_round_to_zero(float32 a STATUS_PARAM)
{ {
int64_t v; int64_t v;
signed char current_rounding_mode = STATUS(float_rounding_mode); signed char current_rounding_mode = STATUS(float_rounding_mode);
set_float_rounding_mode(float_round_to_zero STATUS_VAR); set_float_rounding_mode(float_round_to_zero STATUS_VAR);
v = float32_to_uint64(a STATUS_VAR); v = float32_to_uint64(a STATUS_VAR);
set_float_rounding_mode(current_rounding_mode STATUS_VAR); set_float_rounding_mode(current_rounding_mode STATUS_VAR);
@ -7159,7 +7159,7 @@ uint64_t float64_to_uint64(float64 a STATUS_PARAM)
uint64_t float64_to_uint64_round_to_zero (float64 a STATUS_PARAM) uint64_t float64_to_uint64_round_to_zero (float64 a STATUS_PARAM)
{ {
int64_t v; int64_t v;
signed char current_rounding_mode = STATUS(float_rounding_mode); signed char current_rounding_mode = STATUS(float_rounding_mode);
set_float_rounding_mode(float_round_to_zero STATUS_VAR); set_float_rounding_mode(float_round_to_zero STATUS_VAR);
v = float64_to_uint64(a STATUS_VAR); v = float64_to_uint64(a STATUS_VAR);
set_float_rounding_mode(current_rounding_mode STATUS_VAR); set_float_rounding_mode(current_rounding_mode STATUS_VAR);

38
qemu/glib_compat.c
View file

@ -190,9 +190,9 @@ GList *g_list_remove_link(GList *list, GList *llink)
// code copied from glib/glist.c, version 2.28.0 // code copied from glib/glist.c, version 2.28.0
static GList *g_list_sort_merge(GList *l1, static GList *g_list_sort_merge(GList *l1,
GList *l2, GList *l2,
GFunc compare_func, GFunc compare_func,
gpointer user_data) gpointer user_data)
{ {
GList list, *l, *lprev; GList list, *l, *lprev;
gint cmp; gint cmp;
@ -206,13 +206,13 @@ static GList *g_list_sort_merge(GList *l1,
if (cmp <= 0) if (cmp <= 0)
{ {
l->next = l1; l->next = l1;
l1 = l1->next; l1 = l1->next;
} }
else else
{ {
l->next = l2; l->next = l2;
l2 = l2->next; l2 = l2->next;
} }
l = l->next; l = l->next;
l->prev = lprev; l->prev = lprev;
@ -225,8 +225,8 @@ static GList *g_list_sort_merge(GList *l1,
} }
static GList *g_list_sort_real(GList *list, static GList *g_list_sort_real(GList *list,
GFunc compare_func, GFunc compare_func,
gpointer user_data) gpointer user_data)
{ {
GList *l1, *l2; GList *l1, *l2;
@ -241,16 +241,16 @@ static GList *g_list_sort_real(GList *list,
while ((l2 = l2->next) != NULL) while ((l2 = l2->next) != NULL)
{ {
if ((l2 = l2->next) == NULL) if ((l2 = l2->next) == NULL)
break; break;
l1 = l1->next; l1 = l1->next;
} }
l2 = l1->next; l2 = l1->next;
l1->next = NULL; l1->next = NULL;
return g_list_sort_merge (g_list_sort_real (list, compare_func, user_data), return g_list_sort_merge (g_list_sort_real (list, compare_func, user_data),
g_list_sort_real (l2, compare_func, user_data), g_list_sort_real (l2, compare_func, user_data),
compare_func, compare_func,
user_data); user_data);
} }
/** /**
@ -1218,7 +1218,7 @@ void g_free(gpointer ptr)
gpointer g_malloc(size_t size) gpointer g_malloc(size_t size)
{ {
void *res; void *res;
if (size == 0) return NULL; if (size == 0) return NULL;
res = malloc(size); res = malloc(size);
if (res == NULL) exit(1); if (res == NULL) exit(1);
return res; return res;
@ -1254,9 +1254,9 @@ gpointer g_realloc(gpointer ptr, size_t size)
char *g_strdup(const char *str) char *g_strdup(const char *str)
{ {
#ifdef _MSC_VER #ifdef _MSC_VER
return str ? _strdup(str) : NULL; return str ? _strdup(str) : NULL;
#else #else
return str ? strdup(str) : NULL; return str ? strdup(str) : NULL;
#endif #endif
} }
@ -1276,10 +1276,10 @@ char *g_strdup_vprintf(const char *format, va_list ap)
#ifdef _MSC_VER #ifdef _MSC_VER
int len = _vscprintf(format, ap); int len = _vscprintf(format, ap);
if( len < 0 ) if( len < 0 )
return NULL; return NULL;
str_res = (char *)malloc(len+1); str_res = (char *)malloc(len+1);
if(str_res==NULL) if(str_res==NULL)
return NULL; return NULL;
vsnprintf(str_res, len+1, format, ap); vsnprintf(str_res, len+1, format, ap);
#else #else
vasprintf(&str_res, format, ap); vasprintf(&str_res, format, ap);

16
qemu/hw/core/machine.c
View file

@ -26,19 +26,19 @@ static const TypeInfo machine_info = {
sizeof(MachineClass), sizeof(MachineClass),
sizeof(MachineState), sizeof(MachineState),
NULL, NULL,
machine_initfn, machine_initfn,
NULL, NULL,
machine_finalize, machine_finalize,
NULL, NULL,
NULL, NULL,
NULL, NULL,
NULL, NULL,
true, true,
}; };
void machine_register_types(struct uc_struct *uc) void machine_register_types(struct uc_struct *uc)

32
qemu/hw/core/qdev.c
View file

@ -284,20 +284,20 @@ static const TypeInfo device_type_info = {
TYPE_OBJECT, TYPE_OBJECT,
sizeof(DeviceClass), sizeof(DeviceClass),
sizeof(DeviceState), sizeof(DeviceState),
NULL, NULL,
device_initfn, device_initfn,
device_post_init, device_post_init,
device_finalize, device_finalize,
NULL, NULL,
device_class_init, device_class_init,
device_class_base_init, device_class_base_init,
NULL, NULL,
true, true,
}; };
static void qbus_initfn(struct uc_struct *uc, Object *obj, void *opaque) static void qbus_initfn(struct uc_struct *uc, Object *obj, void *opaque)
@ -321,20 +321,20 @@ static const TypeInfo bus_info = {
TYPE_OBJECT, TYPE_OBJECT,
sizeof(BusClass), sizeof(BusClass),
sizeof(BusState), sizeof(BusState),
NULL, NULL,
qbus_initfn, qbus_initfn,
NULL, NULL,
qbus_finalize, qbus_finalize,
NULL, NULL,
bus_class_init, bus_class_init,
NULL, NULL,
NULL, NULL,
true, true,
}; };
void qdev_register_types(struct uc_struct *uc) void qdev_register_types(struct uc_struct *uc)

30
qemu/hw/i386/pc.c
View file

@ -154,25 +154,25 @@ static const TypeInfo pc_machine_info = {
sizeof(PCMachineClass), sizeof(PCMachineClass),
sizeof(PCMachineState), sizeof(PCMachineState),
NULL, NULL,
pc_machine_initfn, pc_machine_initfn,
NULL, NULL,
NULL, NULL,
NULL, NULL,
pc_machine_class_init,
NULL,
NULL,
true,
NULL, pc_machine_class_init,
NULL, NULL,
NULL,
// should this be added somehow?
//.interfaces = (InterfaceInfo[]) { { } }, true,
NULL,
NULL,
// should this be added somehow?
//.interfaces = (InterfaceInfo[]) { { } },
}; };
void pc_machine_register_types(struct uc_struct *uc) void pc_machine_register_types(struct uc_struct *uc)

6
qemu/hw/i386/pc_piix.c
View file

@ -47,12 +47,12 @@ static int pc_init_pci(struct uc_struct *uc, MachineState *machine)
} }
static QEMUMachine pc_i440fx_machine_v2_2 = { static QEMUMachine pc_i440fx_machine_v2_2 = {
"pc_piix", "pc_piix",
"pc-i440fx-2.2", "pc-i440fx-2.2",
pc_init_pci, pc_init_pci,
NULL, NULL,
255, 255,
1, 1,
UC_ARCH_X86, // X86 UC_ARCH_X86, // X86
}; };

18
qemu/hw/intc/apic.c
View file

@ -203,28 +203,28 @@ static void apic_class_init(struct uc_struct *uc, ObjectClass *klass, void *data
k->vapic_base_update = apic_vapic_base_update; k->vapic_base_update = apic_vapic_base_update;
k->pre_save = apic_pre_save; k->pre_save = apic_pre_save;
k->post_load = apic_post_load; k->post_load = apic_post_load;
//printf("... init apic class\n"); //printf("... init apic class\n");
} }
static const TypeInfo apic_info = { static const TypeInfo apic_info = {
"apic", "apic",
TYPE_APIC_COMMON, TYPE_APIC_COMMON,
0, 0,
sizeof(APICCommonState), sizeof(APICCommonState),
NULL, NULL,
NULL, NULL,
NULL, NULL,
NULL, NULL,
NULL, NULL,
apic_class_init, apic_class_init,
}; };
void apic_register_types(struct uc_struct *uc) void apic_register_types(struct uc_struct *uc)
{ {
//printf("... register apic types\n"); //printf("... register apic types\n");
type_register_static(uc, &apic_info); type_register_static(uc, &apic_info);
} }

30
qemu/hw/intc/apic_common.c
View file

@ -164,8 +164,8 @@ void apic_init_reset(struct uc_struct *uc, DeviceState *dev)
void apic_designate_bsp(struct uc_struct *uc, DeviceState *dev) void apic_designate_bsp(struct uc_struct *uc, DeviceState *dev)
{ {
APICCommonState *s; APICCommonState *s;
if (dev == NULL) { if (dev == NULL) {
return; return;
} }
@ -243,7 +243,7 @@ static void apic_common_class_init(struct uc_struct *uc, ObjectClass *klass, voi
* x86_cpu_apic_create() * x86_cpu_apic_create()
*/ */
dc->cannot_instantiate_with_device_add_yet = true; dc->cannot_instantiate_with_device_add_yet = true;
//printf("... init apic common class\n"); //printf("... init apic common class\n");
} }
static const TypeInfo apic_common_type = { static const TypeInfo apic_common_type = {
@ -251,24 +251,24 @@ static const TypeInfo apic_common_type = {
TYPE_DEVICE, TYPE_DEVICE,
sizeof(APICCommonClass), sizeof(APICCommonClass),
sizeof(APICCommonState), sizeof(APICCommonState),
NULL, NULL,
NULL, NULL,
NULL, NULL,
NULL, NULL,
NULL,
apic_common_class_init,
NULL,
NULL,
true, NULL,
apic_common_class_init,
NULL,
NULL,
true,
}; };
void apic_common_register_types(struct uc_struct *uc) void apic_common_register_types(struct uc_struct *uc)
{ {
//printf("... register apic common\n"); //printf("... register apic common\n");
type_register_static(uc, &apic_common_type); type_register_static(uc, &apic_common_type);
} }

2
qemu/hw/mips/cputimer.c
View file

@ -50,7 +50,7 @@ static void cpu_mips_timer_update(CPUMIPSState *env)
now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
wait = env->CP0_Compare - env->CP0_Count - wait = env->CP0_Compare - env->CP0_Count -
(uint32_t)muldiv64(now, TIMER_FREQ, get_ticks_per_sec()); (uint32_t)muldiv64(now, TIMER_FREQ, get_ticks_per_sec());
next = now + muldiv64(wait, get_ticks_per_sec(), TIMER_FREQ); next = now + muldiv64(wait, get_ticks_per_sec(), TIMER_FREQ);
timer_mod(env->timer, next); timer_mod(env->timer, next);
#endif #endif

2
qemu/include/elf.h
View file

@ -444,7 +444,7 @@
#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ #define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */
#define R_X86_64_RELATIVE 8 /* Adjust by program base */ #define R_X86_64_RELATIVE 8 /* Adjust by program base */
#define R_X86_64_GOTPCREL 9 /* 32 bit signed pc relative #define R_X86_64_GOTPCREL 9 /* 32 bit signed pc relative
offset to GOT */ offset to GOT */
#define R_X86_64_32 10 /* Direct 32 bit zero extended */ #define R_X86_64_32 10 /* Direct 32 bit zero extended */
#define R_X86_64_32S 11 /* Direct 32 bit sign extended */ #define R_X86_64_32S 11 /* Direct 32 bit sign extended */
#define R_X86_64_16 12 /* Direct 16 bit zero extended */ #define R_X86_64_16 12 /* Direct 16 bit zero extended */

4
qemu/include/exec/cpu-defs.h
View file

@ -95,9 +95,9 @@ typedef struct CPUTLBEntry {
uintptr_t addend; uintptr_t addend;
/* padding to get a power of two size */ /* padding to get a power of two size */
#if defined(_MSC_VER) && defined(_WIN64) #if defined(_MSC_VER) && defined(_WIN64)
// dummy would be size 0 which isnt supported by msvc, so we remove it // dummy would be size 0 which isnt supported by msvc, so we remove it
#else #else
uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) - uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) -
(sizeof(target_ulong) * 3 + (sizeof(target_ulong) * 3 +
(((-(int)sizeof(target_ulong)) * 3) & (sizeof(uintptr_t) - 1)) + (((-(int)sizeof(target_ulong)) * 3) & (sizeof(uintptr_t) - 1)) +
sizeof(uintptr_t))]; sizeof(uintptr_t))];

2
qemu/include/exec/exec-all.h
View file

@ -196,7 +196,7 @@ static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
target_ulong tmp; target_ulong tmp;
tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK) return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
| (tmp & TB_JMP_ADDR_MASK)); | (tmp & TB_JMP_ADDR_MASK));
} }
static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc) static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)

16
qemu/include/exec/memory.h
View file

@ -241,14 +241,14 @@ struct MemoryRegionSection {
static inline MemoryRegionSection MemoryRegionSection_make(MemoryRegion *mr, AddressSpace *address_space, static inline MemoryRegionSection MemoryRegionSection_make(MemoryRegion *mr, AddressSpace *address_space,
hwaddr offset_within_region, Int128 size, hwaddr offset_within_address_space, bool readonly) hwaddr offset_within_region, Int128 size, hwaddr offset_within_address_space, bool readonly)
{ {
MemoryRegionSection section; MemoryRegionSection section;
section.mr = mr; section.mr = mr;
section.address_space = address_space; section.address_space = address_space;
section.offset_within_region = offset_within_region; section.offset_within_region = offset_within_region;
section.size = size; section.size = size;
section.offset_within_address_space = offset_within_address_space; section.offset_within_address_space = offset_within_address_space;
section.readonly = readonly; section.readonly = readonly;
return section; return section;
} }
/** /**

12
qemu/include/qemu/aes.h
View file

@ -20,17 +20,17 @@ typedef struct aes_key_st AES_KEY;
#endif #endif
int AES_set_encrypt_key(const unsigned char *userKey, const int bits, int AES_set_encrypt_key(const unsigned char *userKey, const int bits,
AES_KEY *key); AES_KEY *key);
int AES_set_decrypt_key(const unsigned char *userKey, const int bits, int AES_set_decrypt_key(const unsigned char *userKey, const int bits,
AES_KEY *key); AES_KEY *key);
void AES_encrypt(const unsigned char *in, unsigned char *out, void AES_encrypt(const unsigned char *in, unsigned char *out,
const AES_KEY *key); const AES_KEY *key);
void AES_decrypt(const unsigned char *in, unsigned char *out, void AES_decrypt(const unsigned char *in, unsigned char *out,
const AES_KEY *key); const AES_KEY *key);
void AES_cbc_encrypt(const unsigned char *in, unsigned char *out, void AES_cbc_encrypt(const unsigned char *in, unsigned char *out,
const unsigned long length, const AES_KEY *key, const unsigned long length, const AES_KEY *key,
unsigned char *ivec, const int enc); unsigned char *ivec, const int enc);
extern const uint8_t AES_sbox[256]; extern const uint8_t AES_sbox[256];
extern const uint8_t AES_isbox[256]; extern const uint8_t AES_isbox[256];

40
qemu/include/qemu/bitops.h
View file

@ -32,10 +32,10 @@
*/ */
static inline void set_bit(long nr, unsigned long *addr) static inline void set_bit(long nr, unsigned long *addr)
{ {
unsigned long mask = BIT_MASK(nr); unsigned long mask = BIT_MASK(nr);
unsigned long *p = addr + BIT_WORD(nr); unsigned long *p = addr + BIT_WORD(nr);
*p |= mask; *p |= mask;
} }
/** /**
@ -45,10 +45,10 @@ static inline void set_bit(long nr, unsigned long *addr)
*/ */
static inline void clear_bit(long nr, unsigned long *addr) static inline void clear_bit(long nr, unsigned long *addr)
{ {
unsigned long mask = BIT_MASK(nr); unsigned long mask = BIT_MASK(nr);
unsigned long *p = addr + BIT_WORD(nr); unsigned long *p = addr + BIT_WORD(nr);
*p &= ~mask; *p &= ~mask;
} }
/** /**
@ -58,10 +58,10 @@ static inline void clear_bit(long nr, unsigned long *addr)
*/ */
static inline void change_bit(long nr, unsigned long *addr) static inline void change_bit(long nr, unsigned long *addr)
{ {
unsigned long mask = BIT_MASK(nr); unsigned long mask = BIT_MASK(nr);
unsigned long *p = addr + BIT_WORD(nr); unsigned long *p = addr + BIT_WORD(nr);
*p ^= mask; *p ^= mask;
} }
/** /**
@ -71,12 +71,12 @@ static inline void change_bit(long nr, unsigned long *addr)
*/ */
static inline int test_and_set_bit(long nr, unsigned long *addr) static inline int test_and_set_bit(long nr, unsigned long *addr)
{ {
unsigned long mask = BIT_MASK(nr); unsigned long mask = BIT_MASK(nr);
unsigned long *p = addr + BIT_WORD(nr); unsigned long *p = addr + BIT_WORD(nr);
unsigned long old = *p; unsigned long old = *p;
*p = old | mask; *p = old | mask;
return (old & mask) != 0; return (old & mask) != 0;
} }
/** /**
@ -86,12 +86,12 @@ static inline int test_and_set_bit(long nr, unsigned long *addr)
*/ */
static inline int test_and_clear_bit(long nr, unsigned long *addr) static inline int test_and_clear_bit(long nr, unsigned long *addr)
{ {
unsigned long mask = BIT_MASK(nr); unsigned long mask = BIT_MASK(nr);
unsigned long *p = addr + BIT_WORD(nr); unsigned long *p = addr + BIT_WORD(nr);
unsigned long old = *p; unsigned long old = *p;
*p = old & ~mask; *p = old & ~mask;
return (old & mask) != 0; return (old & mask) != 0;
} }
/** /**
@ -101,12 +101,12 @@ static inline int test_and_clear_bit(long nr, unsigned long *addr)
*/ */
static inline int test_and_change_bit(long nr, unsigned long *addr) static inline int test_and_change_bit(long nr, unsigned long *addr)
{ {
unsigned long mask = BIT_MASK(nr); unsigned long mask = BIT_MASK(nr);
unsigned long *p = addr + BIT_WORD(nr); unsigned long *p = addr + BIT_WORD(nr);
unsigned long old = *p; unsigned long old = *p;
*p = old ^ mask; *p = old ^ mask;
return (old & mask) != 0; return (old & mask) != 0;
} }
/** /**
@ -116,7 +116,7 @@ static inline int test_and_change_bit(long nr, unsigned long *addr)
*/ */
static inline int test_bit(long nr, const unsigned long *addr) static inline int test_bit(long nr, const unsigned long *addr)
{ {
return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1))); return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
} }
/** /**
@ -126,7 +126,7 @@ static inline int test_bit(long nr, const unsigned long *addr)
* @size: The bitmap size in bits * @size: The bitmap size in bits
*/ */
unsigned long find_next_bit(const unsigned long *addr, unsigned long find_next_bit(const unsigned long *addr,
unsigned long size, unsigned long offset); unsigned long size, unsigned long offset);
/** /**
* find_next_zero_bit - find the next cleared bit in a memory region * find_next_zero_bit - find the next cleared bit in a memory region

2
qemu/include/qemu/compiler.h
View file

@ -17,7 +17,7 @@
static double rint( double x ) static double rint( double x )
{ {
return floor(x < 0 ? x - 0.5 : x + 0.5); return floor(x < 0 ? x - 0.5 : x + 0.5);
} }
union MSVC_FLOAT_HACK union MSVC_FLOAT_HACK

28
qemu/include/qemu/int128.h
View file

@ -13,7 +13,7 @@ struct Int128 {
static inline Int128 int128_make64(uint64_t a) static inline Int128 int128_make64(uint64_t a)
{ {
Int128 i128 = { a, 0 }; Int128 i128 = { a, 0 };
return i128; return i128;
} }
@ -35,19 +35,19 @@ static inline Int128 int128_one(void)
static inline Int128 int128_2_64(void) static inline Int128 int128_2_64(void)
{ {
Int128 i128 = { 0, 1 }; Int128 i128 = { 0, 1 };
return i128; return i128;
} }
static inline Int128 int128_exts64(int64_t a) static inline Int128 int128_exts64(int64_t a)
{ {
Int128 i128 = { a, (a < 0) ? -1 : 0 }; Int128 i128 = { a, (a < 0) ? -1 : 0 };
return i128; return i128;
} }
static inline Int128 int128_and(Int128 a, Int128 b) static inline Int128 int128_and(Int128 a, Int128 b)
{ {
Int128 i128 = { a.lo & b.lo, a.hi & b.hi }; Int128 i128 = { a.lo & b.lo, a.hi & b.hi };
return i128; return i128;
} }
@ -59,11 +59,11 @@ static inline Int128 int128_rshift(Int128 a, int n)
} }
h = a.hi >> (n & 63); h = a.hi >> (n & 63);
if (n >= 64) { if (n >= 64) {
Int128 i128 = { h, h >> 63 }; Int128 i128 = { h, h >> 63 };
return i128; return i128;
} else { } else {
Int128 i128 = { (a.lo >> n) | ((uint64_t)a.hi << (64 - n)), h }; Int128 i128 = { (a.lo >> n) | ((uint64_t)a.hi << (64 - n)), h };
return i128; return i128;
} }
} }
@ -77,21 +77,21 @@ static inline Int128 int128_add(Int128 a, Int128 b)
* *
* So the carry is lo < a.lo. * So the carry is lo < a.lo.
*/ */
Int128 i128 = { lo, (uint64_t)a.hi + b.hi + (lo < a.lo) }; Int128 i128 = { lo, (uint64_t)a.hi + b.hi + (lo < a.lo) };
return i128; return i128;
} }
static inline Int128 int128_neg(Int128 a) static inline Int128 int128_neg(Int128 a)
{ {
uint64_t lo = 0-a.lo; uint64_t lo = 0-a.lo;
Int128 i128 = { lo, ~(uint64_t)a.hi + !lo }; Int128 i128 = { lo, ~(uint64_t)a.hi + !lo };
return i128; return i128;
} }
static inline Int128 int128_sub(Int128 a, Int128 b) static inline Int128 int128_sub(Int128 a, Int128 b)
{ {
Int128 i128 = { a.lo - b.lo, (uint64_t)a.hi - b.hi - (a.lo < b.lo) }; Int128 i128 = { a.lo - b.lo, (uint64_t)a.hi - b.hi - (a.lo < b.lo) };
return i128; return i128;
} }
static inline bool int128_nonneg(Int128 a) static inline bool int128_nonneg(Int128 a)

4
qemu/include/qemu/timer.h
View file

@ -229,7 +229,7 @@ static inline int64_t cpu_get_real_ticks(void)
static inline int64_t cpu_get_real_ticks(void) static inline int64_t cpu_get_real_ticks(void)
{ {
#ifdef _MSC_VER #ifdef _MSC_VER
return __rdtsc(); return __rdtsc();
#else #else
int64_t val; int64_t val;
asm volatile ("rdtsc" : "=A" (val)); asm volatile ("rdtsc" : "=A" (val));
@ -242,7 +242,7 @@ static inline int64_t cpu_get_real_ticks(void)
static inline int64_t cpu_get_real_ticks(void) static inline int64_t cpu_get_real_ticks(void)
{ {
#ifdef _MSC_VER #ifdef _MSC_VER
return __rdtsc(); return __rdtsc();
#else #else
uint32_t low,high; uint32_t low,high;
int64_t val; int64_t val;

40
qemu/memory.c
View file

@ -140,9 +140,9 @@ struct AddrRange {
static AddrRange addrrange_make(Int128 start, Int128 size) static AddrRange addrrange_make(Int128 start, Int128 size)
{ {
AddrRange ar; AddrRange ar;
ar.start = start; ar.start = start;
ar.size = size; ar.size = size;
return ar; return ar;
} }
static bool addrrange_equal(AddrRange r1, AddrRange r2) static bool addrrange_equal(AddrRange r1, AddrRange r2)
@ -243,9 +243,9 @@ static bool memory_listener_match(MemoryListener *listener,
/* No need to ref/unref .mr, the FlatRange keeps it alive. */ /* No need to ref/unref .mr, the FlatRange keeps it alive. */
#define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback) \ #define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback) \
do { MemoryRegionSection _mrs = MemoryRegionSection_make((fr)->mr, as, (fr)->offset_in_region, \ do { MemoryRegionSection _mrs = MemoryRegionSection_make((fr)->mr, as, (fr)->offset_in_region, \
(fr)->addr.size, int128_get64((fr)->addr.start), (fr)->readonly); \ (fr)->addr.size, int128_get64((fr)->addr.start), (fr)->readonly); \
MEMORY_LISTENER_CALL(callback, dir, &_mrs); } while(0); MEMORY_LISTENER_CALL(callback, dir, &_mrs); } while(0);
/* /*
MEMORY_LISTENER_CALL(callback, dir, (&(MemoryRegionSection) { \ MEMORY_LISTENER_CALL(callback, dir, (&(MemoryRegionSection) { \
@ -272,12 +272,12 @@ struct MemoryRegionIoeventfd {
static MemoryRegionIoeventfd MemoryRegionIoeventfd_make(AddrRange addr, bool match_data, uint64_t data, EventNotifier *e) static MemoryRegionIoeventfd MemoryRegionIoeventfd_make(AddrRange addr, bool match_data, uint64_t data, EventNotifier *e)
{ {
MemoryRegionIoeventfd mrfd; MemoryRegionIoeventfd mrfd;
mrfd.addr = addr; mrfd.addr = addr;
mrfd.match_data = match_data; mrfd.match_data = match_data;
mrfd.data = data; mrfd.data = data;
mrfd.e = e; mrfd.e = e;
return mrfd; return mrfd;
} }
static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a, static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a,
@ -392,7 +392,7 @@ static void flatview_destroy(FlatView *view)
static void flatview_ref(FlatView *view) static void flatview_ref(FlatView *view)
{ {
atomic_inc(&view->ref); atomic_inc(&view->ref);
} }
static void flatview_unref(FlatView *view) static void flatview_unref(FlatView *view)
@ -1093,12 +1093,12 @@ static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
} }
const MemoryRegionOps unassigned_mem_ops = { const MemoryRegionOps unassigned_mem_ops = {
NULL, NULL,
NULL, NULL,
DEVICE_NATIVE_ENDIAN, DEVICE_NATIVE_ENDIAN,
{0,0,false,unassigned_mem_accepts}, {0,0,false,unassigned_mem_accepts},
}; };
bool memory_region_access_valid(MemoryRegion *mr, bool memory_region_access_valid(MemoryRegion *mr,
@ -1473,7 +1473,7 @@ void memory_region_add_eventfd(MemoryRegion *mr,
EventNotifier *e) EventNotifier *e)
{ {
MemoryRegionIoeventfd mrfd = MemoryRegionIoeventfd_make( MemoryRegionIoeventfd mrfd = MemoryRegionIoeventfd_make(
addrrange_make(int128_make64(addr), int128_make64(size)), addrrange_make(int128_make64(addr), int128_make64(size)),
match_data, data, e); match_data, data, e);
unsigned i; unsigned i;
@ -1502,7 +1502,7 @@ void memory_region_del_eventfd(MemoryRegion *mr,
EventNotifier *e) EventNotifier *e)
{ {
MemoryRegionIoeventfd mrfd = MemoryRegionIoeventfd_make( MemoryRegionIoeventfd mrfd = MemoryRegionIoeventfd_make(
addrrange_make(int128_make64(addr), int128_make64(size)), addrrange_make(int128_make64(addr), int128_make64(size)),
match_data, data, e); match_data, data, e);
unsigned i; unsigned i;
@ -1876,13 +1876,13 @@ static const TypeInfo memory_region_info = {
TYPE_MEMORY_REGION, TYPE_MEMORY_REGION,
TYPE_OBJECT, TYPE_OBJECT,
0, 0,
sizeof(MemoryRegion), sizeof(MemoryRegion),
NULL, NULL,
memory_region_initfn, memory_region_initfn,
NULL, NULL,
memory_region_finalize, memory_region_finalize,
}; };
void memory_register_types(struct uc_struct *uc) void memory_register_types(struct uc_struct *uc)

2
qemu/qom/container.c
View file

@ -17,7 +17,7 @@
static const TypeInfo container_info = { static const TypeInfo container_info = {
"container", "container",
TYPE_OBJECT, TYPE_OBJECT,
0, 0,
sizeof(Object), sizeof(Object),
}; };

22
qemu/qom/cpu.c
View file

@ -261,21 +261,21 @@ static const TypeInfo cpu_type_info = {
TYPE_CPU, TYPE_CPU,
TYPE_DEVICE, TYPE_DEVICE,
sizeof(CPUClass), sizeof(CPUClass),
sizeof(CPUState), sizeof(CPUState),
NULL, NULL,
cpu_common_initfn, cpu_common_initfn,
NULL, NULL,
NULL, NULL,
NULL, NULL,
cpu_class_init, cpu_class_init,
NULL, NULL,
NULL, NULL,
true, true,
}; };
void cpu_register_types(struct uc_struct *uc) void cpu_register_types(struct uc_struct *uc)

38
qemu/qom/object.c
View file

@ -1646,44 +1646,44 @@ void register_types_object(struct uc_struct *uc)
{ {
static TypeInfo interface_info = { static TypeInfo interface_info = {
TYPE_INTERFACE, // name TYPE_INTERFACE, // name
NULL, NULL,
sizeof(InterfaceClass), // class_size sizeof(InterfaceClass), // class_size
0, 0,
NULL, NULL,
NULL, NULL,
NULL, NULL,
NULL, NULL,
NULL, NULL,
NULL, NULL,
NULL, NULL,
NULL, NULL,
true, // abstract true, // abstract
}; };
static TypeInfo object_info = { static TypeInfo object_info = {
TYPE_OBJECT, TYPE_OBJECT,
NULL, NULL,
0, 0,
sizeof(Object), sizeof(Object),
NULL, NULL,
object_instance_init, object_instance_init,
NULL,
NULL, NULL,
NULL,
NULL, NULL,
NULL, NULL,
NULL, NULL,
NULL, NULL,
true, true,
}; };
uc->type_interface = type_register_internal(uc, &interface_info); uc->type_interface = type_register_internal(uc, &interface_info);

14
qemu/softmmu_template.h
View file

@ -134,12 +134,12 @@ License along with this library; if not, see <http://www.gnu.org/licenses/>. */
#define victim_tlb_hit_funcs #define victim_tlb_hit_funcs
static inline bool victim_tlb_hit_read(CPUArchState *env, target_ulong addr, int mmu_idx, int index) static inline bool victim_tlb_hit_read(CPUArchState *env, target_ulong addr, int mmu_idx, int index)
{ {
VICTIM_TLB_HIT(ADDR_READ); VICTIM_TLB_HIT(ADDR_READ);
} }
static inline bool victim_tlb_hit_write(CPUArchState *env, target_ulong addr, int mmu_idx, int index) static inline bool victim_tlb_hit_write(CPUArchState *env, target_ulong addr, int mmu_idx, int index)
{ {
VICTIM_TLB_HIT(addr_write); VICTIM_TLB_HIT(addr_write);
} }
#endif // victim_tlb_hit_funcs #endif // victim_tlb_hit_funcs
@ -179,7 +179,7 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
int error_code; int error_code;
struct hook *hook; struct hook *hook;
bool handled; bool handled;
HOOK_FOREACH_VAR_DECLARE; HOOK_FOREACH_VAR_DECLARE;
struct uc_struct *uc = env->uc; struct uc_struct *uc = env->uc;
MemoryRegion *mr = memory_mapping(uc, addr); MemoryRegion *mr = memory_mapping(uc, addr);
@ -293,7 +293,7 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
return 0; return 0;
} }
#endif #endif
if (!victim_tlb_hit_read(env, addr, mmu_idx, index)) { if (!victim_tlb_hit_read(env, addr, mmu_idx, index)) {
tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE,
mmu_idx, retaddr); mmu_idx, retaddr);
} }
@ -407,7 +407,7 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx,
int error_code; int error_code;
struct hook *hook; struct hook *hook;
bool handled; bool handled;
HOOK_FOREACH_VAR_DECLARE; HOOK_FOREACH_VAR_DECLARE;
struct uc_struct *uc = env->uc; struct uc_struct *uc = env->uc;
MemoryRegion *mr = memory_mapping(uc, addr); MemoryRegion *mr = memory_mapping(uc, addr);
@ -672,7 +672,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
uintptr_t haddr; uintptr_t haddr;
struct hook *hook; struct hook *hook;
bool handled; bool handled;
HOOK_FOREACH_VAR_DECLARE; HOOK_FOREACH_VAR_DECLARE;
struct uc_struct *uc = env->uc; struct uc_struct *uc = env->uc;
MemoryRegion *mr = memory_mapping(uc, addr); MemoryRegion *mr = memory_mapping(uc, addr);
@ -831,7 +831,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val,
uintptr_t haddr; uintptr_t haddr;
struct hook *hook; struct hook *hook;
bool handled; bool handled;
HOOK_FOREACH_VAR_DECLARE; HOOK_FOREACH_VAR_DECLARE;
struct uc_struct *uc = env->uc; struct uc_struct *uc = env->uc;
MemoryRegion *mr = memory_mapping(uc, addr); MemoryRegion *mr = memory_mapping(uc, addr);

2
qemu/target-arm/helper-a64.c
View file

@ -424,7 +424,7 @@ uint64_t HELPER(crc32_64)(uint64_t acc, uint64_t val, uint32_t bytes)
/* zlib crc32 converts the accumulator and output to one's complement. */ /* zlib crc32 converts the accumulator and output to one's complement. */
// return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; // return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
return 0; // FIXME return 0; // FIXME
} }
uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, uint32_t bytes) uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, uint32_t bytes)

98
qemu/target-arm/helper.c
View file

@ -4110,13 +4110,13 @@ static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
*page_size = 1024 * 1024; *page_size = 1024 * 1024;
} else { } else {
/* Lookup l2 entry. */ /* Lookup l2 entry. */
if (type == 1) { if (type == 1) {
/* Coarse pagetable. */ /* Coarse pagetable. */
table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
} else { } else {
/* Fine pagetable. */ /* Fine pagetable. */
table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
} }
desc = ldl_phys(cs->as, table); desc = ldl_phys(cs->as, table);
switch (desc & 3) { switch (desc & 3) {
case 0: /* Page translation fault. */ case 0: /* Page translation fault. */
@ -4133,17 +4133,17 @@ static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
*page_size = 0x1000; *page_size = 0x1000;
break; break;
case 3: /* 1k page. */ case 3: /* 1k page. */
if (type == 1) { if (type == 1) {
if (arm_feature(env, ARM_FEATURE_XSCALE)) { if (arm_feature(env, ARM_FEATURE_XSCALE)) {
phys_addr = (desc & 0xfffff000) | (address & 0xfff); phys_addr = (desc & 0xfffff000) | (address & 0xfff);
} else { } else {
/* Page translation fault. */ /* Page translation fault. */
code = 7; code = 7;
goto do_fault; goto do_fault;
} }
} else { } else {
phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
} }
ap = (desc >> 4) & 3; ap = (desc >> 4) & 3;
*page_size = 0x400; *page_size = 0x400;
break; break;
@ -4516,18 +4516,18 @@ static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
*phys_ptr = address; *phys_ptr = address;
for (n = 7; n >= 0; n--) { for (n = 7; n >= 0; n--) {
base = env->cp15.c6_region[n]; base = env->cp15.c6_region[n];
if ((base & 1) == 0) if ((base & 1) == 0)
continue; continue;
mask = 1 << ((base >> 1) & 0x1f); mask = 1 << ((base >> 1) & 0x1f);
/* Keep this shift separate from the above to avoid an /* Keep this shift separate from the above to avoid an
(undefined) << 32. */ (undefined) << 32. */
mask = (mask << 1) - 1; mask = (mask << 1) - 1;
if (((base ^ address) & ~mask) == 0) if (((base ^ address) & ~mask) == 0)
break; break;
} }
if (n < 0) if (n < 0)
return 2; return 2;
if (access_type == 2) { if (access_type == 2) {
mask = env->cp15.pmsav5_insn_ap; mask = env->cp15.pmsav5_insn_ap;
@ -4537,31 +4537,31 @@ static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
mask = (mask >> (n * 4)) & 0xf; mask = (mask >> (n * 4)) & 0xf;
switch (mask) { switch (mask) {
case 0: case 0:
return 1; return 1;
case 1: case 1:
if (is_user) if (is_user)
return 1; return 1;
*prot = PAGE_READ | PAGE_WRITE; *prot = PAGE_READ | PAGE_WRITE;
break; break;
case 2: case 2:
*prot = PAGE_READ; *prot = PAGE_READ;
if (!is_user) if (!is_user)
*prot |= PAGE_WRITE; *prot |= PAGE_WRITE;
break; break;
case 3: case 3:
*prot = PAGE_READ | PAGE_WRITE; *prot = PAGE_READ | PAGE_WRITE;
break; break;
case 5: case 5:
if (is_user) if (is_user)
return 1; return 1;
*prot = PAGE_READ; *prot = PAGE_READ;
break; break;
case 6: case 6:
*prot = PAGE_READ; *prot = PAGE_READ;
break; break;
default: default:
/* Bad permission. */ /* Bad permission. */
return 1; return 1;
} }
*prot |= PAGE_EXEC; *prot |= PAGE_EXEC;
return 0; return 0;
@ -4607,8 +4607,8 @@ static inline int get_phys_addr(CPUARMState *env, target_ulong address,
return 0; return 0;
} else if (arm_feature(env, ARM_FEATURE_MPU)) { } else if (arm_feature(env, ARM_FEATURE_MPU)) {
*page_size = TARGET_PAGE_SIZE; *page_size = TARGET_PAGE_SIZE;
return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr, return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
prot); prot);
} else if (extended_addresses_enabled(env)) { } else if (extended_addresses_enabled(env)) {
return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr, return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
prot, page_size); prot, page_size);

328
qemu/target-i386/cpu.c
View file

@ -310,24 +310,24 @@ typedef struct FeatureWordInfo {
static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
#ifdef _MSC_VER #ifdef _MSC_VER
// FEAT_1_EDX // FEAT_1_EDX
{ {
feature_name, feature_name,
1, 1,
false,0, false,0,
R_EDX, R_EDX,
TCG_FEATURES, TCG_FEATURES,
}, },
// FEAT_1_ECX // FEAT_1_ECX
{ {
ext_feature_name, ext_feature_name,
1, 1,
false,0, false,0,
R_ECX, R_ECX,
TCG_EXT_FEATURES, TCG_EXT_FEATURES,
}, },
// FEAT_7_0_EBX // FEAT_7_0_EBX
{ {
cpuid_7_0_ebx_feature_name, cpuid_7_0_ebx_feature_name,
7, 7,
true, 0, true, 0,
@ -335,44 +335,44 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
TCG_7_0_EBX_FEATURES, TCG_7_0_EBX_FEATURES,
}, },
// FEAT_8000_0001_EDX // FEAT_8000_0001_EDX
{ {
ext2_feature_name, ext2_feature_name,
0x80000001, 0x80000001,
false,0, false,0,
R_EDX, R_EDX,
TCG_EXT2_FEATURES, TCG_EXT2_FEATURES,
}, },
// FEAT_8000_0001_ECX // FEAT_8000_0001_ECX
{ {
ext3_feature_name, ext3_feature_name,
0x80000001, 0x80000001,
false,0, false,0,
R_ECX, R_ECX,
TCG_EXT3_FEATURES, TCG_EXT3_FEATURES,
}, },
// FEAT_8000_0007_EDX // FEAT_8000_0007_EDX
{ {
cpuid_apm_edx_feature_name, cpuid_apm_edx_feature_name,
0x80000007, 0x80000007,
false,0, false,0,
R_EDX, R_EDX,
TCG_APM_FEATURES, TCG_APM_FEATURES,
CPUID_APM_INVTSC, CPUID_APM_INVTSC,
}, },
// FEAT_C000_0001_EDX // FEAT_C000_0001_EDX
{ {
ext4_feature_name, ext4_feature_name,
0xC0000001, 0xC0000001,
false,0, false,0,
R_EDX, R_EDX,
TCG_EXT4_FEATURES, TCG_EXT4_FEATURES,
}, },
// FEAT_KVM // FEAT_KVM
{0}, {0},
// FEAT_SVM // FEAT_SVM
{0}, {0},
#else #else
[FEAT_1_EDX] = { [FEAT_1_EDX] = {
.feat_names = feature_name, .feat_names = feature_name,
.cpuid_eax = 1, .cpuid_reg = R_EDX, .cpuid_eax = 1, .cpuid_reg = R_EDX,
.tcg_features = TCG_FEATURES, .tcg_features = TCG_FEATURES,
@ -458,7 +458,7 @@ void host_cpuid(uint32_t function, uint32_t count,
uint32_t vec[4]; uint32_t vec[4];
#ifdef _MSC_VER #ifdef _MSC_VER
__cpuidex((int*)vec, function, count); __cpuidex((int*)vec, function, count);
#else #else
#ifdef __x86_64__ #ifdef __x86_64__
asm volatile("cpuid" asm volatile("cpuid"
@ -619,61 +619,61 @@ static X86CPUDefinition builtin_x86_defs[] = {
4, 0x8000000A, 0, 4, 0x8000000A, 0,
CPUID_VENDOR_AMD, CPUID_VENDOR_AMD,
6, 6, 3, 6, 6, 3,
{ {
// FEAT_1_EDX // FEAT_1_EDX
PPRO_FEATURES | PPRO_FEATURES |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
CPUID_PSE36, CPUID_PSE36,
// FEAT_1_ECX // FEAT_1_ECX
CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT, CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
// FEAT_7_0_EBX // FEAT_7_0_EBX
0, 0,
// FEAT_8000_0001_EDX // FEAT_8000_0001_EDX
(PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
// FEAT_8000_0001_ECX // FEAT_8000_0001_ECX
CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
}, },
}, },
{ {
"phenom", "phenom",
5, 0x8000001A, 0, 5, 0x8000001A, 0,
CPUID_VENDOR_AMD, CPUID_VENDOR_AMD,
16, 2, 3, 16, 2, 3,
{ {
/* Missing: CPUID_HT */ /* Missing: CPUID_HT */
// FEAT_1_EDX // FEAT_1_EDX
PPRO_FEATURES | PPRO_FEATURES |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
CPUID_PSE36 | CPUID_VME, CPUID_PSE36 | CPUID_VME,
// FEAT_1_ECX // FEAT_1_ECX
CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
CPUID_EXT_POPCNT, CPUID_EXT_POPCNT,
// FEAT_7_0_EBX // FEAT_7_0_EBX
0, 0,
// FEAT_8000_0001_EDX // FEAT_8000_0001_EDX
(PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
/* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
CPUID_EXT3_CR8LEG, CPUID_EXT3_CR8LEG,
CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
// FEAT_8000_0001_ECX // FEAT_8000_0001_ECX
CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
// FEAT_8000_0007_EDX // FEAT_8000_0007_EDX
0, 0,
// FEAT_C000_0001_EDX // FEAT_C000_0001_EDX
0, 0,
// FEAT_KVM // FEAT_KVM
0, 0,
/* Missing: CPUID_SVM_LBRV */ /* Missing: CPUID_SVM_LBRV */
// FEAT_SVM // FEAT_SVM
CPUID_SVM_NPT, CPUID_SVM_NPT,
}, },
"AMD Phenom(tm) 9550 Quad-Core Processor", "AMD Phenom(tm) 9550 Quad-Core Processor",
}, },
{ {
@ -681,7 +681,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
10, 0x80000008, 0, 10, 0x80000008, 0,
CPUID_VENDOR_INTEL, CPUID_VENDOR_INTEL,
6, 15, 11, 6, 15, 11,
{ {
/* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
// FEAT_1_EDX // FEAT_1_EDX
PPRO_FEATURES | PPRO_FEATURES |
@ -692,13 +692,13 @@ static X86CPUDefinition builtin_x86_defs[] = {
// FEAT_1_ECX // FEAT_1_ECX
CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
CPUID_EXT_CX16, CPUID_EXT_CX16,
// FEAT_7_0_EBX // FEAT_7_0_EBX
0, 0,
// FEAT_8000_0001_EDX // FEAT_8000_0001_EDX
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
// FEAT_8000_0001_ECX // FEAT_8000_0001_ECX
CPUID_EXT3_LAHF_LM, CPUID_EXT3_LAHF_LM,
}, },
"Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
}, },
{ {
@ -706,7 +706,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
5, 0x80000008, 0, 5, 0x80000008, 0,
CPUID_VENDOR_INTEL, CPUID_VENDOR_INTEL,
15, 6, 1, 15, 6, 1,
{ {
/* Missing: CPUID_VME, CPUID_HT */ /* Missing: CPUID_VME, CPUID_HT */
// FEAT_1_EDX // FEAT_1_EDX
PPRO_FEATURES | PPRO_FEATURES |
@ -715,8 +715,8 @@ static X86CPUDefinition builtin_x86_defs[] = {
/* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
// FEAT_1_ECX // FEAT_1_ECX
CPUID_EXT_SSE3 | CPUID_EXT_CX16, CPUID_EXT_SSE3 | CPUID_EXT_CX16,
// FEAT_7_0_EBX // FEAT_7_0_EBX
0, 0,
/* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
// FEAT_8000_0001_EDX // FEAT_8000_0001_EDX
(PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
@ -727,7 +727,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
// FEAT_8000_0001_ECX // FEAT_8000_0001_ECX
0, 0,
}, },
"Common KVM processor", "Common KVM processor",
}, },
{ {
@ -735,31 +735,31 @@ static X86CPUDefinition builtin_x86_defs[] = {
4, 0x80000004, 0, 4, 0x80000004, 0,
CPUID_VENDOR_INTEL, CPUID_VENDOR_INTEL,
6, 6, 3, 6, 6, 3,
{ {
// FEAT_1_EDX // FEAT_1_EDX
PPRO_FEATURES, PPRO_FEATURES,
// FEAT_1_ECX // FEAT_1_ECX
CPUID_EXT_SSE3 | CPUID_EXT_POPCNT, CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
}, },
}, },
{ {
"kvm32", "kvm32",
5, 0x80000008, 0, 5, 0x80000008, 0,
CPUID_VENDOR_INTEL, CPUID_VENDOR_INTEL,
15, 6, 1, 15, 6, 1,
{ {
// FEAT_1_EDX // FEAT_1_EDX
PPRO_FEATURES | PPRO_FEATURES |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
// FEAT_1_ECX // FEAT_1_ECX
CPUID_EXT_SSE3, CPUID_EXT_SSE3,
// FEAT_7_0_EBX // FEAT_7_0_EBX
0, 0,
// FEAT_8000_0001_EDX // FEAT_8000_0001_EDX
PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES, PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
// FEAT_8000_0001_ECX // FEAT_8000_0001_ECX
0, 0,
}, },
"Common 32-bit KVM processor", "Common 32-bit KVM processor",
}, },
{ {
@ -767,7 +767,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
10, 0x80000008, 0, 10, 0x80000008, 0,
CPUID_VENDOR_INTEL, CPUID_VENDOR_INTEL,
6, 14, 8, 6, 14, 8,
{ {
/* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
// FEAT_1_EDX // FEAT_1_EDX
PPRO_FEATURES | CPUID_VME | PPRO_FEATURES | CPUID_VME |
@ -777,11 +777,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
* CPUID_EXT_PDCM, CPUID_EXT_VMX */ * CPUID_EXT_PDCM, CPUID_EXT_VMX */
// FEAT_1_ECX // FEAT_1_ECX
CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, CPUID_EXT_SSE3 | CPUID_EXT_MONITOR,
// FEAT_7_0_EBX // FEAT_7_0_EBX
0, 0,
// FEAT_8000_0001_EDX // FEAT_8000_0001_EDX
CPUID_EXT2_NX, CPUID_EXT2_NX,
}, },
"Genuine Intel(R) CPU T2600 @ 2.16GHz", "Genuine Intel(R) CPU T2600 @ 2.16GHz",
}, },
{ {
@ -789,58 +789,58 @@ static X86CPUDefinition builtin_x86_defs[] = {
1, 0, 0, 1, 0, 0,
CPUID_VENDOR_INTEL, CPUID_VENDOR_INTEL,
4, 8, 0, 4, 8, 0,
{ {
// FEAT_1_EDX // FEAT_1_EDX
I486_FEATURES, I486_FEATURES,
}, },
}, },
{ {
"pentium", "pentium",
1, 0, 0, 1, 0, 0,
CPUID_VENDOR_INTEL, CPUID_VENDOR_INTEL,
5, 4, 3, 5, 4, 3,
{ {
// FEAT_1_EDX // FEAT_1_EDX
PENTIUM_FEATURES, PENTIUM_FEATURES,
}, },
}, },
{ {
"pentium2", "pentium2",
2, 0, 0, 2, 0, 0,
CPUID_VENDOR_INTEL, CPUID_VENDOR_INTEL,
6, 5, 2, 6, 5, 2,
{ {
// FEAT_1_EDX // FEAT_1_EDX
PENTIUM2_FEATURES, PENTIUM2_FEATURES,
}, },
}, },
{ {
"pentium3", "pentium3",
2, 0, 0, 2, 0, 0,
CPUID_VENDOR_INTEL, CPUID_VENDOR_INTEL,
6, 7, 3, 6, 7, 3,
{ {
// FEAT_1_EDX // FEAT_1_EDX
PENTIUM3_FEATURES, PENTIUM3_FEATURES,
}, },
}, },
{ {
"athlon", "athlon",
2, 0x80000008, 0, 2, 0x80000008, 0,
CPUID_VENDOR_AMD, CPUID_VENDOR_AMD,
6, 2, 3, 6, 2, 3,
{ {
// FEAT_1_EDX // FEAT_1_EDX
PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
CPUID_MCA, CPUID_MCA,
// FEAT_1_ECX // FEAT_1_ECX
0, 0,
// FEAT_7_0_EBX // FEAT_7_0_EBX
0, 0,
// FEAT_8000_0001_EDX // FEAT_8000_0001_EDX
(PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
}, },
}, },
{ {
"n270", "n270",
@ -848,7 +848,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
5, 0x8000000A, 0, 5, 0x8000000A, 0,
CPUID_VENDOR_INTEL, CPUID_VENDOR_INTEL,
6, 28, 2, 6, 28, 2,
{ {
/* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */
// FEAT_1_EDX // FEAT_1_EDX
PPRO_FEATURES | PPRO_FEATURES |
@ -860,14 +860,14 @@ static X86CPUDefinition builtin_x86_defs[] = {
// FEAT_1_ECX // FEAT_1_ECX
CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
CPUID_EXT_MOVBE, CPUID_EXT_MOVBE,
// FEAT_7_0_EBX // FEAT_7_0_EBX
0, 0,
// FEAT_8000_0001_EDX // FEAT_8000_0001_EDX
(PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
CPUID_EXT2_NX, CPUID_EXT2_NX,
// FEAT_8000_0001_ECX // FEAT_8000_0001_ECX
CPUID_EXT3_LAHF_LM, CPUID_EXT3_LAHF_LM,
}, },
"Intel(R) Atom(TM) CPU N270 @ 1.60GHz", "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
}, },
{ {
@ -875,7 +875,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
4, 0x8000000A, 0, 4, 0x8000000A, 0,
CPUID_VENDOR_INTEL, CPUID_VENDOR_INTEL,
6, 15, 3, 6, 15, 3,
{ {
// FEAT_1_EDX // FEAT_1_EDX
CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
@ -884,13 +884,13 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_DE | CPUID_FP87, CPUID_DE | CPUID_FP87,
// FEAT_1_ECX // FEAT_1_ECX
CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
// FEAT_7_0_EBX // FEAT_7_0_EBX
0, 0,
// FEAT_8000_0001_EDX // FEAT_8000_0001_EDX
CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
// FEAT_8000_0001_ECX // FEAT_8000_0001_ECX
CPUID_EXT3_LAHF_LM, CPUID_EXT3_LAHF_LM,
}, },
"Intel Celeron_4x0 (Conroe/Merom Class Core 2)", "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
}, },
{ {
@ -898,7 +898,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
4, 0x8000000A, 0, 4, 0x8000000A, 0,
CPUID_VENDOR_INTEL, CPUID_VENDOR_INTEL,
6, 23, 3, 6, 23, 3,
{ {
// FEAT_1_EDX // FEAT_1_EDX
CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
@ -908,13 +908,13 @@ static X86CPUDefinition builtin_x86_defs[] = {
// FEAT_1_ECX // FEAT_1_ECX
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_SSE3, CPUID_EXT_SSE3,
// FEAT_7_0_EBX // FEAT_7_0_EBX
0, 0,
// FEAT_8000_0001_EDX // FEAT_8000_0001_EDX
CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
// FEAT_8000_0001_ECX // FEAT_8000_0001_ECX
CPUID_EXT3_LAHF_LM, CPUID_EXT3_LAHF_LM,
}, },
"Intel Core 2 Duo P9xxx (Penryn Class Core 2)", "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
}, },
{ {
@ -922,7 +922,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
4, 0x8000000A, 0, 4, 0x8000000A, 0,
CPUID_VENDOR_INTEL, CPUID_VENDOR_INTEL,
6, 26, 3, 6, 26, 3,
{ {
// FEAT_1_EDX // FEAT_1_EDX
CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
@ -932,13 +932,13 @@ static X86CPUDefinition builtin_x86_defs[] = {
// FEAT_1_ECX // FEAT_1_ECX
CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
// FEAT_7_0_EBX // FEAT_7_0_EBX
0, 0,
// FEAT_8000_0001_EDX // FEAT_8000_0001_EDX
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
// FEAT_8000_0001_ECX // FEAT_8000_0001_ECX
CPUID_EXT3_LAHF_LM, CPUID_EXT3_LAHF_LM,
}, },
"Intel Core i7 9xx (Nehalem Class Core i7)", "Intel Core i7 9xx (Nehalem Class Core i7)",
}, },
{ {
@ -946,7 +946,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
11, 0x8000000A, 0, 11, 0x8000000A, 0,
CPUID_VENDOR_INTEL, CPUID_VENDOR_INTEL,
6, 44, 1, 6, 44, 1,
{ {
// FEAT_1_EDX // FEAT_1_EDX
CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
@ -957,13 +957,13 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
// FEAT_7_0_EBX // FEAT_7_0_EBX
0, 0,
// FEAT_8000_0001_EDX // FEAT_8000_0001_EDX
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
// FEAT_8000_0001_ECX // FEAT_8000_0001_ECX
CPUID_EXT3_LAHF_LM, CPUID_EXT3_LAHF_LM,
}, },
"Westmere E56xx/L56xx/X56xx (Nehalem-C)", "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
}, },
{ {
@ -971,7 +971,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
0xd, 0x8000000A, 0, 0xd, 0x8000000A, 0,
CPUID_VENDOR_INTEL, CPUID_VENDOR_INTEL,
6, 42, 1, 6, 42, 1,
{ {
// FEAT_1_EDX // FEAT_1_EDX
CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
@ -984,14 +984,14 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
CPUID_EXT_SSE3, CPUID_EXT_SSE3,
// FEAT_7_0_EBX // FEAT_7_0_EBX
0, 0,
// FEAT_8000_0001_EDX // FEAT_8000_0001_EDX
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
CPUID_EXT2_SYSCALL, CPUID_EXT2_SYSCALL,
// FEAT_8000_0001_ECX // FEAT_8000_0001_ECX
CPUID_EXT3_LAHF_LM, CPUID_EXT3_LAHF_LM,
}, },
"Intel Xeon E312xx (Sandy Bridge)", "Intel Xeon E312xx (Sandy Bridge)",
}, },
{ {
@ -999,7 +999,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
0xd, 0x8000000A, 0, 0xd, 0x8000000A, 0,
CPUID_VENDOR_INTEL, CPUID_VENDOR_INTEL,
6, 60, 1, 6, 60, 1,
{ {
// FEAT_1_EDX // FEAT_1_EDX
CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
@ -1013,7 +1013,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
CPUID_EXT_PCID, CPUID_EXT_PCID,
// FEAT_7_0_EBX // FEAT_7_0_EBX
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
@ -1023,7 +1023,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT2_SYSCALL, CPUID_EXT2_SYSCALL,
// FEAT_8000_0001_ECX // FEAT_8000_0001_ECX
CPUID_EXT3_LAHF_LM, CPUID_EXT3_LAHF_LM,
}, },
"Intel Core Processor (Haswell)", "Intel Core Processor (Haswell)",
}, },
{ {
@ -1031,7 +1031,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
0xd, 0x8000000A, 0, 0xd, 0x8000000A, 0,
CPUID_VENDOR_INTEL, CPUID_VENDOR_INTEL,
6, 61, 2, 6, 61, 2,
{ {
// FEAT_1_EDX // FEAT_1_EDX
CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
@ -1056,7 +1056,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT2_SYSCALL, CPUID_EXT2_SYSCALL,
// FEAT_8000_0001_ECX // FEAT_8000_0001_ECX
CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH,
}, },
"Intel Core Processor (Broadwell)", "Intel Core Processor (Broadwell)",
}, },
{ {
@ -1064,7 +1064,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
5, 0x80000008, 0, 5, 0x80000008, 0,
CPUID_VENDOR_AMD, CPUID_VENDOR_AMD,
15, 6, 1, 15, 6, 1,
{ {
// FEAT_1_EDX // FEAT_1_EDX
CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
@ -1074,7 +1074,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
// FEAT_1_ECX // FEAT_1_ECX
CPUID_EXT_SSE3, CPUID_EXT_SSE3,
// FEAT_7_0_EBX // FEAT_7_0_EBX
0, 0,
// FEAT_8000_0001_EDX // FEAT_8000_0001_EDX
CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
@ -1082,7 +1082,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU, CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
}, },
"AMD Opteron 240 (Gen 1 Class Opteron)", "AMD Opteron 240 (Gen 1 Class Opteron)",
}, },
{ {
@ -1090,7 +1090,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
5, 0x80000008, 0, 5, 0x80000008, 0,
CPUID_VENDOR_AMD, CPUID_VENDOR_AMD,
15, 6, 1, 15, 6, 1,
{ {
// FEAT_1_EDX // FEAT_1_EDX
CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
@ -1100,7 +1100,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
// FEAT_1_ECX // FEAT_1_ECX
CPUID_EXT_CX16 | CPUID_EXT_SSE3, CPUID_EXT_CX16 | CPUID_EXT_SSE3,
// FEAT_7_0_EBX // FEAT_7_0_EBX
0, 0,
// FEAT_8000_0001_EDX // FEAT_8000_0001_EDX
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
@ -1111,7 +1111,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT2_DE | CPUID_EXT2_FPU, CPUID_EXT2_DE | CPUID_EXT2_FPU,
// FEAT_8000_0001_ECX // FEAT_8000_0001_ECX
CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
}, },
"AMD Opteron 22xx (Gen 2 Class Opteron)", "AMD Opteron 22xx (Gen 2 Class Opteron)",
}, },
{ {
@ -1119,7 +1119,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
5, 0x80000008, 0, 5, 0x80000008, 0,
CPUID_VENDOR_AMD, CPUID_VENDOR_AMD,
15, 6, 1, 15, 6, 1,
{ {
// FEAT_1_EDX // FEAT_1_EDX
CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
@ -1130,7 +1130,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
CPUID_EXT_SSE3, CPUID_EXT_SSE3,
// FEAT_7_0_EBX // FEAT_7_0_EBX
0, 0,
// FEAT_8000_0001_EDX // FEAT_8000_0001_EDX
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
@ -1142,7 +1142,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
// FEAT_8000_0001_ECX // FEAT_8000_0001_ECX
CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
}, },
"AMD Opteron 23xx (Gen 3 Class Opteron)", "AMD Opteron 23xx (Gen 3 Class Opteron)",
}, },
{ {
@ -1150,7 +1150,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
0xd, 0x8000001A, 0, 0xd, 0x8000001A, 0,
CPUID_VENDOR_AMD, CPUID_VENDOR_AMD,
21, 1, 2, 21, 1, 2,
{ {
// FEAT_1_EDX // FEAT_1_EDX
CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
@ -1163,7 +1163,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
CPUID_EXT_SSE3, CPUID_EXT_SSE3,
// FEAT_7_0_EBX // FEAT_7_0_EBX
0, 0,
// FEAT_8000_0001_EDX // FEAT_8000_0001_EDX
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
@ -1177,7 +1177,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
CPUID_EXT3_LAHF_LM, CPUID_EXT3_LAHF_LM,
}, },
"AMD Opteron 62xx class CPU", "AMD Opteron 62xx class CPU",
}, },
{ {
@ -1185,7 +1185,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
0xd, 0x8000001A, 0, 0xd, 0x8000001A, 0,
CPUID_VENDOR_AMD, CPUID_VENDOR_AMD,
21, 2, 0, 21, 2, 0,
{ {
// FEAT_1_EDX // FEAT_1_EDX
CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
@ -1198,7 +1198,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
// FEAT_7_0_EBX // FEAT_7_0_EBX
0, 0,
// FEAT_8000_0001_EDX // FEAT_8000_0001_EDX
CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
@ -1212,7 +1212,7 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
CPUID_EXT3_LAHF_LM, CPUID_EXT3_LAHF_LM,
}, },
"AMD Opteron 63xx class CPU", "AMD Opteron 63xx class CPU",
}, },
}; };
@ -1562,8 +1562,8 @@ static void x86_cpu_get_feature_words(struct uc_struct *uc, Object *obj, Visitor
uint32_t *array = (uint32_t *)opaque; uint32_t *array = (uint32_t *)opaque;
FeatureWord w; FeatureWord w;
Error *err = NULL; Error *err = NULL;
// These all get setup below, so no need to initialise them here. // These all get setup below, so no need to initialise them here.
X86CPUFeatureWordInfo word_infos[FEATURE_WORDS]; X86CPUFeatureWordInfo word_infos[FEATURE_WORDS];
X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS]; X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS];
X86CPUFeatureWordInfoList *list = NULL; X86CPUFeatureWordInfoList *list = NULL;
@ -1844,16 +1844,16 @@ static void x86_register_cpudef_type(struct uc_struct *uc, X86CPUDefinition *def
TYPE_X86_CPU, TYPE_X86_CPU,
0, 0,
0, 0,
NULL, NULL,
NULL, NULL,
NULL, NULL,
NULL, NULL,
def, def,
x86_cpu_cpudef_class_init, x86_cpu_cpudef_class_init,
}; };
type_register(uc, &ti); type_register(uc, &ti);
@ -2459,7 +2459,7 @@ uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
static void x86_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque) static void x86_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
{ {
//printf("... X86 initialize (object)\n"); //printf("... X86 initialize (object)\n");
CPUState *cs = CPU(obj); CPUState *cs = CPU(obj);
X86CPU *cpu = X86_CPU(cs->uc, obj); X86CPU *cpu = X86_CPU(cs->uc, obj);
X86CPUClass *xcc = X86_CPU_GET_CLASS(uc, obj); X86CPUClass *xcc = X86_CPU_GET_CLASS(uc, obj);
@ -2563,7 +2563,7 @@ static bool x86_cpu_has_work(CPUState *cs)
static void x86_cpu_common_class_init(struct uc_struct *uc, ObjectClass *oc, void *data) static void x86_cpu_common_class_init(struct uc_struct *uc, ObjectClass *oc, void *data)
{ {
//printf("... init X86 cpu common class\n"); //printf("... init X86 cpu common class\n");
X86CPUClass *xcc = X86_CPU_CLASS(uc, oc); X86CPUClass *xcc = X86_CPU_CLASS(uc, oc);
CPUClass *cc = CPU_CLASS(uc, oc); CPUClass *cc = CPU_CLASS(uc, oc);
DeviceClass *dc = DEVICE_CLASS(uc, oc); DeviceClass *dc = DEVICE_CLASS(uc, oc);
@ -2601,33 +2601,33 @@ static void x86_cpu_common_class_init(struct uc_struct *uc, ObjectClass *oc, voi
void x86_cpu_register_types(void *opaque) void x86_cpu_register_types(void *opaque)
{ {
const TypeInfo x86_cpu_type_info = { const TypeInfo x86_cpu_type_info = {
TYPE_X86_CPU, TYPE_X86_CPU,
TYPE_CPU, TYPE_CPU,
sizeof(X86CPUClass), sizeof(X86CPUClass),
sizeof(X86CPU), sizeof(X86CPU),
opaque, opaque,
x86_cpu_initfn, x86_cpu_initfn,
NULL, NULL,
NULL, NULL,
NULL, NULL,
x86_cpu_common_class_init, x86_cpu_common_class_init,
NULL, NULL,
NULL, NULL,
true, true,
}; };
//printf("... register X86 cpu\n"); //printf("... register X86 cpu\n");
int i; int i;
type_register_static(opaque, &x86_cpu_type_info); type_register_static(opaque, &x86_cpu_type_info);
for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
x86_register_cpudef_type(opaque, &builtin_x86_defs[i]); x86_register_cpudef_type(opaque, &builtin_x86_defs[i]);
} }
//printf("... END OF register X86 cpu\n"); //printf("... END OF register X86 cpu\n");
} }

6
qemu/target-i386/cpu.h
View file

@ -870,7 +870,7 @@ typedef struct CPUX86State {
/* Beginning of state preserved by INIT (dummy marker). */ /* Beginning of state preserved by INIT (dummy marker). */
//struct {} start_init_save; //struct {} start_init_save;
int start_init_save; int start_init_save;
/* FPU state */ /* FPU state */
unsigned int fpstt; /* top of stack index */ unsigned int fpstt; /* top of stack index */
@ -939,7 +939,7 @@ typedef struct CPUX86State {
/* End of state preserved by INIT (dummy marker). */ /* End of state preserved by INIT (dummy marker). */
//struct {} end_init_save; //struct {} end_init_save;
int end_init_save; int end_init_save;
uint64_t system_time_msr; uint64_t system_time_msr;
uint64_t wall_clock_msr; uint64_t wall_clock_msr;
@ -986,7 +986,7 @@ typedef struct CPUX86State {
#if CPU_VTLB_SIZE == 0 #if CPU_VTLB_SIZE == 0
#error CPU_VTLB_SIZE is zero #error CPU_VTLB_SIZE is zero
#endif #endif
CPU_COMMON CPU_COMMON
/* Fields from here on are preserved across CPU reset. */ /* Fields from here on are preserved across CPU reset. */

28
qemu/target-i386/fpu_helper.c
View file

@ -490,56 +490,56 @@ void helper_fabs_ST0(CPUX86State *env)
void helper_fld1_ST0(CPUX86State *env) void helper_fld1_ST0(CPUX86State *env)
{ {
//ST0 = floatx80_one; //ST0 = floatx80_one;
floatx80 one = { 0x8000000000000000LL, 0x3fff }; floatx80 one = { 0x8000000000000000LL, 0x3fff };
ST0 = one; ST0 = one;
} }
void helper_fldl2t_ST0(CPUX86State *env) void helper_fldl2t_ST0(CPUX86State *env)
{ {
//ST0 = floatx80_l2t; //ST0 = floatx80_l2t;
floatx80 l2t = { 0xd49a784bcd1b8afeLL, 0x4000 }; floatx80 l2t = { 0xd49a784bcd1b8afeLL, 0x4000 };
ST0 = l2t; ST0 = l2t;
} }
void helper_fldl2e_ST0(CPUX86State *env) void helper_fldl2e_ST0(CPUX86State *env)
{ {
//ST0 = floatx80_l2e; //ST0 = floatx80_l2e;
floatx80 l2e = { 0xb8aa3b295c17f0bcLL, 0x3fff }; floatx80 l2e = { 0xb8aa3b295c17f0bcLL, 0x3fff };
ST0 = l2e; ST0 = l2e;
} }
void helper_fldpi_ST0(CPUX86State *env) void helper_fldpi_ST0(CPUX86State *env)
{ {
//ST0 = floatx80_pi; //ST0 = floatx80_pi;
floatx80 pi = { 0xc90fdaa22168c235LL, 0x4000 }; floatx80 pi = { 0xc90fdaa22168c235LL, 0x4000 };
ST0 = pi; ST0 = pi;
} }
void helper_fldlg2_ST0(CPUX86State *env) void helper_fldlg2_ST0(CPUX86State *env)
{ {
//ST0 = floatx80_lg2; //ST0 = floatx80_lg2;
floatx80 lg2 = { 0x9a209a84fbcff799LL, 0x3ffd }; floatx80 lg2 = { 0x9a209a84fbcff799LL, 0x3ffd };
ST0 = lg2; ST0 = lg2;
} }
void helper_fldln2_ST0(CPUX86State *env) void helper_fldln2_ST0(CPUX86State *env)
{ {
//ST0 = floatx80_ln2; //ST0 = floatx80_ln2;
floatx80 ln2 = { 0xb17217f7d1cf79acLL, 0x3ffe }; floatx80 ln2 = { 0xb17217f7d1cf79acLL, 0x3ffe };
ST0 = ln2; ST0 = ln2;
} }
void helper_fldz_ST0(CPUX86State *env) void helper_fldz_ST0(CPUX86State *env)
{ {
//ST0 = floatx80_zero; //ST0 = floatx80_zero;
floatx80 zero = { 0x0000000000000000LL, 0x0000 }; floatx80 zero = { 0x0000000000000000LL, 0x0000 };
ST0 = zero; ST0 = zero;
} }
void helper_fldz_FT0(CPUX86State *env) void helper_fldz_FT0(CPUX86State *env)
{ {
//FT0 = floatx80_zero; //FT0 = floatx80_zero;
floatx80 zero = { 0x0000000000000000LL, 0x0000 }; floatx80 zero = { 0x0000000000000000LL, 0x0000 };
ST0 = zero; ST0 = zero;
} }
@ -702,8 +702,8 @@ void helper_fptan(CPUX86State *env)
if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) { if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
env->fpus |= 0x400; env->fpus |= 0x400;
} else { } else {
floatx80 one = { 0x8000000000000000LL, 0x3fff }; floatx80 one = { 0x8000000000000000LL, 0x3fff };
fptemp = tan(fptemp); fptemp = tan(fptemp);
ST0 = double_to_floatx80(env, fptemp); ST0 = double_to_floatx80(env, fptemp);
fpush(env); fpush(env);
ST0 = one; ST0 = one;
@ -730,8 +730,8 @@ void helper_fxtract(CPUX86State *env)
if (floatx80_is_zero(ST0)) { if (floatx80_is_zero(ST0)) {
/* Easy way to generate -inf and raising division by 0 exception */ /* Easy way to generate -inf and raising division by 0 exception */
floatx80 zero = { 0x0000000000000000LL, 0x0000 }; floatx80 zero = { 0x0000000000000000LL, 0x0000 };
floatx80 one = { 0x8000000000000000LL, 0x3fff }; floatx80 one = { 0x8000000000000000LL, 0x3fff };
ST0 = floatx80_div(floatx80_chs(one), zero, ST0 = floatx80_div(floatx80_chs(one), zero,
&env->fp_status); &env->fp_status);
fpush(env); fpush(env);
@ -760,7 +760,7 @@ void helper_fprem1(CPUX86State *env)
if (isinf(st0) || isnan(st0) || isnan(st1) || (st1 == 0.0)) { if (isinf(st0) || isnan(st0) || isnan(st1) || (st1 == 0.0)) {
ST0 = double_to_floatx80(env, NAN); /* NaN */ ST0 = double_to_floatx80(env, NAN); /* NaN */
env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */ env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
return; return;
} }

154
qemu/target-i386/svm.h
View file

@ -131,92 +131,92 @@
#define SVM_CR0_SELECTIVE_MASK (1 << 3 | 1) /* TS and MP */ #define SVM_CR0_SELECTIVE_MASK (1 << 3 | 1) /* TS and MP */
QEMU_PACK( struct vmcb_control_area { QEMU_PACK( struct vmcb_control_area {
uint16_t intercept_cr_read; uint16_t intercept_cr_read;
uint16_t intercept_cr_write; uint16_t intercept_cr_write;
uint16_t intercept_dr_read; uint16_t intercept_dr_read;
uint16_t intercept_dr_write; uint16_t intercept_dr_write;
uint32_t intercept_exceptions; uint32_t intercept_exceptions;
uint64_t intercept; uint64_t intercept;
uint8_t reserved_1[44]; uint8_t reserved_1[44];
uint64_t iopm_base_pa; uint64_t iopm_base_pa;
uint64_t msrpm_base_pa; uint64_t msrpm_base_pa;
uint64_t tsc_offset; uint64_t tsc_offset;
uint32_t asid; uint32_t asid;
uint8_t tlb_ctl; uint8_t tlb_ctl;
uint8_t reserved_2[3]; uint8_t reserved_2[3];
uint32_t int_ctl; uint32_t int_ctl;
uint32_t int_vector; uint32_t int_vector;
uint32_t int_state; uint32_t int_state;
uint8_t reserved_3[4]; uint8_t reserved_3[4];
uint64_t exit_code; uint64_t exit_code;
uint64_t exit_info_1; uint64_t exit_info_1;
uint64_t exit_info_2; uint64_t exit_info_2;
uint32_t exit_int_info; uint32_t exit_int_info;
uint32_t exit_int_info_err; uint32_t exit_int_info_err;
uint64_t nested_ctl; uint64_t nested_ctl;
uint8_t reserved_4[16]; uint8_t reserved_4[16];
uint32_t event_inj; uint32_t event_inj;
uint32_t event_inj_err; uint32_t event_inj_err;
uint64_t nested_cr3; uint64_t nested_cr3;
uint64_t lbr_ctl; uint64_t lbr_ctl;
uint8_t reserved_5[832]; uint8_t reserved_5[832];
}); });
QEMU_PACK( struct vmcb_seg { QEMU_PACK( struct vmcb_seg {
uint16_t selector; uint16_t selector;
uint16_t attrib; uint16_t attrib;
uint32_t limit; uint32_t limit;
uint64_t base; uint64_t base;
}); });
QEMU_PACK( struct vmcb_save_area { QEMU_PACK( struct vmcb_save_area {
struct vmcb_seg es; struct vmcb_seg es;
struct vmcb_seg cs; struct vmcb_seg cs;
struct vmcb_seg ss; struct vmcb_seg ss;
struct vmcb_seg ds; struct vmcb_seg ds;
struct vmcb_seg fs; struct vmcb_seg fs;
struct vmcb_seg gs; struct vmcb_seg gs;
struct vmcb_seg gdtr; struct vmcb_seg gdtr;
struct vmcb_seg ldtr; struct vmcb_seg ldtr;
struct vmcb_seg idtr; struct vmcb_seg idtr;
struct vmcb_seg tr; struct vmcb_seg tr;
uint8_t reserved_1[43]; uint8_t reserved_1[43];
uint8_t cpl; uint8_t cpl;
uint8_t reserved_2[4]; uint8_t reserved_2[4];
uint64_t efer; uint64_t efer;
uint8_t reserved_3[112]; uint8_t reserved_3[112];
uint64_t cr4; uint64_t cr4;
uint64_t cr3; uint64_t cr3;
uint64_t cr0; uint64_t cr0;
uint64_t dr7; uint64_t dr7;
uint64_t dr6; uint64_t dr6;
uint64_t rflags; uint64_t rflags;
uint64_t rip; uint64_t rip;
uint8_t reserved_4[88]; uint8_t reserved_4[88];
uint64_t rsp; uint64_t rsp;
uint8_t reserved_5[24]; uint8_t reserved_5[24];
uint64_t rax; uint64_t rax;
uint64_t star; uint64_t star;
uint64_t lstar; uint64_t lstar;
uint64_t cstar; uint64_t cstar;
uint64_t sfmask; uint64_t sfmask;
uint64_t kernel_gs_base; uint64_t kernel_gs_base;
uint64_t sysenter_cs; uint64_t sysenter_cs;
uint64_t sysenter_esp; uint64_t sysenter_esp;
uint64_t sysenter_eip; uint64_t sysenter_eip;
uint64_t cr2; uint64_t cr2;
uint8_t reserved_6[32]; uint8_t reserved_6[32];
uint64_t g_pat; uint64_t g_pat;
uint64_t dbgctl; uint64_t dbgctl;
uint64_t br_from; uint64_t br_from;
uint64_t br_to; uint64_t br_to;
uint64_t last_excp_from; uint64_t last_excp_from;
uint64_t last_excp_to; uint64_t last_excp_to;
}); });
QEMU_PACK( struct vmcb { QEMU_PACK( struct vmcb {
struct vmcb_control_area control; struct vmcb_control_area control;
struct vmcb_save_area save; struct vmcb_save_area save;
}); });
#endif #endif

20
qemu/target-i386/svm_helper.c
View file

@ -490,23 +490,23 @@ void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,
if (env->intercept_cr_read & (1 << (type - SVM_EXIT_READ_CR0))) { if (env->intercept_cr_read & (1 << (type - SVM_EXIT_READ_CR0))) {
helper_vmexit(env, type, param); helper_vmexit(env, type, param);
} }
} else if( type >= SVM_EXIT_WRITE_CR0 && type <= SVM_EXIT_WRITE_CR0 + 8 ) { } else if( type >= SVM_EXIT_WRITE_CR0 && type <= SVM_EXIT_WRITE_CR0 + 8 ) {
if (env->intercept_cr_write & (1 << (type - SVM_EXIT_WRITE_CR0))) { if (env->intercept_cr_write & (1 << (type - SVM_EXIT_WRITE_CR0))) {
helper_vmexit(env, type, param); helper_vmexit(env, type, param);
} }
} else if( type >= SVM_EXIT_READ_DR0 && type <= SVM_EXIT_READ_DR0 + 7 ) { } else if( type >= SVM_EXIT_READ_DR0 && type <= SVM_EXIT_READ_DR0 + 7 ) {
if (env->intercept_dr_read & (1 << (type - SVM_EXIT_READ_DR0))) { if (env->intercept_dr_read & (1 << (type - SVM_EXIT_READ_DR0))) {
helper_vmexit(env, type, param); helper_vmexit(env, type, param);
} }
} else if( type >= SVM_EXIT_WRITE_DR0 && type <= SVM_EXIT_WRITE_DR0 + 7 ) { } else if( type >= SVM_EXIT_WRITE_DR0 && type <= SVM_EXIT_WRITE_DR0 + 7 ) {
if (env->intercept_dr_write & (1 << (type - SVM_EXIT_WRITE_DR0))) { if (env->intercept_dr_write & (1 << (type - SVM_EXIT_WRITE_DR0))) {
helper_vmexit(env, type, param); helper_vmexit(env, type, param);
} }
} else if( type >= SVM_EXIT_EXCP_BASE && type <= SVM_EXIT_EXCP_BASE + 31 ) { } else if( type >= SVM_EXIT_EXCP_BASE && type <= SVM_EXIT_EXCP_BASE + 31 ) {
if (env->intercept_exceptions & (1 << (type - SVM_EXIT_EXCP_BASE))) { if (env->intercept_exceptions & (1 << (type - SVM_EXIT_EXCP_BASE))) {
helper_vmexit(env, type, param); helper_vmexit(env, type, param);
} }
} else if( type == SVM_EXIT_MSR ) { } else if( type == SVM_EXIT_MSR ) {
if (env->intercept & (1ULL << (SVM_EXIT_MSR - SVM_EXIT_INTR))) { if (env->intercept & (1ULL << (SVM_EXIT_MSR - SVM_EXIT_INTR))) {
/* FIXME: this should be read in at vmrun (faster this way?) */ /* FIXME: this should be read in at vmrun (faster this way?) */
uint64_t addr = ldq_phys(cs->as, env->vm_vmcb + uint64_t addr = ldq_phys(cs->as, env->vm_vmcb +
@ -515,10 +515,10 @@ void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,
uint32_t t0, t1; uint32_t t0, t1;
uint32_t ecx = (uint32_t)env->regs[R_ECX]; uint32_t ecx = (uint32_t)env->regs[R_ECX];
if( (int32_t)ecx >= 0 && ecx <= 0x1fff ) { if( (int32_t)ecx >= 0 && ecx <= 0x1fff ) {
t0 = (env->regs[R_ECX] * 2) % 8; t0 = (env->regs[R_ECX] * 2) % 8;
t1 = (env->regs[R_ECX] * 2) / 8; t1 = (env->regs[R_ECX] * 2) / 8;
} else if( ecx >= 0xc0000000 && ecx <= 0xc0001fff ) { } else if( ecx >= 0xc0000000 && ecx <= 0xc0001fff ) {
t0 = (8192 + env->regs[R_ECX] - 0xc0000000) * 2; t0 = (8192 + env->regs[R_ECX] - 0xc0000000) * 2;
t1 = (t0 / 8); t1 = (t0 / 8);
t0 %= 8; t0 %= 8;
@ -526,7 +526,7 @@ void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,
t0 = (16384 + env->regs[R_ECX] - 0xc0010000) * 2; t0 = (16384 + env->regs[R_ECX] - 0xc0010000) * 2;
t1 = (t0 / 8); t1 = (t0 / 8);
t0 %= 8; t0 %= 8;
} else { } else {
helper_vmexit(env, type, param); helper_vmexit(env, type, param);
t0 = 0; t0 = 0;
t1 = 0; t1 = 0;
@ -535,11 +535,11 @@ void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type,
helper_vmexit(env, type, param); helper_vmexit(env, type, param);
} }
} }
} else { } else {
if (env->intercept & (1ULL << (type - SVM_EXIT_INTR))) { if (env->intercept & (1ULL << (type - SVM_EXIT_INTR))) {
helper_vmexit(env, type, param); helper_vmexit(env, type, param);
} }
} }
} }
void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type, void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type,

746
qemu/target-i386/translate.c
View file

File diff suppressed because it is too large Load diff

168
qemu/target-i386/unicorn.c
View file

@ -150,14 +150,14 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
switch(regid) { switch(regid) {
default: default:
break; break;
case UC_X86_REG_FP0: case UC_X86_REG_FP0:
case UC_X86_REG_FP1: case UC_X86_REG_FP1:
case UC_X86_REG_FP2: case UC_X86_REG_FP2:
case UC_X86_REG_FP3: case UC_X86_REG_FP3:
case UC_X86_REG_FP4: case UC_X86_REG_FP4:
case UC_X86_REG_FP5: case UC_X86_REG_FP5:
case UC_X86_REG_FP6: case UC_X86_REG_FP6:
case UC_X86_REG_FP7: case UC_X86_REG_FP7:
{ {
floatx80 reg = X86_CPU(uc, mycpu)->env.fpregs[regid - UC_X86_REG_FP0].d; floatx80 reg = X86_CPU(uc, mycpu)->env.fpregs[regid - UC_X86_REG_FP0].d;
cpu_get_fp80(value, (uint16_t*)((char*)value+sizeof(uint64_t)), reg); cpu_get_fp80(value, (uint16_t*)((char*)value+sizeof(uint64_t)), reg);
@ -204,14 +204,14 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
*(uint16_t*) value = fptag; *(uint16_t*) value = fptag;
} }
continue; continue;
case UC_X86_REG_XMM0: case UC_X86_REG_XMM0:
case UC_X86_REG_XMM1: case UC_X86_REG_XMM1:
case UC_X86_REG_XMM2: case UC_X86_REG_XMM2:
case UC_X86_REG_XMM3: case UC_X86_REG_XMM3:
case UC_X86_REG_XMM4: case UC_X86_REG_XMM4:
case UC_X86_REG_XMM5: case UC_X86_REG_XMM5:
case UC_X86_REG_XMM6: case UC_X86_REG_XMM6:
case UC_X86_REG_XMM7: case UC_X86_REG_XMM7:
{ {
float64 *dst = (float64*)value; float64 *dst = (float64*)value;
XMMReg *reg = &X86_CPU(uc, mycpu)->env.xmm_regs[regid - UC_X86_REG_XMM0]; XMMReg *reg = &X86_CPU(uc, mycpu)->env.xmm_regs[regid - UC_X86_REG_XMM0];
@ -248,21 +248,21 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
switch(regid) { switch(regid) {
default: default:
break; break;
case UC_X86_REG_CR0: case UC_X86_REG_CR0:
case UC_X86_REG_CR1: case UC_X86_REG_CR1:
case UC_X86_REG_CR2: case UC_X86_REG_CR2:
case UC_X86_REG_CR3: case UC_X86_REG_CR3:
case UC_X86_REG_CR4: case UC_X86_REG_CR4:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0]; *(int32_t *)value = X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0];
break; break;
case UC_X86_REG_DR0: case UC_X86_REG_DR0:
case UC_X86_REG_DR1: case UC_X86_REG_DR1:
case UC_X86_REG_DR2: case UC_X86_REG_DR2:
case UC_X86_REG_DR3: case UC_X86_REG_DR3:
case UC_X86_REG_DR4: case UC_X86_REG_DR4:
case UC_X86_REG_DR5: case UC_X86_REG_DR5:
case UC_X86_REG_DR6: case UC_X86_REG_DR6:
case UC_X86_REG_DR7: case UC_X86_REG_DR7:
*(int32_t *)value = X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0]; *(int32_t *)value = X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0];
break; break;
case UC_X86_REG_EFLAGS: case UC_X86_REG_EFLAGS:
@ -392,21 +392,21 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun
switch(regid) { switch(regid) {
default: default:
break; break;
case UC_X86_REG_CR0: case UC_X86_REG_CR0:
case UC_X86_REG_CR1: case UC_X86_REG_CR1:
case UC_X86_REG_CR2: case UC_X86_REG_CR2:
case UC_X86_REG_CR3: case UC_X86_REG_CR3:
case UC_X86_REG_CR4: case UC_X86_REG_CR4:
*(int64_t *)value = X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0]; *(int64_t *)value = X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0];
break; break;
case UC_X86_REG_DR0: case UC_X86_REG_DR0:
case UC_X86_REG_DR1: case UC_X86_REG_DR1:
case UC_X86_REG_DR2: case UC_X86_REG_DR2:
case UC_X86_REG_DR3: case UC_X86_REG_DR3:
case UC_X86_REG_DR4: case UC_X86_REG_DR4:
case UC_X86_REG_DR5: case UC_X86_REG_DR5:
case UC_X86_REG_DR6: case UC_X86_REG_DR6:
case UC_X86_REG_DR7: case UC_X86_REG_DR7:
*(int64_t *)value = X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0]; *(int64_t *)value = X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0];
break; break;
case UC_X86_REG_EFLAGS: case UC_X86_REG_EFLAGS:
@ -683,14 +683,14 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i
switch(regid) { switch(regid) {
default: default:
break; break;
case UC_X86_REG_FP0: case UC_X86_REG_FP0:
case UC_X86_REG_FP1: case UC_X86_REG_FP1:
case UC_X86_REG_FP2: case UC_X86_REG_FP2:
case UC_X86_REG_FP3: case UC_X86_REG_FP3:
case UC_X86_REG_FP4: case UC_X86_REG_FP4:
case UC_X86_REG_FP5: case UC_X86_REG_FP5:
case UC_X86_REG_FP6: case UC_X86_REG_FP6:
case UC_X86_REG_FP7: case UC_X86_REG_FP7:
{ {
uint64_t mant = *(uint64_t*) value; uint64_t mant = *(uint64_t*) value;
uint16_t upper = *(uint16_t*) ((char*)value + sizeof(uint64_t)); uint16_t upper = *(uint16_t*) ((char*)value + sizeof(uint64_t));
@ -719,14 +719,14 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i
continue; continue;
} }
break; break;
case UC_X86_REG_XMM0: case UC_X86_REG_XMM0:
case UC_X86_REG_XMM1: case UC_X86_REG_XMM1:
case UC_X86_REG_XMM2: case UC_X86_REG_XMM2:
case UC_X86_REG_XMM3: case UC_X86_REG_XMM3:
case UC_X86_REG_XMM4: case UC_X86_REG_XMM4:
case UC_X86_REG_XMM5: case UC_X86_REG_XMM5:
case UC_X86_REG_XMM6: case UC_X86_REG_XMM6:
case UC_X86_REG_XMM7: case UC_X86_REG_XMM7:
{ {
float64 *src = (float64*)value; float64 *src = (float64*)value;
XMMReg *reg = &X86_CPU(uc, mycpu)->env.xmm_regs[regid - UC_X86_REG_XMM0]; XMMReg *reg = &X86_CPU(uc, mycpu)->env.xmm_regs[regid - UC_X86_REG_XMM0];
@ -764,21 +764,21 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i
switch(regid) { switch(regid) {
default: default:
break; break;
case UC_X86_REG_CR0: case UC_X86_REG_CR0:
case UC_X86_REG_CR1: case UC_X86_REG_CR1:
case UC_X86_REG_CR2: case UC_X86_REG_CR2:
case UC_X86_REG_CR3: case UC_X86_REG_CR3:
case UC_X86_REG_CR4: case UC_X86_REG_CR4:
X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0] = *(uint32_t *)value; X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0] = *(uint32_t *)value;
break; break;
case UC_X86_REG_DR0: case UC_X86_REG_DR0:
case UC_X86_REG_DR1: case UC_X86_REG_DR1:
case UC_X86_REG_DR2: case UC_X86_REG_DR2:
case UC_X86_REG_DR3: case UC_X86_REG_DR3:
case UC_X86_REG_DR4: case UC_X86_REG_DR4:
case UC_X86_REG_DR5: case UC_X86_REG_DR5:
case UC_X86_REG_DR6: case UC_X86_REG_DR6:
case UC_X86_REG_DR7: case UC_X86_REG_DR7:
X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0] = *(uint32_t *)value; X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0] = *(uint32_t *)value;
break; break;
case UC_X86_REG_EFLAGS: case UC_X86_REG_EFLAGS:
@ -915,21 +915,21 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i
switch(regid) { switch(regid) {
default: default:
break; break;
case UC_X86_REG_CR0: case UC_X86_REG_CR0:
case UC_X86_REG_CR1: case UC_X86_REG_CR1:
case UC_X86_REG_CR2: case UC_X86_REG_CR2:
case UC_X86_REG_CR3: case UC_X86_REG_CR3:
case UC_X86_REG_CR4: case UC_X86_REG_CR4:
X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0] = *(uint64_t *)value; X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0] = *(uint64_t *)value;
break; break;
case UC_X86_REG_DR0: case UC_X86_REG_DR0:
case UC_X86_REG_DR1: case UC_X86_REG_DR1:
case UC_X86_REG_DR2: case UC_X86_REG_DR2:
case UC_X86_REG_DR3: case UC_X86_REG_DR3:
case UC_X86_REG_DR4: case UC_X86_REG_DR4:
case UC_X86_REG_DR5: case UC_X86_REG_DR5:
case UC_X86_REG_DR6: case UC_X86_REG_DR6:
case UC_X86_REG_DR7: case UC_X86_REG_DR7:
X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0] = *(uint64_t *)value; X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0] = *(uint64_t *)value;
break; break;
case UC_X86_REG_EFLAGS: case UC_X86_REG_EFLAGS:

2
qemu/target-mips/cpu.h
View file

@ -763,7 +763,7 @@ int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra); void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra);
hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address, hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address,
int rw); int rw);
#endif #endif
target_ulong exception_resume_pc (CPUMIPSState *env); target_ulong exception_resume_pc (CPUMIPSState *env);

180
qemu/tcg/i386/tcg-target.c
View file

@ -78,12 +78,12 @@ static const int tcg_target_call_iarg_regs[] = {
TCG_REG_R9, TCG_REG_R9,
#else #else
/* 32 bit mode uses stack based calling convention (GCC default). /* 32 bit mode uses stack based calling convention (GCC default).
We add a dummy value here for MSVC compatibility for the error: We add a dummy value here for MSVC compatibility for the error:
"error C2466: cannot allocate an array of constant size 0" "error C2466: cannot allocate an array of constant size 0"
The "tcg_target_call_iarg_regs" array is not accessed when The "tcg_target_call_iarg_regs" array is not accessed when
TCG_TARGET_REG_BITS == 32 TCG_TARGET_REG_BITS == 32
*/ */
0, 0,
#endif #endif
}; };
@ -411,24 +411,24 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
static const uint8_t tcg_cond_to_jcc[] = { static const uint8_t tcg_cond_to_jcc[] = {
#ifdef _MSC_VER #ifdef _MSC_VER
0, // TCG_COND_NEVER 0, // TCG_COND_NEVER
0, // TCG_COND_ALWAYS 0, // TCG_COND_ALWAYS
JCC_JL, // TCG_COND_LT JCC_JL, // TCG_COND_LT
JCC_JGE, // TCG_COND_GE JCC_JGE, // TCG_COND_GE
JCC_JB, // TCG_COND_LTU JCC_JB, // TCG_COND_LTU
JCC_JAE, // TCG_COND_GEU JCC_JAE, // TCG_COND_GEU
0, // n/a 0, // n/a
0, // n/a 0, // n/a
JCC_JE, // TCG_COND_EQ JCC_JE, // TCG_COND_EQ
JCC_JNE, // TCG_COND_NE JCC_JNE, // TCG_COND_NE
JCC_JLE, // TCG_COND_LE JCC_JLE, // TCG_COND_LE
JCC_JG, // TCG_COND_GT JCC_JG, // TCG_COND_GT
JCC_JBE, // TCG_COND_LEU JCC_JBE, // TCG_COND_LEU
JCC_JA, // TCG_COND_GTU JCC_JA, // TCG_COND_GTU
0, // n/a 0, // n/a
0, // n/a 0, // n/a
#else #else
[TCG_COND_EQ] = JCC_JE, [TCG_COND_EQ] = JCC_JE,
[TCG_COND_NE] = JCC_JNE, [TCG_COND_NE] = JCC_JNE,
[TCG_COND_LT] = JCC_JL, [TCG_COND_LT] = JCC_JL,
[TCG_COND_GE] = JCC_JGE, [TCG_COND_GE] = JCC_JGE,
@ -1155,43 +1155,43 @@ static void tcg_out_jmp(TCGContext *s, tcg_insn_unit *dest)
*/ */
static void * const qemu_ld_helpers[16] = { static void * const qemu_ld_helpers[16] = {
#ifdef _MSC_VER #ifdef _MSC_VER
helper_ret_ldub_mmu, // MO_UB helper_ret_ldub_mmu, // MO_UB
# ifdef HOST_WORDS_BIGENDIAN # ifdef HOST_WORDS_BIGENDIAN
helper_be_lduw_mmu, // MO_BEUW helper_be_lduw_mmu, // MO_BEUW
helper_be_ldul_mmu, // MO_BEUL helper_be_ldul_mmu, // MO_BEUL
helper_be_ldq_mmu, // MO_BEQ helper_be_ldq_mmu, // MO_BEQ
0, // MO_SB 0, // MO_SB
0, // MO_BESW 0, // MO_BESW
0, // MO_BESL 0, // MO_BESL
0, // n/a 0, // n/a
0, // n/a 0, // n/a
helper_le_lduw_mmu, // MO_LEUW helper_le_lduw_mmu, // MO_LEUW
helper_le_ldul_mmu, // MO_LEUL helper_le_ldul_mmu, // MO_LEUL
helper_le_ldq_mmu, // MO_LEQ helper_le_ldq_mmu, // MO_LEQ
0, // n/a 0, // n/a
0, // MO_LESW 0, // MO_LESW
0, // MO_LESL 0, // MO_LESL
0, // n/a 0, // n/a
# else // !HOST_WORDS_BIGENDIAN # else // !HOST_WORDS_BIGENDIAN
helper_le_lduw_mmu, // MO_LEUW helper_le_lduw_mmu, // MO_LEUW
helper_le_ldul_mmu, // MO_LEUL helper_le_ldul_mmu, // MO_LEUL
helper_le_ldq_mmu, // MO_LEQ helper_le_ldq_mmu, // MO_LEQ
0, // MO_SB 0, // MO_SB
0, // MO_LESW 0, // MO_LESW
0, // MO_LESL 0, // MO_LESL
0, // n/a 0, // n/a
0, // n/a 0, // n/a
helper_be_lduw_mmu, // MO_BEUW helper_be_lduw_mmu, // MO_BEUW
helper_be_ldul_mmu, // MO_BEUL helper_be_ldul_mmu, // MO_BEUL
helper_be_ldq_mmu, // MO_BEQ helper_be_ldq_mmu, // MO_BEQ
0, // n/a 0, // n/a
0, // MO_BESW 0, // MO_BESW
0, // MO_BESL 0, // MO_BESL
0, // n/a 0, // n/a
# endif // HOST_WORDS_BIGENDIAN # endif // HOST_WORDS_BIGENDIAN
#else //_MSC_VER #else //_MSC_VER
[MO_UB] = helper_ret_ldub_mmu, [MO_UB] = helper_ret_ldub_mmu,
[MO_LEUW] = helper_le_lduw_mmu, [MO_LEUW] = helper_le_lduw_mmu,
[MO_LEUL] = helper_le_ldul_mmu, [MO_LEUL] = helper_le_ldul_mmu,
[MO_LEQ] = helper_le_ldq_mmu, [MO_LEQ] = helper_le_ldq_mmu,
@ -1206,39 +1206,39 @@ static void * const qemu_ld_helpers[16] = {
*/ */
static void * const qemu_st_helpers[16] = { static void * const qemu_st_helpers[16] = {
#ifdef _MSC_VER #ifdef _MSC_VER
helper_ret_stb_mmu, // MO_UB helper_ret_stb_mmu, // MO_UB
# ifdef HOST_WORDS_BIGENDIAN # ifdef HOST_WORDS_BIGENDIAN
helper_be_stw_mmu, // MO_BEUW helper_be_stw_mmu, // MO_BEUW
helper_be_stl_mmu, // MO_BEUL helper_be_stl_mmu, // MO_BEUL
helper_be_stq_mmu, // MO_BEQ helper_be_stq_mmu, // MO_BEQ
0, // MO_SB 0, // MO_SB
0, // MO_BESW 0, // MO_BESW
0, // MO_BESL 0, // MO_BESL
0, // n/a 0, // n/a
0, // n/a 0, // n/a
helper_le_stw_mmu, // MO_LEUW helper_le_stw_mmu, // MO_LEUW
helper_le_stl_mmu, // MO_LEUL helper_le_stl_mmu, // MO_LEUL
helper_le_stq_mmu, // MO_LEQ helper_le_stq_mmu, // MO_LEQ
0, // n/a 0, // n/a
0, // MO_LESW 0, // MO_LESW
0, // MO_LESL 0, // MO_LESL
0, // n/a 0, // n/a
# else // !HOST_WORDS_BIGENDIAN # else // !HOST_WORDS_BIGENDIAN
helper_le_stw_mmu, // MO_LEUW helper_le_stw_mmu, // MO_LEUW
helper_le_stl_mmu, // MO_LEUL helper_le_stl_mmu, // MO_LEUL
helper_le_stq_mmu, // MO_LEQ helper_le_stq_mmu, // MO_LEQ
0, // MO_SB 0, // MO_SB
0, // MO_LESW 0, // MO_LESW
0, // MO_LESL 0, // MO_LESL
0, // n/a 0, // n/a
0, // n/a 0, // n/a
helper_be_stw_mmu, // MO_BEUW helper_be_stw_mmu, // MO_BEUW
helper_be_stl_mmu, // MO_BEUL helper_be_stl_mmu, // MO_BEUL
helper_be_stq_mmu, // MO_BEQ helper_be_stq_mmu, // MO_BEQ
0, // n/a 0, // n/a
0, // MO_BESW 0, // MO_BESW
0, // MO_BESL 0, // MO_BESL
0, // n/a 0, // n/a
# endif // HOST_WORDS_BIGENDIAN # endif // HOST_WORDS_BIGENDIAN
#else //_MSC_VER #else //_MSC_VER
@ -2356,8 +2356,8 @@ static void tcg_target_qemu_prologue(TCGContext *s)
tcg_out_addi(s, TCG_REG_ESP, -stack_addend); tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
/* jmp *tb. */ /* jmp *tb. */
tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP, tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP,
(ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4 (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4
+ stack_addend); + stack_addend);
#else #else
tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
tcg_out_addi(s, TCG_REG_ESP, -stack_addend); tcg_out_addi(s, TCG_REG_ESP, -stack_addend);
@ -2387,12 +2387,12 @@ static void tcg_target_init(TCGContext *s)
{ {
#ifdef CONFIG_CPUID_H #ifdef CONFIG_CPUID_H
unsigned a, b, c, d; unsigned a, b, c, d;
int max; int max;
#ifdef _MSC_VER #ifdef _MSC_VER
int cpu_info[4]; int cpu_info[4];
__cpuid(cpu_info, 0); __cpuid(cpu_info, 0);
max = cpu_info[0]; max = cpu_info[0];
#else #else
max = __get_cpuid_max(0, 0); max = __get_cpuid_max(0, 0);
#endif #endif

30
qemu/tcg/sparc/tcg-target.c
View file

@ -405,7 +405,7 @@ static inline void tcg_out_arithi(TCGContext *s, TCGReg rd, TCGReg rs1,
} }
static void tcg_out_arithc(TCGContext *s, TCGReg rd, TCGReg rs1, static void tcg_out_arithc(TCGContext *s, TCGReg rd, TCGReg rs1,
int32_t val2, int val2const, int op) int32_t val2, int val2const, int op)
{ {
tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1)
| (val2const ? INSN_IMM13(val2) : INSN_RS2(val2))); | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2)));
@ -682,7 +682,7 @@ static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret,
} }
c1 = TCG_REG_G0, c2const = 0; c1 = TCG_REG_G0, c2const = 0;
cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU); cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU);
break; break;
case TCG_COND_GTU: case TCG_COND_GTU:
case TCG_COND_LEU: case TCG_COND_LEU:
@ -783,16 +783,16 @@ static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh,
} }
tcg_out_arith(s, rh, ah, bh, ARITH_ADDXC); tcg_out_arith(s, rh, ah, bh, ARITH_ADDXC);
} else if (bh == TCG_REG_G0) { } else if (bh == TCG_REG_G0) {
/* If we have a zero, we can perform the operation in two insns, /* If we have a zero, we can perform the operation in two insns,
with the arithmetic first, and a conditional move into place. */ with the arithmetic first, and a conditional move into place. */
if (rh == ah) { if (rh == ah) {
tcg_out_arithi(s, TCG_REG_T2, ah, 1, tcg_out_arithi(s, TCG_REG_T2, ah, 1,
is_sub ? ARITH_SUB : ARITH_ADD); is_sub ? ARITH_SUB : ARITH_ADD);
tcg_out_movcc(s, TCG_COND_LTU, MOVCC_XCC, rh, TCG_REG_T2, 0); tcg_out_movcc(s, TCG_COND_LTU, MOVCC_XCC, rh, TCG_REG_T2, 0);
} else { } else {
tcg_out_arithi(s, rh, ah, 1, is_sub ? ARITH_SUB : ARITH_ADD); tcg_out_arithi(s, rh, ah, 1, is_sub ? ARITH_SUB : ARITH_ADD);
tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, rh, ah, 0); tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, rh, ah, 0);
} }
} else { } else {
/* Otherwise adjust BH as if there is carry into T2 ... */ /* Otherwise adjust BH as if there is carry into T2 ... */
if (bhconst) { if (bhconst) {
@ -803,7 +803,7 @@ static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh,
} }
/* ... smoosh T2 back to original BH if carry is clear ... */ /* ... smoosh T2 back to original BH if carry is clear ... */
tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, TCG_REG_T2, bh, bhconst); tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, TCG_REG_T2, bh, bhconst);
/* ... and finally perform the arithmetic with the new operand. */ /* ... and finally perform the arithmetic with the new operand. */
tcg_out_arith(s, rh, ah, TCG_REG_T2, is_sub ? ARITH_SUB : ARITH_ADD); tcg_out_arith(s, rh, ah, TCG_REG_T2, is_sub ? ARITH_SUB : ARITH_ADD);
} }
@ -1315,11 +1315,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
goto gen_arith; goto gen_arith;
OP_32_64(neg): OP_32_64(neg):
c = ARITH_SUB; c = ARITH_SUB;
goto gen_arith1; goto gen_arith1;
OP_32_64(not): OP_32_64(not):
c = ARITH_ORN; c = ARITH_ORN;
goto gen_arith1; goto gen_arith1;
case INDEX_op_div_i32: case INDEX_op_div_i32:
tcg_out_div32(s, a0, a1, a2, c2, 0); tcg_out_div32(s, a0, a1, a2, c2, 0);
@ -1445,8 +1445,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
break; break;
gen_arith1: gen_arith1:
tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c); tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c);
break; break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_mov_i64: case INDEX_op_mov_i64:

4
qemu/tcg/sparc/tcg-target.h
View file

@ -152,12 +152,12 @@ extern bool use_vis3_instructions;
#include <windows.h> #include <windows.h>
static inline void flush_icache_range(uintptr_t start, uintptr_t stop) static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
{ {
FlushInstructionCache(GetCurrentProcess(), (const void*)start, stop-start); FlushInstructionCache(GetCurrentProcess(), (const void*)start, stop-start);
} }
#else #else
static inline void flush_icache_range(uintptr_t start, uintptr_t stop) static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
{ {
uintptr_t p; uintptr_t p;
for (p = start & -8; p < ((stop + 7) & -8); p += 8) { for (p = start & -8; p < ((stop + 7) & -8); p += 8) {
__asm__ __volatile__("flush\t%0" : : "r" (p)); __asm__ __volatile__("flush\t%0" : : "r" (p));
} }

106
qemu/tcg/tcg.c
View file

@ -70,7 +70,7 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int type,
/* The CIE and FDE header definitions will be common to all hosts. */ /* The CIE and FDE header definitions will be common to all hosts. */
typedef struct { typedef struct {
//uint32_t QEMU_ALIGN(sizeof(void *), len); //uint32_t QEMU_ALIGN(sizeof(void *), len);
uint32_t QEMU_ALIGN(8, len); uint32_t QEMU_ALIGN(8, len);
uint32_t id; uint32_t id;
uint8_t version; uint8_t version;
char augmentation[1]; char augmentation[1];
@ -81,7 +81,7 @@ typedef struct {
QEMU_PACK( typedef struct { QEMU_PACK( typedef struct {
// uint32_t QEMU_ALIGN(sizeof(void *), len); // uint32_t QEMU_ALIGN(sizeof(void *), len);
uint32_t QEMU_ALIGN(8, len); uint32_t QEMU_ALIGN(8, len);
uint32_t cie_offset; uint32_t cie_offset;
uintptr_t func_start; uintptr_t func_start;
uintptr_t func_len; uintptr_t func_len;
@ -1100,22 +1100,22 @@ static inline const char *tcg_find_helper(TCGContext *s, uintptr_t val)
static const char * const cond_name[] = static const char * const cond_name[] =
{ {
#ifdef _MSC_VER #ifdef _MSC_VER
"never", // TCG_COND_NEVER "never", // TCG_COND_NEVER
"always", // TCG_COND_ALWAYS "always", // TCG_COND_ALWAYS
"lt", // TCG_COND_LT "lt", // TCG_COND_LT
"ge", // TCG_COND_GE "ge", // TCG_COND_GE
"ltu", // TCG_COND_LTU "ltu", // TCG_COND_LTU
"geu", // TCG_COND_GEU "geu", // TCG_COND_GEU
NULL, // n/a NULL, // n/a
NULL, // n/a NULL, // n/a
"eq", // TCG_COND_EQ "eq", // TCG_COND_EQ
"ne", // TCG_COND_NE "ne", // TCG_COND_NE
"le", // TCG_COND_LE "le", // TCG_COND_LE
"gt", // TCG_COND_GT "gt", // TCG_COND_GT
"leu", // TCG_COND_LEU "leu", // TCG_COND_LEU
"gtu", // TCG_COND_GTU "gtu", // TCG_COND_GTU
NULL, // n/a NULL, // n/a
NULL, // n/a NULL, // n/a
#else #else
[TCG_COND_NEVER] = "never", [TCG_COND_NEVER] = "never",
[TCG_COND_ALWAYS] = "always", [TCG_COND_ALWAYS] = "always",
@ -1135,43 +1135,43 @@ static const char * const cond_name[] =
static const char * const ldst_name[] = static const char * const ldst_name[] =
{ {
#ifdef _MSC_VER #ifdef _MSC_VER
"ub", // MO_UB "ub", // MO_UB
# ifdef HOST_WORDS_BIGENDIAN # ifdef HOST_WORDS_BIGENDIAN
"beuw", // MO_BEUW "beuw", // MO_BEUW
"beul", // MO_BEUL "beul", // MO_BEUL
"beq", // MO_BEQ "beq", // MO_BEQ
"sb", // MO_SB "sb", // MO_SB
"besw", // MO_BESW "besw", // MO_BESW
"besl", // MO_BESL "besl", // MO_BESL
NULL, // n/a NULL, // n/a
NULL, // n/a NULL, // n/a
"leuw", // MO_LEUW "leuw", // MO_LEUW
"leul", // MO_LEUL "leul", // MO_LEUL
"leq", // MO_LEQ "leq", // MO_LEQ
NULL, // n/a NULL, // n/a
"lesw", // MO_LESW "lesw", // MO_LESW
"lesl", // MO_LESL "lesl", // MO_LESL
NULL, // n/a NULL, // n/a
# else // !HOST_WORDS_BIGENDIAN # else // !HOST_WORDS_BIGENDIAN
"leuw", // MO_LEUW "leuw", // MO_LEUW
"leul", // MO_LEUL "leul", // MO_LEUL
"leq", // MO_LEQ "leq", // MO_LEQ
"sb", // MO_SB "sb", // MO_SB
"lesw", // MO_LESW "lesw", // MO_LESW
"lesl", // MO_LESL "lesl", // MO_LESL
NULL, // n/a NULL, // n/a
NULL, // n/a NULL, // n/a
"beuw", // MO_BEUW "beuw", // MO_BEUW
"beul", // MO_BEUL "beul", // MO_BEUL
"beq", // MO_BEQ "beq", // MO_BEQ
NULL, // n/a NULL, // n/a
"besw", // MO_BESW "besw", // MO_BESW
"besl", // MO_BESL "besl", // MO_BESL
NULL, // n/a NULL, // n/a
# endif // HOST_WORDS_BIGENDIAN # endif // HOST_WORDS_BIGENDIAN
#else //_MSC_VER #else //_MSC_VER
[MO_UB] = "ub", [MO_UB] = "ub",
[MO_SB] = "sb", [MO_SB] = "sb",
[MO_LEUW] = "leuw", [MO_LEUW] = "leuw",
[MO_LESW] = "lesw", [MO_LESW] = "lesw",
@ -2376,10 +2376,10 @@ static int tcg_reg_alloc_call(TCGContext *s, const TCGOpDef *def,
nb_regs = ARRAY_SIZE(tcg_target_call_iarg_regs); nb_regs = ARRAY_SIZE(tcg_target_call_iarg_regs);
#if TCG_TARGET_REG_BITS == 32 #if TCG_TARGET_REG_BITS == 32
// do this because msvc cannot have arrays with 0 entries. // do this because msvc cannot have arrays with 0 entries.
nb_regs = 0; nb_regs = 0;
#endif #endif
if (nb_regs > nb_params) { if (nb_regs > nb_params) {
nb_regs = nb_params; nb_regs = nb_params;
} }

4
qemu/util/bitops.c
View file

@ -19,7 +19,7 @@
* Find the next set bit in a memory region. * Find the next set bit in a memory region.
*/ */
unsigned long find_next_bit(const unsigned long *addr, unsigned long size, unsigned long find_next_bit(const unsigned long *addr, unsigned long size,
unsigned long offset) unsigned long offset)
{ {
const unsigned long *p = addr + BITOP_WORD(offset); const unsigned long *p = addr + BITOP_WORD(offset);
unsigned long result = offset & ~(BITS_PER_LONG-1); unsigned long result = offset & ~(BITS_PER_LONG-1);
@ -84,7 +84,7 @@ found_middle:
* Linus' asm-alpha/bitops.h. * Linus' asm-alpha/bitops.h.
*/ */
unsigned long find_next_zero_bit(const unsigned long *addr, unsigned long size, unsigned long find_next_zero_bit(const unsigned long *addr, unsigned long size,
unsigned long offset) unsigned long offset)
{ {
const unsigned long *p = addr + BITOP_WORD(offset); const unsigned long *p = addr + BITOP_WORD(offset);
unsigned long result = offset & ~(BITS_PER_LONG-1); unsigned long result = offset & ~(BITS_PER_LONG-1);

6
samples/mem_apis.c
View file

@ -359,7 +359,7 @@ static void unmap_test()
int main(int argc, char **argv, char **envp) int main(int argc, char **argv, char **envp)
{ {
// dynamically load shared library // dynamically load shared library
#ifdef DYNLOAD #ifdef DYNLOAD
if (!uc_dyn_load(NULL, 0)) { if (!uc_dyn_load(NULL, 0)) {
printf("Error dynamically loading shared library.\n"); printf("Error dynamically loading shared library.\n");
@ -370,7 +370,7 @@ int main(int argc, char **argv, char **envp)
} }
#endif #endif
nx_test(); nx_test();
perms_test(); perms_test();
unmap_test(); unmap_test();
@ -379,5 +379,5 @@ int main(int argc, char **argv, char **envp)
uc_dyn_free(); uc_dyn_free();
#endif #endif
return 0; return 0;
} }

4
samples/sample_arm.c
View file

@ -152,7 +152,7 @@ static void test_thumb(void)
int main(int argc, char **argv, char **envp) int main(int argc, char **argv, char **envp)
{ {
// dynamically load shared library // dynamically load shared library
#ifdef DYNLOAD #ifdef DYNLOAD
if (!uc_dyn_load(NULL, 0)) { if (!uc_dyn_load(NULL, 0)) {
printf("Error dynamically loading shared library.\n"); printf("Error dynamically loading shared library.\n");
@ -163,7 +163,7 @@ int main(int argc, char **argv, char **envp)
} }
#endif #endif
test_arm(); test_arm();
printf("==========================\n"); printf("==========================\n");
test_thumb(); test_thumb();

4
samples/sample_arm64.c
View file

@ -98,7 +98,7 @@ static void test_arm64(void)
int main(int argc, char **argv, char **envp) int main(int argc, char **argv, char **envp)
{ {
// dynamically load shared library // dynamically load shared library
#ifdef DYNLOAD #ifdef DYNLOAD
if (!uc_dyn_load(NULL, 0)) { if (!uc_dyn_load(NULL, 0)) {
printf("Error dynamically loading shared library.\n"); printf("Error dynamically loading shared library.\n");
@ -109,7 +109,7 @@ int main(int argc, char **argv, char **envp)
} }
#endif #endif
test_arm64(); test_arm64();
// dynamically free shared library // dynamically free shared library
#ifdef DYNLOAD #ifdef DYNLOAD

4
samples/sample_m68k.c
View file

@ -160,7 +160,7 @@ static void test_m68k(void)
int main(int argc, char **argv, char **envp) int main(int argc, char **argv, char **envp)
{ {
// dynamically load shared library // dynamically load shared library
#ifdef DYNLOAD #ifdef DYNLOAD
if (!uc_dyn_load(NULL, 0)) { if (!uc_dyn_load(NULL, 0)) {
printf("Error dynamically loading shared library.\n"); printf("Error dynamically loading shared library.\n");
@ -171,7 +171,7 @@ int main(int argc, char **argv, char **envp)
} }
#endif #endif
test_m68k(); test_m68k();
// dynamically free shared library // dynamically free shared library
#ifdef DYNLOAD #ifdef DYNLOAD

4
samples/sample_mips.c
View file

@ -145,7 +145,7 @@ static void test_mips_el(void)
int main(int argc, char **argv, char **envp) int main(int argc, char **argv, char **envp)
{ {
// dynamically load shared library // dynamically load shared library
#ifdef DYNLOAD #ifdef DYNLOAD
if (!uc_dyn_load(NULL, 0)) { if (!uc_dyn_load(NULL, 0)) {
printf("Error dynamically loading shared library.\n"); printf("Error dynamically loading shared library.\n");
@ -156,7 +156,7 @@ int main(int argc, char **argv, char **envp)
} }
#endif #endif
test_mips_eb(); test_mips_eb();
test_mips_el(); test_mips_el();
// dynamically free shared library // dynamically free shared library

4
samples/sample_sparc.c
View file

@ -100,7 +100,7 @@ static void test_sparc(void)
int main(int argc, char **argv, char **envp) int main(int argc, char **argv, char **envp)
{ {
// dynamically load shared library // dynamically load shared library
#ifdef DYNLOAD #ifdef DYNLOAD
if (!uc_dyn_load(NULL, 0)) { if (!uc_dyn_load(NULL, 0)) {
printf("Error dynamically loading shared library.\n"); printf("Error dynamically loading shared library.\n");
@ -111,7 +111,7 @@ int main(int argc, char **argv, char **envp)
} }
#endif #endif
test_sparc(); test_sparc();
// dynamically free shared library // dynamically free shared library
#ifdef DYNLOAD #ifdef DYNLOAD

2
samples/sample_x86.c
View file

@ -972,7 +972,7 @@ int main(int argc, char **argv, char **envp)
test_x86_16(); test_x86_16();
} }
else if (!strcmp(argv[1], "-32")) { else if (!strcmp(argv[1], "-32")) {
test_i386(); test_i386();
test_i386_map_ptr(); test_i386_map_ptr();
test_i386_inout(); test_i386_inout();
test_i386_context_save(); test_i386_context_save();

2
samples/shellcode.c
View file

@ -157,7 +157,7 @@ static void test_i386(void)
int main(int argc, char **argv, char **envp) int main(int argc, char **argv, char **envp)
{ {
// dynamically load shared library // dynamically load shared library
#ifdef DYNLOAD #ifdef DYNLOAD
if (!uc_dyn_load(NULL, 0)) { if (!uc_dyn_load(NULL, 0)) {
printf("Error dynamically loading shared library.\n"); printf("Error dynamically loading shared library.\n");

2
tests/regress/memleak_arm.c
View file

@ -151,7 +151,7 @@ static void test_thumb(void)
int main(int argc, char **argv, char **envp) int main(int argc, char **argv, char **envp)
{ {
// dynamically load shared library // dynamically load shared library
#ifdef DYNLOAD #ifdef DYNLOAD
if (!uc_dyn_load(NULL, 0)) { if (!uc_dyn_load(NULL, 0)) {
printf("Error dynamically loading shared library.\n"); printf("Error dynamically loading shared library.\n");

2
tests/regress/memleak_arm64.c
View file

@ -98,7 +98,7 @@ static void test_arm64(void)
int main(int argc, char **argv, char **envp) int main(int argc, char **argv, char **envp)
{ {
// dynamically load shared library // dynamically load shared library
#ifdef DYNLOAD #ifdef DYNLOAD
if (!uc_dyn_load(NULL, 0)) { if (!uc_dyn_load(NULL, 0)) {
printf("Error dynamically loading shared library.\n"); printf("Error dynamically loading shared library.\n");

2
tests/regress/memleak_m68k.c
View file

@ -160,7 +160,7 @@ static void test_m68k(void)
int main(int argc, char **argv, char **envp) int main(int argc, char **argv, char **envp)
{ {
// dynamically load shared library // dynamically load shared library
#ifdef DYNLOAD #ifdef DYNLOAD
if (!uc_dyn_load(NULL, 0)) { if (!uc_dyn_load(NULL, 0)) {
printf("Error dynamically loading shared library.\n"); printf("Error dynamically loading shared library.\n");

2
tests/regress/memleak_mips.c
View file

@ -145,7 +145,7 @@ static void test_mips_el(void)
int main(int argc, char **argv, char **envp) int main(int argc, char **argv, char **envp)
{ {
// dynamically load shared library // dynamically load shared library
#ifdef DYNLOAD #ifdef DYNLOAD
if (!uc_dyn_load(NULL, 0)) { if (!uc_dyn_load(NULL, 0)) {
printf("Error dynamically loading shared library.\n"); printf("Error dynamically loading shared library.\n");

2
tests/regress/memleak_sparc.c
View file

@ -100,7 +100,7 @@ static void test_sparc(void)
int main(int argc, char **argv, char **envp) int main(int argc, char **argv, char **envp)
{ {
// dynamically load shared library // dynamically load shared library
#ifdef DYNLOAD #ifdef DYNLOAD
if (!uc_dyn_load(NULL, 0)) { if (!uc_dyn_load(NULL, 0)) {
printf("Error dynamically loading shared library.\n"); printf("Error dynamically loading shared library.\n");

2
tests/regress/memleak_x86.c
View file

@ -281,7 +281,7 @@ static void test_x86_64(void)
int main(int argc, char **argv, char **envp) int main(int argc, char **argv, char **envp)
{ {
// dynamically load shared library // dynamically load shared library
#ifdef DYNLOAD #ifdef DYNLOAD
if (!uc_dyn_load(NULL, 0)) { if (!uc_dyn_load(NULL, 0)) {
printf("Error dynamically loading shared library.\n"); printf("Error dynamically loading shared library.\n");

94
tests/regress/mips_delay_slot_code_hook.c
View file

@ -40,11 +40,11 @@ but that the code hook is just not occurring.
// It should loop 3 times before ending. // It should loop 3 times before ending.
const uint64_t addr = 0x100000; const uint64_t addr = 0x100000;
const unsigned char loop_test_code[] = { const unsigned char loop_test_code[] = {
0x02,0x00,0x04,0x24, // 100000: li $a0, 2 0x02,0x00,0x04,0x24, // 100000: li $a0, 2
// loop1 // loop1
0x00,0x00,0x00,0x00, // 100004: nop 0x00,0x00,0x00,0x00, // 100004: nop
0xFE,0xFF,0x80,0x14, // 100008: bnez $a0, loop1 0xFE,0xFF,0x80,0x14, // 100008: bnez $a0, loop1
0xFF,0xFF,0x84,0x24, // 10000C: addiu $a0, -1 0xFF,0xFF,0x84,0x24, // 10000C: addiu $a0, -1
}; };
bool test_passed_ok = false; bool test_passed_ok = false;
int loop_count = 0; int loop_count = 0;
@ -52,14 +52,14 @@ int loop_count = 0;
static void mips_codehook(uc_engine *uc, uint64_t address, uint32_t size, void *user_data) static void mips_codehook(uc_engine *uc, uint64_t address, uint32_t size, void *user_data)
{ {
if( address == 0x10000C ) if( address == 0x10000C )
test_passed_ok = true; test_passed_ok = true;
if( address == 0x100004 ) if( address == 0x100004 )
{ {
printf("\nloop %d:\n", loop_count); printf("\nloop %d:\n", loop_count);
loop_count++; loop_count++;
} }
printf("Code: %"PRIx64"\n", address); printf("Code: %"PRIx64"\n", address);
} }
@ -67,74 +67,74 @@ int main(int argc, char **argv, char **envp)
{ {
uc_engine *uc; uc_engine *uc;
uc_err err; uc_err err;
uc_hook hhc; uc_hook hhc;
uint32_t val; uint32_t val;
// dynamically load shared library // dynamically load shared library
#ifdef DYNLOAD #ifdef DYNLOAD
uc_dyn_load(NULL, 0); uc_dyn_load(NULL, 0);
#endif #endif
// Initialize emulator in MIPS 32bit little endian mode // Initialize emulator in MIPS 32bit little endian mode
err = uc_open(UC_ARCH_MIPS, UC_MODE_MIPS32, &uc); err = uc_open(UC_ARCH_MIPS, UC_MODE_MIPS32, &uc);
if (err) if (err)
{ {
printf("Failed on uc_open() with error returned: %u\n", err); printf("Failed on uc_open() with error returned: %u\n", err);
return err; return err;
} }
// map in a page of mem // map in a page of mem
err = uc_mem_map(uc, addr, 0x1000, UC_PROT_ALL); err = uc_mem_map(uc, addr, 0x1000, UC_PROT_ALL);
if (err) if (err)
{ {
printf("Failed on uc_mem_map() with error returned: %u\n", err); printf("Failed on uc_mem_map() with error returned: %u\n", err);
return err; return err;
} }
// write machine code to be emulated to memory // write machine code to be emulated to memory
err = uc_mem_write(uc, addr, loop_test_code, sizeof(loop_test_code)); err = uc_mem_write(uc, addr, loop_test_code, sizeof(loop_test_code));
if( err ) if( err )
{ {
printf("Failed on uc_mem_write() with error returned: %u\n", err); printf("Failed on uc_mem_write() with error returned: %u\n", err);
return err; return err;
} }
// hook all instructions by having @begin > @end // hook all instructions by having @begin > @end
uc_hook_add(uc, &hhc, UC_HOOK_CODE, mips_codehook, NULL, 1, 0); uc_hook_add(uc, &hhc, UC_HOOK_CODE, mips_codehook, NULL, 1, 0);
if( err ) if( err )
{ {
printf("Failed on uc_hook_add(code) with error returned: %u\n", err); printf("Failed on uc_hook_add(code) with error returned: %u\n", err);
return err; return err;
} }
// execute code // execute code
printf("---- Executing Code ----\n"); printf("---- Executing Code ----\n");
err = uc_emu_start(uc, addr, addr + sizeof(loop_test_code), 0, 0); err = uc_emu_start(uc, addr, addr + sizeof(loop_test_code), 0, 0);
if (err) if (err)
{ {
printf("Failed on uc_emu_start() with error returned %u: %s\n", printf("Failed on uc_emu_start() with error returned %u: %s\n",
err, uc_strerror(err)); err, uc_strerror(err));
return err; return err;
} }
// done executing, print some reg values as a test // done executing, print some reg values as a test
printf("---- Execution Complete ----\n\n"); printf("---- Execution Complete ----\n\n");
uc_reg_read(uc, UC_MIPS_REG_PC, &val); printf("pc is %X\n", val); uc_reg_read(uc, UC_MIPS_REG_PC, &val); printf("pc is %X\n", val);
uc_reg_read(uc, UC_MIPS_REG_A0, &val); printf("a0 is %X\n", val); uc_reg_read(uc, UC_MIPS_REG_A0, &val); printf("a0 is %X\n", val);
// free resources // free resources
uc_close(uc); uc_close(uc);
if( test_passed_ok ) if( test_passed_ok )
printf("\n\nTEST PASSED!\n\n"); printf("\n\nTEST PASSED!\n\n");
else else
printf("\n\nTEST FAILED!\n\n"); printf("\n\nTEST FAILED!\n\n");
// dynamically free shared library // dynamically free shared library
#ifdef DYNLOAD #ifdef DYNLOAD
uc_dyn_free(); uc_dyn_free();
#endif #endif
return 0; return 0;
} }

208
tests/regress/threaded_emu_start.c
View file

@ -52,11 +52,11 @@ background.
// This should loop forever. // This should loop forever.
const uint64_t addr = 0x100000; const uint64_t addr = 0x100000;
const unsigned char loop_test_code[] = { const unsigned char loop_test_code[] = {
0x02,0x00,0x04,0x24, // 100000: li $a0, 2 0x02,0x00,0x04,0x24, // 100000: li $a0, 2
// loop1 // loop1
0x00,0x00,0x00,0x00, // 100004: nop 0x00,0x00,0x00,0x00, // 100004: nop
0xFE,0xFF,0x80,0x14, // 100008: bnez $a0, loop1 0xFE,0xFF,0x80,0x14, // 100008: bnez $a0, loop1
0x00,0x00,0x00,0x00, // 10000C: nop 0x00,0x00,0x00,0x00, // 10000C: nop
}; };
bool test_passed_ok = false; bool test_passed_ok = false;
int loop_count = 0; int loop_count = 0;
@ -65,14 +65,14 @@ int loop_count = 0;
// This hook is used to show that code is executing in the emulator. // This hook is used to show that code is executing in the emulator.
static void mips_codehook(uc_engine *uc, uint64_t address, uint32_t size, void *user_data) static void mips_codehook(uc_engine *uc, uint64_t address, uint32_t size, void *user_data)
{ {
printf("Code: %"PRIx64"\n", address); printf("Code: %"PRIx64"\n", address);
} }
typedef struct { typedef struct {
uc_engine *uc; uc_engine *uc;
uint64_t startAddr; uint64_t startAddr;
uint64_t endAddr; uint64_t endAddr;
} EmuStarterParam_t; } EmuStarterParam_t;
// This is a thread that just runs uc_emu_start() in it. // This is a thread that just runs uc_emu_start() in it.
@ -80,38 +80,38 @@ typedef struct {
static uc_err emu_starter(void* param) static uc_err emu_starter(void* param)
{ {
uc_engine *uc; uc_engine *uc;
uint64_t start_addr; uint64_t start_addr;
uint64_t end_addr; uint64_t end_addr;
uc_err err; uc_err err;
EmuStarterParam_t* starter_params = (EmuStarterParam_t *)param; EmuStarterParam_t* starter_params = (EmuStarterParam_t *)param;
uc = starter_params->uc; uc = starter_params->uc;
start_addr = starter_params->startAddr; start_addr = starter_params->startAddr;
end_addr = starter_params->endAddr; end_addr = starter_params->endAddr;
printf("uc_emu_start()\n"); printf("uc_emu_start()\n");
err = uc_emu_start(uc, start_addr, end_addr, 0, 0); err = uc_emu_start(uc, start_addr, end_addr, 0, 0);
if (err) if (err)
{ {
printf("Failed on uc_emu_start() with error returned %u: %s\n", printf("Failed on uc_emu_start() with error returned %u: %s\n",
err, uc_strerror(err)); err, uc_strerror(err));
} }
return err; return err;
} }
#ifdef _WIN32 #ifdef _WIN32
static unsigned int __stdcall win32_emu_starter(void* param) static unsigned int __stdcall win32_emu_starter(void* param)
{ {
uc_err err = emu_starter(param); uc_err err = emu_starter(param);
_endthreadex(err); _endthreadex(err);
return err; return err;
} }
#else #else
static void* posix_emu_starter(void* param) static void* posix_emu_starter(void* param)
{ {
uc_err err = emu_starter(param); uc_err err = emu_starter(param);
return (void*)err; return (void*)err;
} }
#endif #endif
@ -120,124 +120,124 @@ int main(int argc, char **argv, char **envp)
{ {
uc_engine *uc; uc_engine *uc;
uc_err err; uc_err err;
int ret; int ret;
uc_hook hhc; uc_hook hhc;
uint32_t val; uint32_t val;
EmuStarterParam_t starter_params; EmuStarterParam_t starter_params;
#ifdef _WIN32 #ifdef _WIN32
HANDLE th = (HANDLE)-1; HANDLE th = (HANDLE)-1;
#else #else
pthread_t th; pthread_t th;
#endif #endif
// dynamically load shared library // dynamically load shared library
#ifdef DYNLOAD #ifdef DYNLOAD
uc_dyn_load(NULL, 0); uc_dyn_load(NULL, 0);
#endif #endif
// Initialize emulator in MIPS 32bit little endian mode // Initialize emulator in MIPS 32bit little endian mode
printf("uc_open()\n"); printf("uc_open()\n");
err = uc_open(UC_ARCH_MIPS, UC_MODE_MIPS32, &uc); err = uc_open(UC_ARCH_MIPS, UC_MODE_MIPS32, &uc);
if (err) if (err)
{ {
printf("Failed on uc_open() with error returned: %u\n", err); printf("Failed on uc_open() with error returned: %u\n", err);
return err; return err;
} }
// map in a page of mem // map in a page of mem
printf("uc_mem_map()\n"); printf("uc_mem_map()\n");
err = uc_mem_map(uc, addr, 0x1000, UC_PROT_ALL); err = uc_mem_map(uc, addr, 0x1000, UC_PROT_ALL);
if (err) if (err)
{ {
printf("Failed on uc_mem_map() with error returned: %u\n", err); printf("Failed on uc_mem_map() with error returned: %u\n", err);
return err; return err;
} }
// write machine code to be emulated to memory // write machine code to be emulated to memory
printf("uc_mem_write()\n"); printf("uc_mem_write()\n");
err = uc_mem_write(uc, addr, loop_test_code, sizeof(loop_test_code)); err = uc_mem_write(uc, addr, loop_test_code, sizeof(loop_test_code));
if( err ) if( err )
{ {
printf("Failed on uc_mem_write() with error returned: %u\n", err); printf("Failed on uc_mem_write() with error returned: %u\n", err);
return err; return err;
} }
// hook all instructions by having @begin > @end // hook all instructions by having @begin > @end
printf("uc_hook_add()\n"); printf("uc_hook_add()\n");
uc_hook_add(uc, &hhc, UC_HOOK_CODE, mips_codehook, NULL, 1, 0); uc_hook_add(uc, &hhc, UC_HOOK_CODE, mips_codehook, NULL, 1, 0);
if( err ) if( err )
{ {
printf("Failed on uc_hook_add(code) with error returned: %u\n", err); printf("Failed on uc_hook_add(code) with error returned: %u\n", err);
return err; return err;
} }
// start background thread // start background thread
printf("---- Thread Starting ----\n"); printf("---- Thread Starting ----\n");
starter_params.uc = uc; starter_params.uc = uc;
starter_params.startAddr = addr; starter_params.startAddr = addr;
starter_params.endAddr = addr + sizeof(loop_test_code); starter_params.endAddr = addr + sizeof(loop_test_code);
#ifdef _WIN32 #ifdef _WIN32
// create thread // create thread
th = (HANDLE)_beginthreadex(NULL, 0, win32_emu_starter, &starter_params, CREATE_SUSPENDED, NULL); th = (HANDLE)_beginthreadex(NULL, 0, win32_emu_starter, &starter_params, CREATE_SUSPENDED, NULL);
if(th == (HANDLE)-1) if(th == (HANDLE)-1)
{ {
printf("Failed on _beginthreadex() with error returned: %u\n", _errno()); printf("Failed on _beginthreadex() with error returned: %u\n", _errno());
return -1; return -1;
} }
// start thread // start thread
ret = ResumeThread(th); ret = ResumeThread(th);
if( ret == -1 ) if( ret == -1 )
{ {
printf("Failed on ResumeThread() with error returned: %u\n", _errno()); printf("Failed on ResumeThread() with error returned: %u\n", _errno());
return -2; return -2;
} }
// wait 3 seconds // wait 3 seconds
Sleep(3 * 1000); Sleep(3 * 1000);
#else #else
// add posix code to start the emu_starter() thread // add posix code to start the emu_starter() thread
ret = pthread_create(&th, NULL, posix_emu_starter, &starter_params); ret = pthread_create(&th, NULL, posix_emu_starter, &starter_params);
if( ret ) if( ret )
{ {
printf("Failed on pthread_create() with error returned: %u\n", err); printf("Failed on pthread_create() with error returned: %u\n", err);
return -2; return -2;
} }
// wait 3 seconds // wait 3 seconds
sleep(3); sleep(3);
#endif #endif
// Stop the thread after it has been let to run in the background for a while // Stop the thread after it has been let to run in the background for a while
printf("---- Thread Stopping ----\n"); printf("---- Thread Stopping ----\n");
printf("uc_emu_stop()\n"); printf("uc_emu_stop()\n");
err = uc_emu_stop(uc); err = uc_emu_stop(uc);
if( err ) if( err )
{ {
printf("Failed on uc_emu_stop() with error returned: %u\n", err); printf("Failed on uc_emu_stop() with error returned: %u\n", err);
return err; return err;
} }
test_passed_ok = true; test_passed_ok = true;
// done executing, print some reg values as a test // done executing, print some reg values as a test
uc_reg_read(uc, UC_MIPS_REG_PC, &val); printf("pc is %X\n", val); uc_reg_read(uc, UC_MIPS_REG_PC, &val); printf("pc is %X\n", val);
uc_reg_read(uc, UC_MIPS_REG_A0, &val); printf("a0 is %X\n", val); uc_reg_read(uc, UC_MIPS_REG_A0, &val); printf("a0 is %X\n", val);
// free resources // free resources
printf("uc_close()\n"); printf("uc_close()\n");
uc_close(uc); uc_close(uc);
if( test_passed_ok ) if( test_passed_ok )
printf("\n\nTEST PASSED!\n\n"); printf("\n\nTEST PASSED!\n\n");
else else
printf("\n\nTEST FAILED!\n\n"); printf("\n\nTEST FAILED!\n\n");
// dynamically free shared library // dynamically free shared library
#ifdef DYNLOAD #ifdef DYNLOAD
uc_dyn_free(); uc_dyn_free();
#endif #endif
return 0; return 0;
} }

116
tests/unit/test_hang.c
View file

@ -1,6 +1,6 @@
/* /*
refer to issue #575. refer to issue #575.
to run correctly unicorn needs to be compiled for AArch64. to run correctly unicorn needs to be compiled for AArch64.
*/ */
#include "unicorn_test.h" #include "unicorn_test.h"
@ -9,94 +9,94 @@
uint64_t trunc_page(uint64_t addr) uint64_t trunc_page(uint64_t addr)
{ {
return (addr & ~(4095)); return (addr & ~(4095));
} }
/* Called before every test to set up a new instance */ /* Called before every test to set up a new instance */
static int init(void **state) static int init(void **state)
{ {
printf("[+] Initializing Unicorn...\n"); printf("[+] Initializing Unicorn...\n");
uc_engine *uc; uc_engine *uc;
if (uc_open(UC_ARCH_ARM64, UC_MODE_ARM, &uc) != UC_ERR_OK) { if (uc_open(UC_ARCH_ARM64, UC_MODE_ARM, &uc) != UC_ERR_OK) {
printf("Error on open. Be sure that your unicorn library supports AArch64.\n"); printf("Error on open. Be sure that your unicorn library supports AArch64.\n");
return -1; return -1;
} }
*state = uc; *state = uc;
return 0; return 0;
} }
/* Called after every test to clean up */ /* Called after every test to clean up */
static int teardown(void **state) static int teardown(void **state)
{ {
printf("[+] Exiting...\n"); printf("[+] Exiting...\n");
uc_engine *uc = *state; uc_engine *uc = *state;
uc_close(uc); uc_close(uc);
*state = NULL; *state = NULL;
return 0; return 0;
} }
void test_hang(void **state) void test_hang(void **state)
{ {
uint32_t code[] = { uint32_t code[] = {
0xd503201f, /* NOP */ 0xd503201f, /* NOP */
0xd503201f, /* NOP */ 0xd503201f, /* NOP */
0xd503201f, /* NOP */ 0xd503201f, /* NOP */
0xaa0103e0 /* MOV X0, X1 */ 0xaa0103e0 /* MOV X0, X1 */
}; };
uc_engine *uc = *state; uc_engine *uc = *state;
uint64_t x0 = 0; uint64_t x0 = 0;
uint64_t x1 = 1; uint64_t x1 = 1;
/* /*
* emulation will hang if some instruction hits every quarter of a page, * emulation will hang if some instruction hits every quarter of a page,
* i.e. these offsets: * i.e. these offsets:
* 0x1400, 0x1800, 0x1c00, 0x2000 * 0x1400, 0x1800, 0x1c00, 0x2000
* *
* in this test, the code to be emulated is mapped just before the 0x1400 * in this test, the code to be emulated is mapped just before the 0x1400
* offset, so that the final instruction emulated (MOV X0, X1) hits the offset, * offset, so that the final instruction emulated (MOV X0, X1) hits the offset,
* causing the hang. * causing the hang.
* If you try to write the code just four bytes behind, the hang doesn't occur. * If you try to write the code just four bytes behind, the hang doesn't occur.
* *
* So far, this strange behaviour has only been observed with AArch64 Unicorn APIs. * So far, this strange behaviour has only been observed with AArch64 Unicorn APIs.
*/ */
uint64_t addr = 0x13f0; // try to map at (0x13f0 - 0x4) and the hang doesn't occur uint64_t addr = 0x13f0; // try to map at (0x13f0 - 0x4) and the hang doesn't occur
uint64_t trunc_addr = trunc_page(addr); // round down to nearest page uint64_t trunc_addr = trunc_page(addr); // round down to nearest page
uc_mem_map(uc, trunc_addr, 2 * 1024 * 1024, UC_PROT_ALL); uc_mem_map(uc, trunc_addr, 2 * 1024 * 1024, UC_PROT_ALL);
if (uc_mem_write(uc, addr, &code, sizeof(code))) { if (uc_mem_write(uc, addr, &code, sizeof(code))) {
printf("error on write\n"); printf("error on write\n");
return; return;
} }
uc_reg_write(uc, UC_ARM64_REG_X0, &x0); uc_reg_write(uc, UC_ARM64_REG_X0, &x0);
uc_reg_write(uc, UC_ARM64_REG_X1, &x1); uc_reg_write(uc, UC_ARM64_REG_X1, &x1);
if (uc_emu_start(uc, addr, addr + sizeof(code), 0, 0)) { if (uc_emu_start(uc, addr, addr + sizeof(code), 0, 0)) {
printf("error on start\n"); printf("error on start\n");
return; return;
} }
uc_reg_read(uc, UC_ARM64_REG_X0, &x0); uc_reg_read(uc, UC_ARM64_REG_X0, &x0);
uc_reg_read(uc, UC_ARM64_REG_X1, &x1); uc_reg_read(uc, UC_ARM64_REG_X1, &x1);
printf("x0: %"PRIx64"\n", x0); printf("x0: %"PRIx64"\n", x0);
printf("x1: %"PRIx64"\n", x1); printf("x1: %"PRIx64"\n", x1);
} }
int main(int argc, const char * argv[]) { int main(int argc, const char * argv[]) {
const struct CMUnitTest tests[] = { const struct CMUnitTest tests[] = {
cmocka_unit_test_setup_teardown(test_hang, init, teardown), cmocka_unit_test_setup_teardown(test_hang, init, teardown),
}; };
return cmocka_run_group_tests(tests, NULL, NULL);; return cmocka_run_group_tests(tests, NULL, NULL);;
} }

548
tests/unit/test_x86_shl_enter_leave.c
View file

@ -16,24 +16,24 @@
typedef struct _reg_value typedef struct _reg_value
{ {
uint32_t regId, regValue, mask; uint32_t regId, regValue, mask;
} reg_value; } reg_value;
typedef struct _instruction typedef struct _instruction
{ {
const char* asmStr; const char* asmStr;
uint8_t code[16]; //x86 inst == 15 bytes max uint8_t code[16]; //x86 inst == 15 bytes max
uint32_t codeSize; uint32_t codeSize;
reg_value* values; reg_value* values;
uint32_t nbValues; uint32_t nbValues;
uint32_t addr; uint32_t addr;
} instruction; } instruction;
typedef struct _block typedef struct _block
{ {
instruction* insts[255]; instruction* insts[255];
uint32_t nbInsts; uint32_t nbInsts;
uint32_t size; uint32_t size;
} block; } block;
/******************************************************************************/ /******************************************************************************/
@ -42,23 +42,23 @@ typedef struct _block
#define CAT(X, Y) CAT2(X, Y) #define CAT(X, Y) CAT2(X, Y)
#define BLOCK_START(BLOCK) \ #define BLOCK_START(BLOCK) \
{ \ { \
block* blockPtr = &BLOCK; \ block* blockPtr = &BLOCK; \
blockPtr->nbInsts = 0; \ blockPtr->nbInsts = 0; \
instruction* instPtr = NULL; instruction* instPtr = NULL;
#define BLOCK_END() } #define BLOCK_END() }
#define BLOCK_ADD(CODE_ASM, CODE) \ #define BLOCK_ADD(CODE_ASM, CODE) \
const uint8_t CAT(code, __LINE__)[] = CODE; \ const uint8_t CAT(code, __LINE__)[] = CODE; \
instPtr = newInstruction(CAT(code, __LINE__), sizeof(CAT(code, __LINE__)), CODE_ASM, NULL, 0); \ instPtr = newInstruction(CAT(code, __LINE__), sizeof(CAT(code, __LINE__)), CODE_ASM, NULL, 0); \
addInstructionToBlock(blockPtr, instPtr); addInstructionToBlock(blockPtr, instPtr);
#define BLOCK_ADD_CHECK(CODE_ASM, CODE, REGVALUES) \ #define BLOCK_ADD_CHECK(CODE_ASM, CODE, REGVALUES) \
const uint8_t CAT(code, __LINE__)[] = CODE; \ const uint8_t CAT(code, __LINE__)[] = CODE; \
const reg_value CAT(regValues, __LINE__)[] = REGVALUES; \ const reg_value CAT(regValues, __LINE__)[] = REGVALUES; \
instPtr = newInstruction(CAT(code, __LINE__), sizeof(CAT(code, __LINE__)), CODE_ASM, CAT(regValues, __LINE__), sizeof(CAT(regValues, __LINE__)) / sizeof(reg_value)); \ instPtr = newInstruction(CAT(code, __LINE__), sizeof(CAT(code, __LINE__)), CODE_ASM, CAT(regValues, __LINE__), sizeof(CAT(regValues, __LINE__)) / sizeof(reg_value)); \
addInstructionToBlock(blockPtr, instPtr); addInstructionToBlock(blockPtr, instPtr);
#define V(...) { __VA_ARGS__ } #define V(...) { __VA_ARGS__ }
@ -77,43 +77,43 @@ void initRegisters(uc_engine *uc);
void hook_code_test_i386_shl(uc_engine *uc, uint64_t address, uint32_t size, void *user_data) void hook_code_test_i386_shl(uc_engine *uc, uint64_t address, uint32_t size, void *user_data)
{ {
uint32_t i; uint32_t i;
block* b = (block*)user_data; block* b = (block*)user_data;
instruction* currInst = getInstruction(b, (uint32_t)address); instruction* currInst = getInstruction(b, (uint32_t)address);
assert_true(currInst != NULL); assert_true(currInst != NULL);
print_message("|\teip=%08x - %s\n", (uint32_t)address, currInst->asmStr); print_message("|\teip=%08x - %s\n", (uint32_t)address, currInst->asmStr);
for (i = 0; i < currInst->nbValues; i++) for (i = 0; i < currInst->nbValues; i++)
{ {
uint32_t regValue = getRegisterValue(uc, currInst->values[i].regId); uint32_t regValue = getRegisterValue(uc, currInst->values[i].regId);
print_message("|\t\ttesting %s : ", getRegisterName(currInst->values[i].regId)); print_message("|\t\ttesting %s : ", getRegisterName(currInst->values[i].regId));
assert_int_equal(regValue & currInst->values[i].mask, currInst->values[i].regValue); assert_int_equal(regValue & currInst->values[i].mask, currInst->values[i].regValue);
print_message("ok\n"); print_message("ok\n");
} }
if (currInst->code[0] == 0xCC) if (currInst->code[0] == 0xCC)
OK(uc_emu_stop(uc)); OK(uc_emu_stop(uc));
} }
bool hook_mem_invalid(uc_engine *uc, uc_mem_type type, uint64_t addr, int size, int64_t value, void *user_data) bool hook_mem_invalid(uc_engine *uc, uc_mem_type type, uint64_t addr, int size, int64_t value, void *user_data)
{ {
switch (type) switch (type)
{ {
default: default:
print_message("hook_mem_invalid: UC_HOOK_MEM_INVALID type: %d at 0x%" PRIx64 "\n", type, addr); break; print_message("hook_mem_invalid: UC_HOOK_MEM_INVALID type: %d at 0x%" PRIx64 "\n", type, addr); break;
case UC_MEM_READ_UNMAPPED: case UC_MEM_READ_UNMAPPED:
print_message("hook_mem_invalid: Read from invalid memory at 0x%" PRIx64 ", data size = %u\n", addr, size); break; print_message("hook_mem_invalid: Read from invalid memory at 0x%" PRIx64 ", data size = %u\n", addr, size); break;
case UC_MEM_WRITE_UNMAPPED: case UC_MEM_WRITE_UNMAPPED:
print_message("hook_mem_invalid: Write to invalid memory at 0x%" PRIx64 ", data size = %u, data value = 0x%" PRIx64 "\n", addr, size, value); break; print_message("hook_mem_invalid: Write to invalid memory at 0x%" PRIx64 ", data size = %u, data value = 0x%" PRIx64 "\n", addr, size, value); break;
case UC_MEM_FETCH_PROT: case UC_MEM_FETCH_PROT:
print_message("hook_mem_invalid: Fetch from non-executable memory at 0x%" PRIx64 "\n", addr); break; print_message("hook_mem_invalid: Fetch from non-executable memory at 0x%" PRIx64 "\n", addr); break;
case UC_MEM_WRITE_PROT: case UC_MEM_WRITE_PROT:
print_message("hook_mem_invalid: Write to non-writeable memory at 0x%" PRIx64 ", data size = %u, data value = 0x%" PRIx64 "\n", addr, size, value); break; print_message("hook_mem_invalid: Write to non-writeable memory at 0x%" PRIx64 ", data size = %u, data value = 0x%" PRIx64 "\n", addr, size, value); break;
case UC_MEM_READ_PROT: case UC_MEM_READ_PROT:
print_message("hook_mem_invalid: Read from non-readable memory at 0x%" PRIx64 ", data size = %u\n", addr, size); break; print_message("hook_mem_invalid: Read from non-readable memory at 0x%" PRIx64 ", data size = %u\n", addr, size); break;
} }
return false; return false;
} }
#define ADDR_CODE 0x100000 #define ADDR_CODE 0x100000
@ -123,311 +123,311 @@ bool hook_mem_invalid(uc_engine *uc, uc_mem_type type, uint64_t addr, int size,
static void test_i386_shl_cl(void **state) static void test_i386_shl_cl(void **state)
{ {
uc_engine *uc; uc_engine *uc;
uc_hook trace1; uc_hook trace1;
block b; block b;
// Initialize emulator in X86-32bit mode // Initialize emulator in X86-32bit mode
OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc)); OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc));
OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL)); OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL));
initRegisters(uc); initRegisters(uc);
BLOCK_START(b); BLOCK_START(b);
BLOCK_ADD( "mov ebx, 3Ch", V(0xBB, 0x3C, 0x00, 0x00, 0x00)); BLOCK_ADD( "mov ebx, 3Ch", V(0xBB, 0x3C, 0x00, 0x00, 0x00));
BLOCK_ADD_CHECK("mov cl, 2", V(0xB1, 0x02), V(V(UC_X86_REG_EBX, 0x3C, NO_MASK))); BLOCK_ADD_CHECK("mov cl, 2", V(0xB1, 0x02), V(V(UC_X86_REG_EBX, 0x3C, NO_MASK)));
BLOCK_ADD_CHECK("shl ebx, cl", V(0xD3, 0xE3), V(V(UC_X86_REG_CL, 0x2, NO_MASK))); BLOCK_ADD_CHECK("shl ebx, cl", V(0xD3, 0xE3), V(V(UC_X86_REG_CL, 0x2, NO_MASK)));
BLOCK_ADD_CHECK("lahf", V(0x9F), V(V(UC_X86_REG_EBX, 0xF0, NO_MASK), V(UC_X86_REG_EFLAGS, 0x4, ALL_MASK))); BLOCK_ADD_CHECK("lahf", V(0x9F), V(V(UC_X86_REG_EBX, 0xF0, NO_MASK), V(UC_X86_REG_EFLAGS, 0x4, ALL_MASK)));
BLOCK_ADD_CHECK("int3", V(0xCC), V(V(UC_X86_REG_AH, 0x4, PF_MASK))); BLOCK_ADD_CHECK("int3", V(0xCC), V(V(UC_X86_REG_AH, 0x4, PF_MASK)));
BLOCK_END(); BLOCK_END();
loadBlock(uc, &b, ADDR_CODE); loadBlock(uc, &b, ADDR_CODE);
OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &b, 1, 0)); OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &b, 1, 0));
OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0)); OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0));
// emulate machine code in infinite time // emulate machine code in infinite time
OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + b.size, 0, 0)); OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + b.size, 0, 0));
freeBlock(&b); freeBlock(&b);
uc_close(uc); uc_close(uc);
} }
static void test_i386_shl_imm(void **state) static void test_i386_shl_imm(void **state)
{ {
uc_engine *uc; uc_engine *uc;
uc_hook trace1; uc_hook trace1;
block b; block b;
// Initialize emulator in X86-32bit mode // Initialize emulator in X86-32bit mode
OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc)); OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc));
OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL)); OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL));
initRegisters(uc); initRegisters(uc);
BLOCK_START(b); BLOCK_START(b);
BLOCK_ADD( "mov ebx, 3Ch", V(0xBB, 0x3C, 0x00, 0x00, 0x00)); BLOCK_ADD( "mov ebx, 3Ch", V(0xBB, 0x3C, 0x00, 0x00, 0x00));
BLOCK_ADD( "shl ebx, 2", V(0xC1, 0xE3, 0x02)); BLOCK_ADD( "shl ebx, 2", V(0xC1, 0xE3, 0x02));
BLOCK_ADD_CHECK("lahf", V(0x9F), V(V(UC_X86_REG_EBX, 0xF0, NO_MASK), V(UC_X86_REG_EFLAGS, 0x4, ALL_MASK))); BLOCK_ADD_CHECK("lahf", V(0x9F), V(V(UC_X86_REG_EBX, 0xF0, NO_MASK), V(UC_X86_REG_EFLAGS, 0x4, ALL_MASK)));
BLOCK_ADD_CHECK("int3", V(0xCC), V(V(UC_X86_REG_AH, 0x4, PF_MASK))); BLOCK_ADD_CHECK("int3", V(0xCC), V(V(UC_X86_REG_AH, 0x4, PF_MASK)));
BLOCK_END(); BLOCK_END();
loadBlock(uc, &b, ADDR_CODE); loadBlock(uc, &b, ADDR_CODE);
OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &b, 1, 0)); OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &b, 1, 0));
OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0)); OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0));
// emulate machine code in infinite time // emulate machine code in infinite time
OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + b.size, 0, 0)); OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + b.size, 0, 0));
freeBlock(&b); freeBlock(&b);
uc_close(uc); uc_close(uc);
} }
static void test_i386_enter_leave(void **state) static void test_i386_enter_leave(void **state)
{ {
uc_engine *uc; uc_engine *uc;
uc_hook trace1; uc_hook trace1;
block b; block b;
// Initialize emulator in X86-32bit mode // Initialize emulator in X86-32bit mode
OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc)); OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc));
OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL)); OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL));
OK(uc_mem_map(uc, ADDR_STACK - 0x1000, 0x1000, UC_PROT_ALL)); OK(uc_mem_map(uc, ADDR_STACK - 0x1000, 0x1000, UC_PROT_ALL));
initRegisters(uc); initRegisters(uc);
BLOCK_START(b); BLOCK_START(b);
BLOCK_ADD( "mov esp, 0x200000", V(0xBC, 0x00, 0x00, 0x20, 0x00)); BLOCK_ADD( "mov esp, 0x200000", V(0xBC, 0x00, 0x00, 0x20, 0x00));
BLOCK_ADD_CHECK("mov eax, 1", V(0xB8, 0x01, 0x00, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000, NO_MASK))); BLOCK_ADD_CHECK("mov eax, 1", V(0xB8, 0x01, 0x00, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000, NO_MASK)));
BLOCK_ADD_CHECK("call 0x100015", V(0xE8, 0x06, 0x00, 0x00, 0x00), V(V(UC_X86_REG_EAX, 0x1, NO_MASK))); BLOCK_ADD_CHECK("call 0x100015", V(0xE8, 0x06, 0x00, 0x00, 0x00), V(V(UC_X86_REG_EAX, 0x1, NO_MASK)));
BLOCK_ADD_CHECK("mov eax, 3", V(0xB8, 0x03, 0x00, 0x00, 0x00), V(V(UC_X86_REG_EAX, 0x2, NO_MASK))); BLOCK_ADD_CHECK("mov eax, 3", V(0xB8, 0x03, 0x00, 0x00, 0x00), V(V(UC_X86_REG_EAX, 0x2, NO_MASK)));
BLOCK_ADD_CHECK("int3", V(0xCC), V(V(UC_X86_REG_EAX, 0x3, NO_MASK))); BLOCK_ADD_CHECK("int3", V(0xCC), V(V(UC_X86_REG_EAX, 0x3, NO_MASK)));
BLOCK_ADD_CHECK("enter 0x10,0", V(0xC8, 0x10, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK))); BLOCK_ADD_CHECK("enter 0x10,0", V(0xC8, 0x10, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK)));
BLOCK_ADD_CHECK("mov eax, 2", V(0xB8, 0x02, 0x00, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000 - 4 - 4 - 0x10, NO_MASK), V(UC_X86_REG_EBP, 0x200000 - 4 - 4, NO_MASK))); BLOCK_ADD_CHECK("mov eax, 2", V(0xB8, 0x02, 0x00, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000 - 4 - 4 - 0x10, NO_MASK), V(UC_X86_REG_EBP, 0x200000 - 4 - 4, NO_MASK)));
BLOCK_ADD_CHECK("leave", V(0xC9), V(V(UC_X86_REG_EAX, 0x2, NO_MASK))); BLOCK_ADD_CHECK("leave", V(0xC9), V(V(UC_X86_REG_EAX, 0x2, NO_MASK)));
BLOCK_ADD_CHECK("ret", V(0xC3), V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK))); BLOCK_ADD_CHECK("ret", V(0xC3), V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK)));
BLOCK_END(); BLOCK_END();
loadBlock(uc, &b, ADDR_CODE); loadBlock(uc, &b, ADDR_CODE);
OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &b, 1, 0)); OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &b, 1, 0));
OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0)); OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0));
// emulate machine code in infinite time // emulate machine code in infinite time
OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + b.size, 0, 0)); OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + b.size, 0, 0));
freeBlock(&b); freeBlock(&b);
uc_close(uc); uc_close(uc);
} }
static void test_i386_enter_nested_leave(void **state) static void test_i386_enter_nested_leave(void **state)
{ {
uc_engine *uc; uc_engine *uc;
uc_hook trace1; uc_hook trace1;
block b; block b;
// Initialize emulator in X86-32bit mode // Initialize emulator in X86-32bit mode
OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc)); OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc));
OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL)); OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL));
OK(uc_mem_map(uc, ADDR_STACK - 0x1000, 0x1000, UC_PROT_ALL)); OK(uc_mem_map(uc, ADDR_STACK - 0x1000, 0x1000, UC_PROT_ALL));
initRegisters(uc); initRegisters(uc);
BLOCK_START(b); BLOCK_START(b);
BLOCK_ADD( "mov esp, 0x200000", V(0xBC, 0x00, 0x00, 0x20, 0x00)); BLOCK_ADD( "mov esp, 0x200000", V(0xBC, 0x00, 0x00, 0x20, 0x00));
BLOCK_ADD_CHECK("mov eax, 1", V(0xB8, 0x01, 0x00, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000, NO_MASK))); BLOCK_ADD_CHECK("mov eax, 1", V(0xB8, 0x01, 0x00, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000, NO_MASK)));
BLOCK_ADD_CHECK("call 0x100015", V(0xE8, 0x06, 0x00, 0x00, 0x00), V(V(UC_X86_REG_EAX, 0x1, NO_MASK))); BLOCK_ADD_CHECK("call 0x100015", V(0xE8, 0x06, 0x00, 0x00, 0x00), V(V(UC_X86_REG_EAX, 0x1, NO_MASK)));
BLOCK_ADD_CHECK("mov eax, 3", V(0xB8, 0x03, 0x00, 0x00, 0x00), V(V(UC_X86_REG_EAX, 0x2, NO_MASK))); BLOCK_ADD_CHECK("mov eax, 3", V(0xB8, 0x03, 0x00, 0x00, 0x00), V(V(UC_X86_REG_EAX, 0x2, NO_MASK)));
BLOCK_ADD_CHECK("int3", V(0xCC), V(V(UC_X86_REG_EAX, 0x3, NO_MASK))); BLOCK_ADD_CHECK("int3", V(0xCC), V(V(UC_X86_REG_EAX, 0x3, NO_MASK)));
BLOCK_ADD_CHECK("mov ebp, esp", V(0x89, 0xE5), V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK))); BLOCK_ADD_CHECK("mov ebp, esp", V(0x89, 0xE5), V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK)));
BLOCK_ADD_CHECK("enter 0x10,1", V(0xC8, 0x10, 0x00, 0x01), V(V(UC_X86_REG_EBP, 0x200000 - 4, NO_MASK))); BLOCK_ADD_CHECK("enter 0x10,1", V(0xC8, 0x10, 0x00, 0x01), V(V(UC_X86_REG_EBP, 0x200000 - 4, NO_MASK)));
BLOCK_ADD_CHECK("mov eax, 2", V(0xB8, 0x02, 0x00, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000 - 4 - 2*4 - 0x10, NO_MASK), V(UC_X86_REG_EBP, 0x200000 - 4 - 4, NO_MASK))); BLOCK_ADD_CHECK("mov eax, 2", V(0xB8, 0x02, 0x00, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000 - 4 - 2*4 - 0x10, NO_MASK), V(UC_X86_REG_EBP, 0x200000 - 4 - 4, NO_MASK)));
BLOCK_ADD_CHECK("leave", V(0xC9), V(V(UC_X86_REG_EAX, 0x2, NO_MASK))); BLOCK_ADD_CHECK("leave", V(0xC9), V(V(UC_X86_REG_EAX, 0x2, NO_MASK)));
BLOCK_ADD_CHECK("ret", V(0xC3), V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK))); BLOCK_ADD_CHECK("ret", V(0xC3), V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK)));
BLOCK_END(); BLOCK_END();
loadBlock(uc, &b, ADDR_CODE); loadBlock(uc, &b, ADDR_CODE);
OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &b, 1, 0)); OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &b, 1, 0));
OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0)); OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0));
// emulate machine code in infinite time // emulate machine code in infinite time
OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + b.size, 0, 0)); OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + b.size, 0, 0));
freeBlock(&b); freeBlock(&b);
uc_close(uc); uc_close(uc);
} }
/******************************************************************************/ /******************************************************************************/
int main(void) { int main(void) {
const struct CMUnitTest tests[] = { const struct CMUnitTest tests[] = {
cmocka_unit_test(test_i386_shl_cl), cmocka_unit_test(test_i386_shl_cl),
cmocka_unit_test(test_i386_shl_imm), cmocka_unit_test(test_i386_shl_imm),
cmocka_unit_test(test_i386_enter_leave), cmocka_unit_test(test_i386_enter_leave),
cmocka_unit_test(test_i386_enter_nested_leave), cmocka_unit_test(test_i386_enter_nested_leave),
}; };
return cmocka_run_group_tests(tests, NULL, NULL); return cmocka_run_group_tests(tests, NULL, NULL);
} }
/******************************************************************************/ /******************************************************************************/
instruction* newInstruction(const uint8_t * _code, uint32_t _codeSize, const char* _asmStr, const reg_value* _values, uint32_t _nbValues) instruction* newInstruction(const uint8_t * _code, uint32_t _codeSize, const char* _asmStr, const reg_value* _values, uint32_t _nbValues)
{ {
instruction* inst = (instruction*)malloc(sizeof(instruction)); instruction* inst = (instruction*)malloc(sizeof(instruction));
inst->asmStr = _asmStr; inst->asmStr = _asmStr;
memcpy(inst->code, _code, _codeSize); memcpy(inst->code, _code, _codeSize);
inst->codeSize = _codeSize; inst->codeSize = _codeSize;
inst->nbValues = 0; inst->nbValues = 0;
if (_values) if (_values)
{ {
inst->values = (reg_value*)malloc(_nbValues*sizeof(reg_value)); inst->values = (reg_value*)malloc(_nbValues*sizeof(reg_value));
memcpy(inst->values, _values, _nbValues*sizeof(reg_value)); memcpy(inst->values, _values, _nbValues*sizeof(reg_value));
inst->nbValues = _nbValues; inst->nbValues = _nbValues;
} }
return inst; return inst;
} }
void addInstructionToBlock(block* _b, instruction* _i) void addInstructionToBlock(block* _b, instruction* _i)
{ {
_b->insts[_b->nbInsts++] = _i; _b->insts[_b->nbInsts++] = _i;
} }
uint32_t loadBlock(uc_engine *_uc, block* _block, uint32_t _at) uint32_t loadBlock(uc_engine *_uc, block* _block, uint32_t _at)
{ {
uint32_t i, j, offset; uint32_t i, j, offset;
for (i = 0, offset = 0; i < _block->nbInsts; i++) for (i = 0, offset = 0; i < _block->nbInsts; i++)
{ {
const uint32_t codeSize = _block->insts[i]->codeSize; const uint32_t codeSize = _block->insts[i]->codeSize;
const uint8_t* code = _block->insts[i]->code; const uint8_t* code = _block->insts[i]->code;
_block->insts[i]->addr = _at + offset; _block->insts[i]->addr = _at + offset;
print_message("load: %08X: ", _block->insts[i]->addr); print_message("load: %08X: ", _block->insts[i]->addr);
for (j = 0; j < codeSize; j++) print_message("%02X ", code[j]); for (j = 0; j < codeSize; j++) print_message("%02X ", code[j]);
for (j = 0; j < 15 - codeSize; j++) print_message(" "); for (j = 0; j < 15 - codeSize; j++) print_message(" ");
print_message("%s\n", _block->insts[i]->asmStr); print_message("%s\n", _block->insts[i]->asmStr);
OK(uc_mem_write(_uc, _at + offset, code, codeSize)); OK(uc_mem_write(_uc, _at + offset, code, codeSize));
offset += codeSize; offset += codeSize;
} }
_block->size = offset; _block->size = offset;
return offset; return offset;
} }
void freeBlock(block* _block) void freeBlock(block* _block)
{ {
uint32_t i; uint32_t i;
for (i = 0; i < _block->nbInsts; i++) for (i = 0; i < _block->nbInsts; i++)
{ {
if (_block->insts[i]->nbValues > 0) if (_block->insts[i]->nbValues > 0)
free(_block->insts[i]->values); free(_block->insts[i]->values);
free(_block->insts[i]); free(_block->insts[i]);
} }
} }
void initRegisters(uc_engine *uc) void initRegisters(uc_engine *uc)
{ {
// initialize machine registers // initialize machine registers
uint32_t zero = 0; uint32_t zero = 0;
OK(uc_reg_write(uc, UC_X86_REG_EAX, &zero)); OK(uc_reg_write(uc, UC_X86_REG_EAX, &zero));
OK(uc_reg_write(uc, UC_X86_REG_EBX, &zero)); OK(uc_reg_write(uc, UC_X86_REG_EBX, &zero));
OK(uc_reg_write(uc, UC_X86_REG_ECX, &zero)); OK(uc_reg_write(uc, UC_X86_REG_ECX, &zero));
OK(uc_reg_write(uc, UC_X86_REG_EDX, &zero)); OK(uc_reg_write(uc, UC_X86_REG_EDX, &zero));
OK(uc_reg_write(uc, UC_X86_REG_EBP, &zero)); OK(uc_reg_write(uc, UC_X86_REG_EBP, &zero));
OK(uc_reg_write(uc, UC_X86_REG_ESP, &zero)); OK(uc_reg_write(uc, UC_X86_REG_ESP, &zero));
OK(uc_reg_write(uc, UC_X86_REG_EDI, &zero)); OK(uc_reg_write(uc, UC_X86_REG_EDI, &zero));
OK(uc_reg_write(uc, UC_X86_REG_ESI, &zero)); OK(uc_reg_write(uc, UC_X86_REG_ESI, &zero));
OK(uc_reg_write(uc, UC_X86_REG_EFLAGS, &zero)); OK(uc_reg_write(uc, UC_X86_REG_EFLAGS, &zero));
} }
instruction* getInstruction(block* _block, uint32_t _addr) instruction* getInstruction(block* _block, uint32_t _addr)
{ {
uint32_t i; uint32_t i;
for (i = 0; i < _block->nbInsts; i++) for (i = 0; i < _block->nbInsts; i++)
{ {
if (_block->insts[i]->addr == _addr) if (_block->insts[i]->addr == _addr)
return _block->insts[i]; return _block->insts[i];
} }
return NULL; return NULL;
} }
const char* getRegisterName(uint32_t _regid) const char* getRegisterName(uint32_t _regid)
{ {
switch (_regid) switch (_regid)
{ {
//8 //8
case UC_X86_REG_AH: return "AH"; case UC_X86_REG_AH: return "AH";
case UC_X86_REG_AL: return "AL"; case UC_X86_REG_AL: return "AL";
case UC_X86_REG_BH: return "BH"; case UC_X86_REG_BH: return "BH";
case UC_X86_REG_BL: return "BL"; case UC_X86_REG_BL: return "BL";
case UC_X86_REG_CL: return "CL"; case UC_X86_REG_CL: return "CL";
case UC_X86_REG_CH: return "CH"; case UC_X86_REG_CH: return "CH";
case UC_X86_REG_DH: return "DH"; case UC_X86_REG_DH: return "DH";
case UC_X86_REG_DL: return "DL"; case UC_X86_REG_DL: return "DL";
//16 //16
case UC_X86_REG_AX: return "AX"; case UC_X86_REG_AX: return "AX";
case UC_X86_REG_BX: return "BX"; case UC_X86_REG_BX: return "BX";
case UC_X86_REG_CX: return "CX"; case UC_X86_REG_CX: return "CX";
case UC_X86_REG_DX: return "DX"; case UC_X86_REG_DX: return "DX";
//32 //32
case UC_X86_REG_EAX: return "EAX"; case UC_X86_REG_EAX: return "EAX";
case UC_X86_REG_EBX: return "EBX"; case UC_X86_REG_EBX: return "EBX";
case UC_X86_REG_ECX: return "ECX"; case UC_X86_REG_ECX: return "ECX";
case UC_X86_REG_EDX: return "EDX"; case UC_X86_REG_EDX: return "EDX";
case UC_X86_REG_EDI: return "EDI"; case UC_X86_REG_EDI: return "EDI";
case UC_X86_REG_ESI: return "ESI"; case UC_X86_REG_ESI: return "ESI";
case UC_X86_REG_EBP: return "EBP"; case UC_X86_REG_EBP: return "EBP";
case UC_X86_REG_ESP: return "ESP"; case UC_X86_REG_ESP: return "ESP";
case UC_X86_REG_EIP: return "EIP"; case UC_X86_REG_EIP: return "EIP";
case UC_X86_REG_EFLAGS: return "EFLAGS"; case UC_X86_REG_EFLAGS: return "EFLAGS";
default: fail(); default: fail();
} }
return "UNKNOWN"; return "UNKNOWN";
} }
uint32_t getRegisterValue(uc_engine *uc, uint32_t _regid) uint32_t getRegisterValue(uc_engine *uc, uint32_t _regid)
{ {
switch (_regid) switch (_regid)
{ {
//8 //8
case UC_X86_REG_AH: case UC_X86_REG_AL: case UC_X86_REG_AH: case UC_X86_REG_AL:
case UC_X86_REG_BH: case UC_X86_REG_BL: case UC_X86_REG_BH: case UC_X86_REG_BL:
case UC_X86_REG_CL: case UC_X86_REG_CH: case UC_X86_REG_CL: case UC_X86_REG_CH:
case UC_X86_REG_DH: case UC_X86_REG_DL: case UC_X86_REG_DH: case UC_X86_REG_DL:
{ {
uint8_t val = 0; uint8_t val = 0;
OK(uc_reg_read(uc, _regid, &val)); OK(uc_reg_read(uc, _regid, &val));
return val; return val;
} }
//16 //16
case UC_X86_REG_AX: case UC_X86_REG_BX: case UC_X86_REG_AX: case UC_X86_REG_BX:
case UC_X86_REG_CX: case UC_X86_REG_DX: case UC_X86_REG_CX: case UC_X86_REG_DX:
{ {
uint16_t val = 0; uint16_t val = 0;
OK(uc_reg_read(uc, _regid, &val)); OK(uc_reg_read(uc, _regid, &val));
return val; return val;
} }
//32 //32
case UC_X86_REG_EAX: case UC_X86_REG_EBX: case UC_X86_REG_EAX: case UC_X86_REG_EBX:
case UC_X86_REG_ECX: case UC_X86_REG_EDX: case UC_X86_REG_ECX: case UC_X86_REG_EDX:
case UC_X86_REG_EDI: case UC_X86_REG_ESI: case UC_X86_REG_EDI: case UC_X86_REG_ESI:
case UC_X86_REG_EBP: case UC_X86_REG_ESP: case UC_X86_REG_EBP: case UC_X86_REG_ESP:
case UC_X86_REG_EIP: case UC_X86_REG_EFLAGS: case UC_X86_REG_EIP: case UC_X86_REG_EFLAGS:
{ {
uint32_t val = 0; uint32_t val = 0;
OK(uc_reg_read(uc, _regid, &val)); OK(uc_reg_read(uc, _regid, &val));
return val; return val;
} }
default: fail(); default: fail();
} }
return 0; return 0;
} }

22
uc.c
View file

@ -268,15 +268,15 @@ uc_err uc_open(uc_arch arch, uc_mode mode, uc_engine **result)
if (uc->reg_reset) if (uc->reg_reset)
uc->reg_reset(uc); uc->reg_reset(uc);
// init winsock sockets so we can use select() for usleep() implementation // init winsock sockets so we can use select() for usleep() implementation
#ifdef _MSC_VER #ifdef _MSC_VER
{ {
WSADATA wsa_data; WSADATA wsa_data;
WSAStartup(0x202, &wsa_data); WSAStartup(0x202, &wsa_data);
} }
#endif #endif
return UC_ERR_OK; return UC_ERR_OK;
} else { } else {
return UC_ERR_ARCH; return UC_ERR_ARCH;
} }
@ -355,14 +355,14 @@ uc_err uc_close(uc_engine *uc)
memset(uc, 0, sizeof(*uc)); memset(uc, 0, sizeof(*uc));
free(uc); free(uc);
// free winsock sockets - used so we can use select() for usleep() implementation // free winsock sockets - used so we can use select() for usleep() implementation
#ifdef _MSC_VER #ifdef _MSC_VER
{ {
WSACleanup(); WSACleanup();
} }
#endif #endif
return UC_ERR_OK; return UC_ERR_OK;
} }