yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2024-12-23 19:45:29 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/arm: Convert get_phys_addr_pmsav5() to not return FSC values

Browse source 
Make get_phys_addr_pmsav5() return a fault type in the ARMMMUFaultInfo
structure, which we convert to the FSC at the callsite.

Note that PMSAv5 does not define any guest-visible fault status
register, so the different "fsr" values we were previously
returning are entirely arbitrary. So we can just switch to using
the most appropriae fi->type values without worrying that we
need to special-case FaultInfo->FSC conversion for PMSAv5.

Backports commit 53a4e5c5b07b2f50c538511b74b0d3d4964695ea from qemu
This commit is contained in:
Peter Maydell 2018-03-05 13:54:03 -05:00 committed by Lioncash
parent 013e7873ee
commit 79b2c4b1e7
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 13 additions and 7 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

20
qemu/target/arm/helper.c
View file

@ -8728,7 +8728,8 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address,
static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
hwaddr *phys_ptr, int *prot, uint32_t *fsr)
hwaddr *phys_ptr, int *prot,
ARMMMUFaultInfo *fi)
{
int n;
uint32_t mask;
@ -8758,7 +8759,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
}
}
if (n < 0) {
*fsr = 2;
fi->type = ARMFault_Background;
return true;
}
@ -8770,11 +8771,13 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
mask = (mask >> (n * 4)) & 0xf;
switch (mask) {
case 0:
*fsr = 1;
fi->type = ARMFault_Permission;
fi->level = 1;
return true;
case 1:
if (is_user) {
*fsr = 1;
fi->type = ARMFault_Permission;
fi->level = 1;
return true;
}
*prot = PAGE_READ | PAGE_WRITE;
@ -8790,7 +8793,8 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
break;
case 5:
if (is_user) {
*fsr = 1;
fi->type = ARMFault_Permission;
fi->level = 1;
return true;
}
*prot = PAGE_READ;
@ -8800,7 +8804,8 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address,
break;
default:
/* Bad permission. */
*fsr = 1;
fi->type = ARMFault_Permission;
fi->level = 1;
return true;
}
*prot |= PAGE_EXEC;
@ -9003,7 +9008,8 @@ static bool get_phys_addr(CPUARMState *env, target_ulong address,
} else {
/* Pre-v7 MPU */
ret = get_phys_addr_pmsav5(env, address, access_type, mmu_idx,
phys_ptr, prot, fsr);
phys_ptr, prot, fi);
*fsr = arm_fi_to_sfsc(fi);
}
qemu_log_mask(CPU_LOG_MMU, "PMSA MPU lookup for %s at 0x%08" PRIx32
" mmu_idx %u -> %s (prot %c%c%c)\n",